DAWEI CHIEN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
SPM: mt8183: support spm suspend in coreboot
Load SPM firmware and init SPM in core boot
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 2,499 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 0a79ed7..bc8085b 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -50,11 +50,22 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += sspm.c +ramstage-y += spm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c
+cbfs-files-y += pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-type := raw +pcm_allinone_lp4_3200.bin-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-type := raw +pcm_allinone_lp4_3733.bin-compression := $(CBFS_COMPRESS_FLAG) + CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 5e7770e..290f99c 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -473,24 +473,66 @@ u32 spm_ack_chk_latch4; };
+check_member(mtk_spm_regs, poweron_config_set, 0x0000); +check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); +check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); +check_member(mtk_spm_regs, spm_clk_con, 0x000c); +check_member(mtk_spm_regs, pcm_con0, 0x0018); +check_member(mtk_spm_regs, pcm_con1, 0x001c); +check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); +check_member(mtk_spm_regs, pcm_im_len, 0x0024); +check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); +check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); +check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); +check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); +check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); +check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); +check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); +check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); +check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); +check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); +check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); +check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); +check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); +check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); +check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); +check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); +check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); +check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); +check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); +check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); +check_member(mtk_spm_regs, spm_swint_clr, 0x0094); +check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); +check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); +check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); +check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8); check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); +check_member(mtk_spm_regs, pcm_reg1_data, 0x0104); +check_member(mtk_spm_regs, pcm_reg15_data, 0x013c); +check_member(mtk_spm_regs, spm_irq_sta, 0x0158); +check_member(mtk_spm_regs, pcm_fsm_sta, 0x0178); check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); check_member(mtk_spm_regs, vde_pwr_con, 0x0300); +check_member(mtk_spm_regs, sysrom_con, 0x0354); check_member(mtk_spm_regs, ufs_sram_con, 0x036c); check_member(mtk_spm_regs, dummy_sram_con, 0x0380); check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); +check_member(mtk_spm_regs, spm_mas_pause_mask_b, 0x0408); +check_member(mtk_spm_regs, spm_mas_pause2_mask_b, 0x040c); check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); check_member(mtk_spm_regs, root_cputop_addr, 0x0570); check_member(mtk_spm_regs, cpu_spare_con, 0x0580); check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); +check_member(mtk_spm_regs, spare_ack_mask, 0x06f4); check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); +check_member(mtk_spm_regs, spare_src_req_mask, 0x06c0); check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); diff --git a/src/soc/mediatek/mt8183/include/soc/spm_init.h b/src/soc/mediatek/mt8183/include/soc/spm_init.h new file mode 100644 index 0000000..7cc4f9f --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/spm_init.h @@ -0,0 +1,2123 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SPM_INIT__ +#define __SPM_INIT__ + +#include <arch/barrier.h> +#include <arch/mmio.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <stdint.h> +#include <types.h> + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ +#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ +#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define WFI_OP_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define MM_MASK_B_LSB (1U << 16) /* 2b */ +#define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ +#define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ +#define MD_MASK_B_LSB (1U << 20) /* 2b */ +#define SSPM_MASK_B_LSB (1U << 22) /* 1b */ +#define SCP_MASK_B_LSB (1U << 23) /* 1b */ +#define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ +#define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ +#define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ +#define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ +#define CONN_MASK_B_LSB (1U << 28) /* 1b */ +#define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_IM_PTR (0x10006000+0x020) */ +#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ +/* PCM_IM_LEN (0x10006000+0x024) */ +#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ +/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ +#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ +/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ +#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ +#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ +#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ +#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ +#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ +#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ +#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ +#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ +#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ +#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ +#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ +#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ +#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ +#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ +#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ +#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ +#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ +#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ +/* SPM_SRAM_RSV_CON (0x10006000+0x088) */ +#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ +/* SCP_SPM_MAILBOX (0x10006000+0x09C) */ +#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ +#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ +#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ +#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ +#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ +#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ +#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ +#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ +#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ +/* SPM_SCP_IRQ (0x10006000+0x0AC) */ +#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ +#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ +#define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ +#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ +#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ +#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ +#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ +#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ +#define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ +#define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ +#define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ +#define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ +#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ +#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ +#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ +#define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ +#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ +#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ +#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ +#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ +#define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ +#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ +#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ +#define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ +#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ +#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ +/* SCP_CLK_CON (0x10006000+0x0D0) */ +#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ +#define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ +#define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ +/* PCM_DEBUG_CON (0x10006000+0x0D4) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ +/* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ +#define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ +#define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ +/* AHB_BUS_CON (0x10006000+0x0DC) */ +#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ +#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ +/* SPM_SRC3_MASK (0x10006000+0x0E0) */ +#define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ +#define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ +#define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ +#define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ +/* SSPM_CLK_CON (0x10006000+0x0E8) */ +#define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG1_DATA (0x10006000+0x104) */ +#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG2_DATA (0x10006000+0x108) */ +#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG3_DATA (0x10006000+0x10C) */ +#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG4_DATA (0x10006000+0x110) */ +#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG5_DATA (0x10006000+0x114) */ +#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG6_DATA (0x10006000+0x118) */ +#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG7_DATA (0x10006000+0x11C) */ +#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG8_DATA (0x10006000+0x120) */ +#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG9_DATA (0x10006000+0x124) */ +#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG10_DATA (0x10006000+0x128) */ +#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG11_DATA (0x10006000+0x12C) */ +#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_DATA (0x10006000+0x130) */ +#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG13_DATA (0x10006000+0x134) */ +#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG14_DATA (0x10006000+0x138) */ +#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG15_DATA (0x10006000+0x13C) */ +#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ +#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ +#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ +#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ +#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ +/* PCM_TIMER_OUT (0x10006000+0x150) */ +#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* PCM_WDT_OUT (0x10006000+0x154) */ +#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ +/* SPM_IRQ_STA (0x10006000+0x158) */ +#define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +/* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ +/* SPM_WAKEUP_STA (0x10006000+0x15C) */ +#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ +#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_MISC (0x10006000+0x164) */ +#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ +#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ +/* BUS_PROTECT_RDY (0x10006000+0x168) */ +#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ +#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ +/* SUBSYS_IDLE_STA (0x10006000+0x170) */ +#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ +/* CPU_IDLE_STA (0x10006000+0x174) */ +#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ +#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ +#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ +#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ +#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ +#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ +#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ +#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ +#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ +#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ +#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ +#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ +/* PCM_FSM_STA (0x10006000+0x178) */ +#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ +#define PC_STATE_LSB (1U << 4) /* 3b */ +#define IM_STATE_LSB (1U << 7) /* 3b */ +#define MASTER_STATE_LSB (1U << 10) /* 5b */ +#define EVENT_FSM_LSB (1U << 15) /* 3b */ +#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ +#define PCM_KICK_LSB (1U << 21) /* 1b */ +#define IM_KICK_LSB (1U << 22) /* 1b */ +#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ +#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ +/* SRC_REQ_STA (0x10006000+0x17C) */ +#define SRC_REQ_STA_LSB (1U << 0) /* 32b */ +/* PWR_STATUS (0x10006000+0x180) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_2ND (0x10006000+0x184) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS (0x10006000+0x188) */ +#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ +#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* MISC_STA (0x10006000+0x190) */ +#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ +/* SPM_SRC_RDY_STA (0x10006000+0x194) */ +#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ +/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ +#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ +#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ +#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ +#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ +#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ +#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ +#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ +#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ +#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ +#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_STA (0x10006000+0x1C8) */ +#define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ +/* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ +#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ +#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ +/* SRC_DDREN_STA (0x10006000+0x1E0) */ +#define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ +/* MCU_PWR_CON (0x10006000+0x200) */ +#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ +#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ +#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ +#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ +#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ +#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ +#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ +#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ +#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ +#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ +#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ +#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ +#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ +#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ +#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ +#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ +#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +#define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ +/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ +#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +/* BYPASS_SPMC (0x10006000+0x2B4) */ +#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ +/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ +#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ +#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ +/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ +#define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ +#define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ +#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ +#define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ +#define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ +/* SPMC_IN_RET (0x10006000+0x2C0) */ +#define SPMC_STATUS_LSB (1U << 0) /* 8b */ +/* VDE_PWR_CON (0x10006000+0x300) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VEN_PWR_CON (0x10006000+0x304) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* ISP_PWR_CON (0x10006000+0x308) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DIS_PWR_CON (0x10006000+0x30C) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE1_PWR_CON (0x10006000+0x310) */ +#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* AUDIO_PWR_CON (0x10006000+0x314) */ +#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* IFR_PWR_CON (0x10006000+0x318) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DPY_PWR_CON (0x10006000+0x31C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MD1_PWR_CON (0x10006000+0x320) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ +/* VPU_TOP_PWR_CON (0x10006000+0x324) */ +#define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CONN_PWR_CON (0x10006000+0x32C) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VPU_CORE2_PWR_CON (0x10006000+0x330) */ +#define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ +#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_PWR_CON (0x10006000+0x338) */ +#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ +#define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* VPU_CORE1_PWR_CON (0x10006000+0x340) */ +#define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CAM_PWR_CON (0x10006000+0x344) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_2D_PWR_CON (0x10006000+0x348) */ +#define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ +#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* SYSRAM_CON (0x10006000+0x350) */ +#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* SYSROM_CON (0x10006000+0x354) */ +#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ +/* SSPM_SRAM_CON (0x10006000+0x358) */ +#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* SCP_SRAM_CON (0x10006000+0x35C) */ +#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* UFS_SRAM_CON (0x10006000+0x36C) */ +#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ +#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ +/* DUMMY_SRAM_CON (0x10006000+0x380) */ +#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ +#define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ +#define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ +/* MD_SRAM_ISO_CON (0x10006000+0x394) */ +#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ +/* MD_EXTRA_PWR_CON (0x10006000+0x398) */ +#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ +#define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ +/* EXT_BUCK_CON (0x10006000+0x3A0) */ +#define RG_VA09_ON_LSB (1U << 0) /* 1b */ +/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ +#define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON (0x10006000+0x400) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ +#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ +/* SPM_MDBSI_CON (0x10006000+0x404) */ +#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ +/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ +#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ +#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BSI_GEN (0x10006000+0x410) */ +#define SPM_BSI_START_LSB (1U << 0) /* 1b */ +/* SPM_BSI_EN_SR (0x10006000+0x414) */ +#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_CLK_SR (0x10006000+0x418) */ +#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D0_SR (0x10006000+0x41C) */ +#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D1_SR (0x10006000+0x420) */ +#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D2_SR (0x10006000+0x424) */ +#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ +/* SPM_AP_SEMA (0x10006000+0x428) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_SPM_SEMA (0x10006000+0x42C) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ +/* AP_MDSRC_REQ (0x10006000+0x430) */ +#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ +#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ +#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ +#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ +#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ +#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ +#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ +#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ +#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ +/* DPY_LP_CON (0x10006000+0x444) */ +#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ +/* CPU_DVFS_REQ (0x10006000+0x448) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ +/* SPM_EMI_BW_MODE (0x10006000+0x450) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ +#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ +#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ +/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ +/* ULPOSC_CON (0x10006000+0x458) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ +#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ +/* SPM2MM_CON (0x10006000+0x45C) */ +#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ +#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ +#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ +#define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ +#define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ +#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ +/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ +#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ +#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ +#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ +#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ +#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ +/* SPM_S1_MODE_CH (0x10006000+0x468) */ +#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ +#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ +/* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ +#define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ +#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ +#define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ +/* DRAMC_DMYRD_CON (0x10006000+0x478) */ +#define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ +#define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ +/* SPM_DRS_CON (0x10006000+0x47C) */ +#define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ +#define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ +#define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ +#define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ +/* SPM_SEMA_M0 (0x10006000+0x480) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M1 (0x10006000+0x484) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M2 (0x10006000+0x488) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M3 (0x10006000+0x48C) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M4 (0x10006000+0x490) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M5 (0x10006000+0x494) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M6 (0x10006000+0x498) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M7 (0x10006000+0x49C) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ +/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ +#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ +#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ +#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON (0x10006000+0x4B0) */ +#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ +#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ +#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ +/* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ +#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ +/* SPM_SSPM_IRQ (0x10006000+0x4C0) */ +#define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM2PMCU_INT (0x10006000+0x4C4) */ +#define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ +#define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ +#define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ +#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ +#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ +#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ +#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_INT (0x10006000+0x4E0) */ +#define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ +#define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ +#define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ +#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ +#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ +#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ +#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_CFG (0x10006000+0x4FC) */ +#define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ +#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ +#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ +#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ +#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_L2CFLUSH (0x10006000+0x554) */ +#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* MP1_L2CFLUSH (0x10006000+0x558) */ +#define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* CPU_PTPOD2_CON (0x10006000+0x560) */ +#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ +#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ +#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ +#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ +#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ +#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ +/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ +/* ROOT_CORE_ADDR (0x10006000+0x574) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON (0x10006000+0x580) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_SET (0x10006000+0x584) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ +#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ +#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ +#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ +#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_INT (0x10006000+0x5E0) */ +#define SW2SPM_INT_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_SET (0x10006000+0x5E4) */ +#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_CLR (0x10006000+0x5E8) */ +#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ +#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ +#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ +#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ +#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_CFG (0x10006000+0x5FC) */ +#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* SPM_SW_FLAG (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG (0x10006000+0x604) */ +#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_0 (0x10006000+0x608) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_1 (0x10006000+0x60C) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_2 (0x10006000+0x610) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_3 (0x10006000+0x614) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_4 (0x10006000+0x618) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_5 (0x10006000+0x61C) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON (0x10006000+0x620) */ +#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA (0x10006000+0x624) */ +#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ +/* SPM_RSV_CON1 (0x10006000+0x628) */ +#define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA1 (0x10006000+0x62C) */ +#define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ +/* SPM_PASR_DPD_0 (0x10006000+0x630) */ +#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_1 (0x10006000+0x634) */ +#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_2 (0x10006000+0x638) */ +#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ +#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON (0x10006000+0x640) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_SET (0x10006000+0x644) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_6 (0x10006000+0x64C) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_7 (0x10006000+0x650) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_8 (0x10006000+0x654) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_9 (0x10006000+0x658) */ +#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_10 (0x10006000+0x65C) */ +#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_18 (0x10006000+0x67C) */ +#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_19 (0x10006000+0x680) */ +#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ +/* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ +#define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ +#define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_SEL (0x10006000+0x698) */ +#define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ +/* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ +#define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ +#define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ +#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ +/* DVFS_ABORT_STA (0x10006000+0x6A8) */ +#define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ +#define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ +/* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ +#define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_DFS_LEVEL (0x10006000+0x6B0) */ +#define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ +/* SPM_DVS_LEVEL (0x10006000+0x6B4) */ +#define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +#define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ +#define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ +/* SPM_DVFS_MISC (0x10006000+0x6B8) */ +#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ +#define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ +#define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ +#define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ +#define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ +#define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ +#define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ +#define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ +#define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ +#define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ +#define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ +/* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ +#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +/* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ +#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ +#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ +/* SPARE_ACK_STA (0x10006000+0x6F0) */ +#define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1 (0x10006000+0x700) */ +#define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1_STA (0x10006000+0x704) */ +#define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD0 (0x10006000+0x710) */ +#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD1 (0x10006000+0x714) */ +#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD2 (0x10006000+0x718) */ +#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD3 (0x10006000+0x71C) */ +#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD4 (0x10006000+0x720) */ +#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD5 (0x10006000+0x724) */ +#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD6 (0x10006000+0x728) */ +#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD7 (0x10006000+0x72C) */ +#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD8 (0x10006000+0x730) */ +#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD9 (0x10006000+0x734) */ +#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD10 (0x10006000+0x738) */ +#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD11 (0x10006000+0x73C) */ +#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD12 (0x10006000+0x740) */ +#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD13 (0x10006000+0x744) */ +#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD14 (0x10006000+0x748) */ +#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD15 (0x10006000+0x74C) */ +#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ +#define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ +#define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ +#define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ +#define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_IN_FIX (0x10006000+0x790) */ +#define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ +#define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ +#define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_0 (0x10006000+0x800) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_1 (0x10006000+0x804) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_2 (0x10006000+0x808) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_4 (0x10006000+0x810) */ +#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_5 (0x10006000+0x814) */ +#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_6 (0x10006000+0x818) */ +#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ +#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_8 (0x10006000+0x820) */ +#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_9 (0x10006000+0x824) */ +#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0 (0x10006000+0x828) */ +#define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ +#define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2 (0x10006000+0x830) */ +#define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3 (0x10006000+0x834) */ +#define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_10 (0x10006000+0x838) */ +#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ +#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ +#define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ +#define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ +#define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ +#define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ +#define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ +#define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ +#define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ +#define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ +#define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ +#define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ +#define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ +#define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ +#define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ +#define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ +#define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ +#define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0 (0x10006000+0x880) */ +#define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0 (0x10006000+0x884) */ +#define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_12 (0x10006000+0x888) */ +#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ +#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ +#define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ +/* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ +#define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ +#define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ +#define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ +#define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ +#define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ +#define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ +#define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ +#define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ +/* SPM_ACK_CHK_CON (0x10006000+0x900) */ +#define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC (0x10006000+0x904) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL (0x10006000+0x908) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ +#define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA (0x10006000+0x910) */ +#define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ +#define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ +#define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ +#define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ +#define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ +#define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ +#define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ +#define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ +#define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ +#define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ +#define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ +#define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ +#define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ +#define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DIS_CPU_PDN (1U << 0) +#define SPM_FLAG_DIS_INFRA_PDN (1U << 1) +#define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) +#define SPM_FLAG_DIS_VCORE_DVS (1U << 3) +#define SPM_FLAG_DIS_VCORE_DFS (1U << 4) +#define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) +#define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) +#define SPM_FLAG_DIS_ATF_ABORT (1U << 7) +#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) +#define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) +#define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) +#define SPM_FLAG_SODI_CG_MODE (1U << 12) +#define SPM_FLAG_SODI_NO_EVENT (1U << 13) +#define SPM_FLAG_ENABLE_SODI3 (1U << 14) +#define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) +#define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) +#define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) +#define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) +#define SPM_FLAG_SUSPEND_OPTION (1U << 19) +#define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) +#define SPM_FLAG_SODI_OPTION (1U << 21) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) + +/* --- SPM Flag1 Define --- */ +#define SPM_FLAG1_RESERVED_BIT0 (1U << 0) +#define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) +#define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) +#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) +#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) +#define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) +#define SPM_FLAG1_DISABLE_MCDSR (1U << 6) +#define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) +#define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) +#define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) +#define SPM_FLAG1_RESERVED_BIT10 (1U << 10) +#define SPM_FLAG1_RESERVED_BIT11 (1U << 11) +#define SPM_FLAG1_RESERVED_BIT12 (1U << 12) +#define SPM_FLAG1_RESERVED_BIT13 (1U << 13) +#define SPM_FLAG1_RESERVED_BIT14 (1U << 14) +#define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) +#define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) +#define SPM_FLAG1_DIS_IMP_DIS (1U << 17) +#define SPM_FLAG1_DIS_IMP_COPY (1U << 18) +#define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) +#define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) +#define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) +#define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) +#define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) +#define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) +#define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) +#define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) +#define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) +#define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) +#define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) +#define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) +#define SPM_FLAG1_DIS_SW_MR4 (1U << 31) + +/* --- SPM DEBUG Define --- */ +#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) +#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) +#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) +#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) +#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) +#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) +#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) +#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) +#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) +#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) +#define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) +#define SPM_DBG_DEBUG_IDX_DPD (1U << 13) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) +#define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) +#define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) +#define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) +#define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) +#define SPM_DBG_RESERVED_BIT21 (1U << 21) +#define SPM_DBG_RESERVED_BIT22 (1U << 22) +#define SPM_DBG_RESERVED_BIT23 (1U << 23) +#define SPM_DBG_RESERVED_BIT24 (1U << 24) +#define SPM_DBG_RESERVED_BIT25 (1U << 25) +#define SPM_DBG_RESERVED_BIT26 (1U << 26) +#define SPM_DBG_SODI1_FLAG (1U << 27) +#define SPM_DBG_SODI3_FLAG (1U << 28) +#define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) +#define SPM_DBG_DEEPIDLE_FLAG (1U << 30) +#define SPM_DBG_SUSPEND_FLAG (1U << 31) + +/* --- SPM DEBUG1 Define --- */ +#define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) +#define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) +#define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) +#define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) +#define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) +#define SPM_DBG1_RESERVED_BIT5 (1U << 5) +#define SPM_DBG1_RESERVED_BIT6 (1U << 6) +#define SPM_DBG1_RESERVED_BIT7 (1U << 7) +#define SPM_DBG1_RESERVED_BIT8 (1U << 8) +#define SPM_DBG1_RESERVED_BIT9 (1U << 9) +#define SPM_DBG1_RESERVED_BIT10 (1U << 10) +#define SPM_DBG1_RESERVED_BIT11 (1U << 11) +#define SPM_DBG1_RESERVED_BIT12 (1U << 12) +#define SPM_DBG1_RESERVED_BIT13 (1U << 13) +#define SPM_DBG1_RESERVED_BIT14 (1U << 14) +#define SPM_DBG1_RESERVED_BIT15 (1U << 15) +#define SPM_DBG1_RESERVED_BIT16 (1U << 16) +#define SPM_DBG1_RESERVED_BIT17 (1U << 17) +#define SPM_DBG1_RESERVED_BIT18 (1U << 18) +#define SPM_DBG1_RESERVED_BIT19 (1U << 19) +#define SPM_DBG1_RESERVED_BIT20 (1U << 20) +#define SPM_DBG1_RESERVED_BIT21 (1U << 21) +#define SPM_DBG1_RESERVED_BIT22 (1U << 22) +#define SPM_DBG1_RESERVED_BIT23 (1U << 23) +#define SPM_DBG1_RESERVED_BIT24 (1U << 24) +#define SPM_DBG1_RESERVED_BIT25 (1U << 25) +#define SPM_DBG1_RESERVED_BIT26 (1U << 26) +#define SPM_DBG1_RESERVED_BIT27 (1U << 27) +#define SPM_DBG1_RESERVED_BIT28 (1U << 28) +#define SPM_DBG1_RESERVED_BIT29 (1U << 29) +#define SPM_DBG1_RESERVED_BIT30 (1U << 30) +#define SPM_DBG1_RESERVED_BIT31 (1U << 31) + +/* --- R0 Define --- */ +#define R0_SC_26M_CK_OFF (1U << 0) +#define R0_BIT1 (1U << 1) +#define R0_SC_MEM_CK_OFF (1U << 2) +#define R0_SC_AXI_CK_OFF (1U << 3) +#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) +#define R0_SC_MD26M_CK_OFF (1U << 5) +#define R0_SC_DPY_MODE_SW_PCM (1U << 6) +#define R0_SC_DMSUS_OFF_PCM (1U << 7) +#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) +#define R0_BIT9 (1U << 9) +#define R0_SC_MPLLOUT_OFF (1U << 10) +#define R0_SC_TX_TRACKING_DIS (1U << 11) +#define R0_SC_DPY_DLL_EN_PCM (1U << 12) +#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) +#define R0_SC_DPY_VREF_EN_PCM (1U << 14) +#define R0_SC_PHYPLL_EN_PCM (1U << 15) +#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) +#define R0_SC_DPY_BCLK_ENABLE (1U << 17) +#define R0_SC_MPLL_OFF (1U << 18) +#define R0_SC_SHU_RESTORE (1U << 19) +#define R0_SC_CKSQ0_OFF (1U << 20) +#define R0_SC_CKSQ1_OFF (1U << 21) +#define R0_SC_DR_SHU_EN_PCM (1U << 22) +#define R0_SC_DPHY_PRECAL_UP (1U << 23) +#define R0_SC_MPLL_S_OFF (1U << 24) +#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) +#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) +#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) +#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) +#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) +#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) +#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) + +/* --- R7 Define --- */ +#define R7_PWRAP_SLEEP_REQ (1U << 0) +#define R7_EMI_CLK_OFF_REQ (1U << 1) +#define R7_TOP_MAS_PAU_REQ (1U << 2) +#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) +#define R7_PCM_CK_SEL0 (1U << 4) +#define R7_PCM_CK_SEL1 (1U << 5) +#define R7_SPM2RC_DVS_DONE (1U << 6) +#define R7_FREQH_PAUSE_MPLL (1U << 7) +#define R7_SC_26M_CK_SEL (1U << 8) +#define R7_PCM_TIMER_SET (1U << 9) +#define R7_PCM_TIMER_CLR (1U << 10) +#define R7_SRCVOLTEN (1U << 11) +#define R7_CSYSPWRUPACK (1U << 12) +#define R7_IM_SLEEP_ENABLE (1U << 13) +#define R7_SRCCLKENO_0 (1U << 14) +#define R7_SYSRST (1U << 15) +#define R7_MD_APSRC_ACK (1U << 16) +#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) +#define R7_SC_AXI_DCM_DIS (1U << 18) +#define R7_FREQH_PAUSE_MAIN (1U << 19) +#define R7_FREQH_PAUSE_MEM (1U << 20) +#define R7_SRCCLKENO_1 (1U << 21) +#define R7_WDT_KICK_P (1U << 22) +#define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) +#define R7_WAKEUP_EXT_W_SEL (1U << 24) +#define R7_WAKEUP_EXT_R_SEL (1U << 25) +#define R7_PMIC_IRQ_REQ_EN (1U << 26) +#define R7_FORCE_26M_WAKE (1U << 27) +#define R7_FORCE_APSRC_WAKE (1U << 28) +#define R7_FORCE_INFRA_WAKE (1U << 29) +#define R7_FORCE_VRF18_WAKE (1U << 30) +#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) + +/* --- R12 Define --- */ +#define R12_PCM_TIMER (1U << 0) +#define R12_SSPM_WDT_EVENT_B (1U << 1) +#define R12_KP_IRQ_B (1U << 2) +#define R12_APWDT_EVENT_B (1U << 3) +#define R12_APXGPT1_EVENT_B (1U << 4) +#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) +#define R12_EINT_EVENT_B (1U << 6) +#define R12_CONN_WDT_IRQ_B (1U << 7) +#define R12_CCIF0_EVENT_B (1U << 8) +#define R12_LOWBATTERY_IRQ_B (1U << 9) +#define R12_SSPM_SPM_IRQ_B (1U << 10) +#define R12_SCP_SPM_IRQ_B (1U << 11) +#define R12_SCP_WDT_EVENT_B (1U << 12) +#define R12_PCM_WDT_WAKEUP_B (1U << 13) +#define R12_USB_CDSC_B (1U << 14) +#define R12_USB_POWERDWN_B (1U << 15) +#define R12_SYS_TIMER_EVENT_B (1U << 16) +#define R12_EINT_EVENT_SECURE_B (1U << 17) +#define R12_CCIF1_EVENT_B (1U << 18) +#define R12_UART0_IRQ_B (1U << 19) +#define R12_AFE_IRQ_MCU_B (1U << 20) +#define R12_THERM_CTRL_EVENT_B (1U << 21) +#define R12_SYS_CIRQ_IRQ_B (1U << 22) +#define R12_MD2AP_PEER_EVENT_B (1U << 23) +#define R12_CSYSPWREQ_B (1U << 24) +#define R12_MD1_WDT_B (1U << 25) +#define R12_CLDMA_EVENT_B (1U << 26) +#define R12_SEJ_WDT_GPT_B (1U << 27) +#define R12_ALL_SSPM_WAKEUP_B (1U << 28) +#define R12_CPU_IRQ_B (1U << 29) +#define R12_CPU_WFI_AND_B (1U << 30) +#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) + +/* --- R12ext Define --- */ +#define R12EXT_26M_WAKE (1U << 0) +#define R12EXT_26M_SLEEP (1U << 1) +#define R12EXT_INFRA_WAKE (1U << 2) +#define R12EXT_INFRA_SLEEP (1U << 3) +#define R12EXT_APSRC_WAKE (1U << 4) +#define R12EXT_APSRC_SLEEP (1U << 5) +#define R12EXT_VRF18_WAKE (1U << 6) +#define R12EXT_VRF18_SLEEP (1U << 7) +#define R12EXT_DVFS_ALL_STATE (1U << 8) +#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) +#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) +#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) +#define R12EXT_DDREN_WAKE (1U << 12) +#define R12EXT_DDREN_SLEEP (1U << 13) +#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) +#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) +#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) +#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) +#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) +#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) +#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) +#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) +#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) +#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) +#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) +#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) +#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) +#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) +#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) +#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) +#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) +#define R12EXT_HYBRID_DDREN_WAKE (1U << 31) + +/* --- R13 Define --- */ +#define R13_EXT_SRCCLKENI_0 (1U << 0) +#define R13_EXT_SRCCLKENI_1 (1U << 1) +#define R13_MD1_SRCCLKENA (1U << 2) +#define R13_MD1_APSRC_REQ (1U << 3) +#define R13_CONN_DDR_EN (1U << 4) +#define R13_MD2_SRCCLKENA (1U << 5) +#define R13_SSPM_SRCCLKENA (1U << 6) +#define R13_SSPM_APSRC_REQ (1U << 7) +#define R13_MD_STATE (1U << 8) +#define R13_EMI_CLK_OFF_2_ACK (1U << 9) +#define R13_MM_STATE (1U << 10) +#define R13_SSPM_STATE (1U << 11) +#define R13_MD_DDR_EN (1U << 12) +#define R13_CONN_STATE (1U << 13) +#define R13_CONN_SRCCLKENA (1U << 14) +#define R13_CONN_APSRC_REQ (1U << 15) +#define R13_SLEEP_EVENT_STA (1U << 16) +#define R13_WAKE_EVENT_STA (1U << 17) +#define R13_EMI_IDLE (1U << 18) +#define R13_CSYSPWRUPREQ (1U << 19) +#define R13_PWRAP_SLEEP_ACK (1U << 20) +#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) +#define R13_TOP_MAS_PAU_ACK (1U << 22) +#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) +#define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) +#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) +#define R13_INFRA_AUX_IDLE (1U << 26) +#define R13_DVFS_ALL_STATE (1U << 27) +#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) +#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) +#define R13_MD1_VRF18_REQ (1U << 30) +#define R13_C2K_VRF18_REQ (1U << 31) + +#define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) +#define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) + +#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) +#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) +#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 7) | \ + (!!(resume) << 6) | \ + ((event) & 0x3f)) + +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF 0x00015800 +#define PCM_FSM_STA_DEF 0x00108490 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 (1U << 0) +#define PCM_SW_INT1 (1U << 1) +#define PCM_SW_INT2 (1U << 2) +#define PCM_SW_INT3 (1U << 3) +#define PCM_SW_INT4 (1U << 4) +#define PCM_SW_INT5 (1U << 5) +#define PCM_SW_INT6 (1U << 6) +#define PCM_SW_INT7 (1U << 7) +#define PCM_SW_INT8 (1U << 8) +#define PCM_SW_INT9 (1U << 9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ0 (1U << 8) +#define ISRM_RET_IRQ1 (1U << 9) +#define ISRM_RET_IRQ2 (1U << 10) +#define ISRM_RET_IRQ3 (1U << 11) +#define ISRM_RET_IRQ4 (1U << 12) +#define ISRM_RET_IRQ5 (1U << 13) +#define ISRM_RET_IRQ6 (1U << 14) +#define ISRM_RET_IRQ7 (1U << 15) +#define ISRM_RET_IRQ8 (1U << 16) +#define ISRM_RET_IRQ9 (1U << 17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ + ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ + ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ + ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_WAKEUP_MISC */ +#define WAKE_MISC_TWAM (1U << 18) +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +enum SPM_WAKE_SRC_LIST { + WAKE_SRC_R12_PCM_TIMER = (1U << 0), + WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), + WAKE_SRC_R12_KP_IRQ_B = (1U << 2), + WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), + WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), + WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), + WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), + WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), + WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), + WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), + WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), + WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), + WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), + WAKE_SRC_R12_USB_CDSC_B = (1U << 14), + WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), + WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), + WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), + WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), + WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), + WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), + WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), + WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), + WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), + WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), + WAKE_SRC_R12_MD1_WDT_B = (1U << 25), + WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), + WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), + WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), + WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), + WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), +}; + +struct pcm_desc { + const char *version; /* PCM code version */ + u32 *base; /* binary array base */ + const u16 size; /* binary array size */ + const u8 sess; /* session number */ + const u8 replace; /* replace mode */ + const u16 addr_2nd; /* 2nd binary array size */ + const u16 reserved; /* for 32bit alignment */ + u32 vec0; /* event vector 0 config */ + u32 vec1; /* event vector 1 config */ + u32 vec2; /* event vector 2 config */ + u32 vec3; /* event vector 3 config */ + u32 vec4; /* event vector 4 config */ + u32 vec5; /* event vector 5 config */ + u32 vec6; /* event vector 6 config */ + u32 vec7; /* event vector 7 config */ + u32 vec8; /* event vector 8 config */ + u32 vec9; /* event vector 9 config */ + u32 vec10; /* event vector 10 config */ + u32 vec11; /* event vector 11 config */ + u32 vec12; /* event vector 12 config */ + u32 vec13; /* event vector 13 config */ + u32 vec14; /* event vector 14 config */ + u32 vec15; /* event vector 15 config */ +}; + +struct pwr_ctrl { + unsigned int pcm_flags; + unsigned int pcm_flags1; + unsigned int timer_val; + unsigned int wake_src; + + /* SPM_AP_STANDBY_CON */ + unsigned int wfi_op; + unsigned int mp0_cputop_idle_mask; + unsigned int mp1_cputop_idle_mask; + unsigned int mcusys_idle_mask; + unsigned int mm_mask_b; + unsigned int md_ddr_en_0_dbc_en; + unsigned int md_ddr_en_1_dbc_en; + unsigned int md_mask_b; + unsigned int sspm_mask_b; + unsigned int scp_mask_b; + unsigned int srcclkeni_mask_b; + unsigned int md_apsrc_1_sel; + unsigned int md_apsrc_0_sel; + unsigned int conn_ddr_en_dbc_en; + unsigned int conn_mask_b; + unsigned int conn_apsrc_sel; + + /* SPM_SRC_REQ */ + unsigned int spm_apsrc_req; + unsigned int spm_f26m_req; + unsigned int spm_infra_req; + unsigned int spm_vrf18_req; + unsigned int spm_ddren_req; + unsigned int spm_rsv_src_req; + unsigned int spm_ddren_2_req; + unsigned int cpu_md_dvfs_sop_force_on; + + /* SPM_SRC_MASK */ + unsigned int csyspwreq_mask; + unsigned int ccif0_md_event_mask_b; + unsigned int ccif0_ap_event_mask_b; + unsigned int ccif1_md_event_mask_b; + unsigned int ccif1_ap_event_mask_b; + unsigned int ccif2_md_event_mask_b; + unsigned int ccif2_ap_event_mask_b; + unsigned int ccif3_md_event_mask_b; + unsigned int ccif3_ap_event_mask_b; + unsigned int md_srcclkena_0_infra_mask_b; + unsigned int md_srcclkena_1_infra_mask_b; + unsigned int conn_srcclkena_infra_mask_b; + unsigned int ufs_infra_req_mask_b; + unsigned int srcclkeni_infra_mask_b; + unsigned int md_apsrc_req_0_infra_mask_b; + unsigned int md_apsrc_req_1_infra_mask_b; + unsigned int conn_apsrcreq_infra_mask_b; + unsigned int ufs_srcclkena_mask_b; + unsigned int md_vrf18_req_0_mask_b; + unsigned int md_vrf18_req_1_mask_b; + unsigned int ufs_vrf18_req_mask_b; + unsigned int gce_vrf18_req_mask_b; + unsigned int conn_infra_req_mask_b; + unsigned int gce_apsrc_req_mask_b; + unsigned int disp0_apsrc_req_mask_b; + unsigned int disp1_apsrc_req_mask_b; + unsigned int mfg_req_mask_b; + unsigned int vdec_req_mask_b; + + /* SPM_SRC2_MASK */ + unsigned int md_ddr_en_0_mask_b; + unsigned int md_ddr_en_1_mask_b; + unsigned int conn_ddr_en_mask_b; + unsigned int ddren_sspm_apsrc_req_mask_b; + unsigned int ddren_scp_apsrc_req_mask_b; + unsigned int disp0_ddren_mask_b; + unsigned int disp1_ddren_mask_b; + unsigned int gce_ddren_mask_b; + unsigned int ddren_emi_self_refresh_ch0_mask_b; + unsigned int ddren_emi_self_refresh_ch1_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + unsigned int spm_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + unsigned int spm_wakeup_event_ext_mask; + + /* SPM_SRC3_MASK */ + unsigned int md_ddr_en_2_0_mask_b; + unsigned int md_ddr_en_2_1_mask_b; + unsigned int conn_ddr_en_2_mask_b; + unsigned int ddren2_sspm_apsrc_req_mask_b; + unsigned int ddren2_scp_apsrc_req_mask_b; + unsigned int disp0_ddren2_mask_b; + unsigned int disp1_ddren2_mask_b; + unsigned int gce_ddren2_mask_b; + unsigned int ddren2_emi_self_refresh_ch0_mask_b; + unsigned int ddren2_emi_self_refresh_ch1_mask_b; + + unsigned int mp0_cpu0_wfi_en; + unsigned int mp0_cpu1_wfi_en; + unsigned int mp0_cpu2_wfi_en; + unsigned int mp0_cpu3_wfi_en; + + unsigned int mp1_cpu0_wfi_en; + unsigned int mp1_cpu1_wfi_en; + unsigned int mp1_cpu2_wfi_en; + unsigned int mp1_cpu3_wfi_en; +}; + +struct wake_status { + unsigned int assert_pc; + unsigned int r12; + unsigned int r12_ext; + unsigned int raw_sta; + unsigned int raw_ext_sta; + unsigned int wake_misc; + unsigned int timer_out; + unsigned int r13; + unsigned int r15; + unsigned int idle_sta; + unsigned int req_sta; + unsigned int debug_flag; + unsigned int debug_flag1; + unsigned int event_reg; + unsigned int isr; + unsigned int sw_flag; + unsigned int sw_flag1; + unsigned int log_index; +}; + +enum dyna_load_pcm_index { + DYNA_LOAD_PCM_SUSPEND_LP4_3733 = 0, + DYNA_LOAD_PCM_SUSPEND_LP4_3200, + DYNA_LOAD_PCM_MAX, +}; + +struct dyna_load_pcm_t { + char path[128]; + char version[128]; + u8 *buf; + struct pcm_desc desc; + int ready; +}; + +void spm_init(void); + +#endif /* __SPM_INIT__ */ diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4..5e8c2e4 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/spm_init.h> #include <symbols.h>
@@ -27,6 +28,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + spm_init(); }
static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c new file mode 100644 index 0000000..dcac95f --- /dev/null +++ b/src/soc/mediatek/mt8183/spm.c @@ -0,0 +1,321 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <soc/emi.h> +#include <soc/spm.h> +#include <soc/spm_init.h> + +#define BUF_SIZE (16 * KiB) +static uint8_t spm_bin[BUF_SIZE] __aligned(8); + +struct dyna_load_pcm_t dyna_load_pcm[DYNA_LOAD_PCM_MAX]; + +static void spm_register_init(void) +{ + write32(&mtk_spm->poweron_config_set, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB | + MD_BCLK_CG_EN_LSB); + + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + if ((read32(&mtk_spm->pcm_fsm_sta) & 0x7fffff) != PCM_FSM_STA_DEF) + printk(BIOS_ERR, "PCM reset failed\n"); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | EVENT_LOCK_EN_LSB | + SPM_SRAM_ISOINT_B_LSB | MIF_APBEN_LSB | + SCP_APB_INTERNAL_EN_LSB); + write32(&mtk_spm->pcm_im_ptr, 0); + write32(&mtk_spm->pcm_im_len, 0); + + write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) | (0x3 << 2) | + SPM_LOCK_INFRA_DCM_LSB | (1 << 6) | + CXO32K_REMOVE_EN_MD1_LSB | + CLKSQ1_SEL_CTRL_LSB | SRCLKEN0_EN_LSB | + (0x10 << 23)); + + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->ddr_en_dbc_len, 0x154 | (0x154 << 10) | (0x154 << 20)); + write32(&mtk_spm->spare_ack_mask, + (read32(&mtk_spm->spare_ack_mask) & ~(0x1 << 1)) | 0x1); + write32(&mtk_spm->sysrom_con, 0x3f); + write32(&mtk_spm->spm_pc_trace_con, 0x8 | SPM_PC_TRACE_HW_EN_LSB); + + write32(&mtk_spm->spare_src_req_mask, read32(&mtk_spm->spare_src_req_mask) | + SPARE1_DDREN_MASK_B_LSB); +} + +static void spm_code_swapping(void) +{ + unsigned int con1, retry = 0, timeout = 5000; + + con1 = read32(&mtk_spm->spm_wakeup_event_mask); + + write32(&mtk_spm->spm_wakeup_event_mask, (con1 & ~(0x1))); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + + while ((read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB) == 0) { + if (retry > timeout) { + printk(BIOS_ERR, "r15: 0x%x, pcmsta: 0x%x, irqsta: 0x%x [%d]\n", + read32(&mtk_spm->pcm_reg15_data), + read32(&mtk_spm->pcm_fsm_sta), + read32(&mtk_spm->spm_irq_sta), timeout); + } + retry++; + } + + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, con1); +} + +static void spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) +{ + unsigned int con1; + + if ((read32(&mtk_spm->pcm_reg1_data) == 0x1) && + !(read32(&mtk_spm->pcm_reg15_data) == 0x0)) { + spm_code_swapping(); + write32(&mtk_spm->spm_power_on_val0, read32(&mtk_spm->pcm_reg0_data)); + } + + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~PCM_TIMER_EN_LSB)); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + if ((read32(&mtk_spm->pcm_fsm_sta) & 0x7fffff) != PCM_FSM_STA_DEF) + printk(BIOS_ERR, "reset pcm(PCM_FSM_STA=0x%x)\n", + read32(&mtk_spm->pcm_fsm_sta)); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + + con1 = read32(&mtk_spm->pcm_con1) & (PCM_WDT_WAKE_MODE_LSB); + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + EVENT_LOCK_EN_LSB | SPM_SRAM_ISOINT_B_LSB | + (pcmdesc->replace ? 0 : IM_NONRP_EN_LSB) | + MIF_APBEN_LSB | SCP_APB_INTERNAL_EN_LSB); +} + +static void spm_load_pcm_code(const struct pcm_desc *pcmdesc) +{ + int i; + + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | IM_SLAVE_LSB); + + for (i = 0; i < pcmdesc->size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, BIT(31) | BIT(30) | i); + write32(&mtk_spm->pcm_im_host_rw_dat, + (unsigned int) *(pcmdesc->base + i)); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_check_pcm_code(const struct pcm_desc *pcmdesc) +{ + int i; + + for (i = 0; i < pcmdesc->size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, BIT(31) | i); + if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != + (unsigned int) *(pcmdesc->base + i)) + spm_load_pcm_code(pcmdesc); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) +{ + unsigned int ptr, len, con0; + + ptr = (unsigned int)(unsigned long)(pcmdesc->base); + len = pcmdesc->size - 1; + + spm_load_pcm_code(pcmdesc); + spm_check_pcm_code(pcmdesc); + + printk(BIOS_INFO, "spm_kick_im_to_fetch: ptr = 0x%x\n", ptr); + printk(BIOS_INFO, "spm_kick_im_to_fetch: len = %d\n", len); + + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | + PCM_CK_EN_LSB | IM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + write32(&mtk_spm->pcm_event_vector0, pcmdesc->vec0); + write32(&mtk_spm->pcm_event_vector1, pcmdesc->vec1); + write32(&mtk_spm->pcm_event_vector2, pcmdesc->vec2); + write32(&mtk_spm->pcm_event_vector3, pcmdesc->vec3); + write32(&mtk_spm->pcm_event_vector4, pcmdesc->vec4); + write32(&mtk_spm->pcm_event_vector5, pcmdesc->vec5); + write32(&mtk_spm->pcm_event_vector6, pcmdesc->vec6); + write32(&mtk_spm->pcm_event_vector7, pcmdesc->vec7); + write32(&mtk_spm->pcm_event_vector8, pcmdesc->vec8); + write32(&mtk_spm->pcm_event_vector9, pcmdesc->vec9); + write32(&mtk_spm->pcm_event_vector10, pcmdesc->vec10); + write32(&mtk_spm->pcm_event_vector11, pcmdesc->vec11); + write32(&mtk_spm->pcm_event_vector12, pcmdesc->vec12); + write32(&mtk_spm->pcm_event_vector13, pcmdesc->vec13); + write32(&mtk_spm->pcm_event_vector14, pcmdesc->vec14); + write32(&mtk_spm->pcm_event_vector15, pcmdesc->vec15); +} + +static const char *dyna_load_pcm_path[] = { + [DYNA_LOAD_PCM_SUSPEND_LP4_3733] = "pcm_allinone_lp4_3733.bin", + [DYNA_LOAD_PCM_SUSPEND_LP4_3200] = "pcm_allinone_lp4_3200.bin", + [DYNA_LOAD_PCM_MAX] = "pcm_path_max", +}; + +static void spm_load_firmware(enum dyna_load_pcm_index index) +{ + int offset = 0; + u16 firmware_size = 0; + int copy_size = 0; + const char *file_name = dyna_load_pcm_path[index]; + struct pcm_desc *pdesc = &(dyna_load_pcm[index].desc); + + size_t fw_size = cbfs_boot_load_file(file_name, + spm_bin, + sizeof(spm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) + printk(BIOS_ERR, "SPM file: %s not found!!!\n", + dyna_load_pcm_path[index]); + + /* start of binary size */ + offset = 0; + copy_size = 2; + memcpy(&firmware_size, spm_bin + offset, copy_size); + + printk(BIOS_INFO, "spm: firmware_size = %d\n", firmware_size); + + /* start of binary */ + offset += copy_size; + copy_size = firmware_size * 4; + dyna_load_pcm[index].buf = spm_bin + offset; + + printk(BIOS_INFO, "start of binary: (spm_bin + offset) = 0x%x\n", + (unsigned int)(unsigned long) dyna_load_pcm[index].buf); + + /* start of pcm_desc */ + offset += copy_size; + copy_size = sizeof(struct pcm_desc) - offsetof(struct pcm_desc, size); + memcpy((void *)&(dyna_load_pcm[index].desc.size), + spm_bin + offset, copy_size); + + offset += copy_size; + snprintf(dyna_load_pcm[index].version, 128 - 1, "%s", spm_bin + offset); + pdesc->version = dyna_load_pcm[index].version; + pdesc->base = (u32 *) dyna_load_pcm[index].buf; + + printk(BIOS_INFO, "start of pcm_desc: pdesc->version %s\n", + pdesc->version); + + printk(BIOS_INFO, "#@# %s(%d) use spmfw partition for %s\n", __func__, + __LINE__, dyna_load_pcm_path[index]); + + dyna_load_pcm[index].ready = 1; +} + +static void spm_kick_pcm_to_run(void) +{ + uint32_t con0; + + write32(&mtk_spm->spm_mas_pause_mask_b, 0xffffffff); + write32(&mtk_spm->spm_mas_pause2_mask_b, 0xffffffff); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + write32(&mtk_spm->pcm_pwr_io_en, PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7); + + printk(BIOS_INFO, "SPM spm_kick_pcm_to_run\n"); + + /* check IM ready */ + while ((read32(&mtk_spm->pcm_fsm_sta) & (0x7 << 7)) != (0x4 << 7)) + ; + + /* kick PCM to run, and toggle PCM_KICK */ + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + printk(BIOS_INFO, "SPM spm_kick_pcm_to_run done\n"); +} + +void spm_init(void) +{ + struct pcm_desc *pcmdesc = NULL; + unsigned int dram_type = get_dram_type(); + enum dyna_load_pcm_index index; + + if (dram_type == DRAM_TYPE_EMCP) + index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; + else + index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; + + printk(BIOS_INFO, "SPM: dram type = %d, pcm index = %d\n", + dram_type, index); + + if (dyna_load_pcm[index].ready) + pcmdesc = &(dyna_load_pcm[index].desc); + else { + printk(BIOS_ERR, "SPM: firmware is not ready!!!\n"); + return; + } + + spm_load_firmware(index); + spm_register_init(); + spm_reset_and_init_pcm(pcmdesc); + spm_kick_im_to_fetch(pcmdesc); + spm_init_pcm_register(); + spm_init_event_vector(pcmdesc); + spm_kick_pcm_to_run(); + + printk(BIOS_INFO, "SPM spm_init done\n"); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/inc... PS1, Line 946: #define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ 'SEPERATE' may be misspelled - perhaps 'SEPARATE'?
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 168: printk(BIOS_INFO, "spm_kick_im_to_fetch: ptr = 0x%x\n", ptr); Prefer using '"%s...", __func__' to using 'spm_kick_im_to_fetch', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 169: printk(BIOS_INFO, "spm_kick_im_to_fetch: len = %d\n", len); Prefer using '"%s...", __func__' to using 'spm_kick_im_to_fetch', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 208: static const char *dyna_load_pcm_path[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 276: printk(BIOS_INFO, "SPM spm_kick_pcm_to_run\n"); Prefer using '"%s...", __func__' to using 'spm_kick_pcm_to_run', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 288: printk(BIOS_INFO, "SPM spm_kick_pcm_to_run done\n"); Prefer using '"%s...", __func__' to using 'spm_kick_pcm_to_run', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 320: printk(BIOS_INFO, "SPM spm_init done\n"); Prefer using '"%s...", __func__' to using 'spm_init', this function's name, in a string
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 65: 0x154 what's magic 0x154? maybe put a #define or enum with meaningful name.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 68: 0x3f what is 0x3f?
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 69: 0x8 what is 0x8?
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 77: 5000 do you want to retry by "number" or "time (i.e., 50us or 50us?)"?
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 123: (PCM_WDT_WAKE_MODE_LSB) no need to quote.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 162: (unsigned int)(unsigned long) why doing twice
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 253: 128 - 1 use sizeof or some named constant.
also, snprintf will add NUL so you don't need to -1.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 255: no space between type casting and variable,
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 291: void Does SPM need to be always initialized inside SOC implementation?
I feel it makes more sense if we do this in board level, that in ROM stage or somewhere after RAM is loaded, we load SDRAM config, and pass the type/speed into spm_init.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 297: DRAM_TYPE_EMCP if in the end we hve to choose either 3200 or 3733, why not just put that in DRAM configuration as 'int maxspeed'?
Then we can even decide the path by sprintf("..%d", speed), no need to do t he conversion so many times.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#2).
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
SPM: mt8183: support spm suspend in coreboot
Load SPM firmware and init SPM in core boot
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 2,500 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 208: static const char * dyna_load_pcm_path[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 208: static const char * dyna_load_pcm_path[] = { "foo * bar" should be "foo *bar"
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2: Code-Review+1
suspend/resume test ok for LPDDR4 3200.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@7 PS2, Line 7: SPM: mt8183: support spm suspend in coreboot Please use the common prefix (see `git log --oneline`).
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@9 PS2, Line 9: core boot coreboot
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@10 PS2, Line 10: Tested how? Why is the SPM firmware needed for suspend?
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@11 PS2, Line 11: Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Please add your Signed-off-by line below.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
(5 comments)
Please add a more elaborate commit message for such a huge diff stat. What is SPM and why is it needed? Why does it have to be set up by the firmware, and it’s not enough that the OS sets it up? From what datasheet did you take the macro definitions?
Also, please add a follow-up commit with additional time-stamps (or stopwatch messages) so the time of this can be measured.
What is the boot time penalty of this commit?
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 225: CBFS_TYPE_RAW); Please use the full text width.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 243: BIOS_INFO Probably more debug level?
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 244: (unsigned int)(unsigned long) Why the double cast?
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 305: spm_load_firmware(index); Did you add time-stamps for this? I thinks these thinks should be measured for how long the take.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 310: printk(BIOS_ERR, "SPM: firmware is not ready!!!\n"); As this is a user visible message, please add more information, what the user should do.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
In the coreboot project (welcome by the way!) commit authors should not score their own commit.
suspend/resume test ok for LPDDR4 3200.
Please add that to the commit message.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2: -Code-Review
(18 comments)
Patch Set 2:
(5 comments)
Please add a more elaborate commit message for such a huge diff stat. What is SPM and why is it needed? Why does it have to be set up by the firmware, and it’s not enough that the OS sets it up? From what datasheet did you take the macro definitions?
Also, please add a follow-up commit with additional time-stamps (or stopwatch messages) so the time of this can be measured.
What is the boot time penalty of this commit?
==> Yes, I would add more information in comment message, and try to explain it more clear.
What is SPM and why is it needed? Why does it have to be set up by the firmware? ==> For SOC power saving There is a HW module inside SOC, we call this HW module SPM. After linux PM suspend, SPM would turn off last CPU power and do more powersave for SOC (such like DRAM self-refresh mode, reduce SOC voltage level, turn off 26M crystal,...)
SPM need firmware to turn off SoC power or do power-save in right time and right condition. Otherwise, SPM can't do any thing after linux PM suspend.
From what datasheet did you take the macro definitions? ==> MT8183 SPM datasheet
Also, please add a follow-up commit with additional time-stamps (or stopwatch messages) so the time of this can be measured ==> I would have a try to add time-stamps on next version.
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@9 PS2, Line 9: core boot
coreboot
ok, would update on next version.
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@10 PS2, Line 10:
Tested how? Why is the SPM firmware needed for suspend?
Test by powerd_dbus_suspend (it would call linux suspend to ram)
There is a HW module inside SOC, we call this HW module SPM. After linux PM suspend, SPM would turn off last CPU power and do more powersave for SOC (such like DRAM self-refresh mode, reduce SOC voltage level, turn off 26M crystal,...)
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@11 PS2, Line 11: Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
Please add your Signed-off-by line below.
ok, I would update on next version.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 65: 0x154
what's magic 0x154? maybe put a #define or enum with meaningful name.
I would put a define for meaningful name on next version. => 0x154 = MD_DDR_EN_0_DBC_LEN => (0x154 << 10) = MD_DDR_EN_1_DBC_LEN => (0x154 << 20) = CONN_DDR_EN_DBC_LEN
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 68: 0x3f
what is 0x3f?
I would put a define for meaningful name on next version. => 0x3f = IFR_SRAMROM_ROM_PDN
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 69: 0x8
what is 0x8?
I would put a define for meaningful name on next version. => 0x8 = SPM_PC_TRACE_OFFSET
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 77: 5000
do you want to retry by "number" or "time (i.e. […]
retry for time, and next version that I would add udelay(1) on while loop (max timeout = 5000 * 1us)
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 123: (PCM_WDT_WAKE_MODE_LSB)
no need to quote.
ok, would fix on next version.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 162: (unsigned int)(unsigned long)
why doing twice
This is for ptr get the dram address of pcmdesc->base (ptr is for unsigned int and the value is from dram address of pcmdesc->base) Actually, it is for debug purpose only, maybe I need remove 'ptr'.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 253: 128 - 1
use sizeof or some named constant. […]
ok, I would update it on next version for name and don't need to -1.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 255:
no space between type casting and variable,
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 291: void
Does SPM need to be always initialized inside SOC implementation? […]
In my opinion, it maybe keep inside SOC since SPM HW is inside SOC, and we can't mount it on board. and would you please explain what SDRAM config is.
Hi SJ, Would you have any comment?
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 297: DRAM_TYPE_EMCP
if in the end we hve to choose either 3200 or 3733, why not just put that in DRAM configuration as ' […]
Hi Hung-Te, I loop DRAM ownen for reviewer, and let him answer this question.
Hi Huayang, How about this suggest, would you please have a comment, thank you.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 225: CBFS_TYPE_RAW);
Please use the full text width.
ok, I would update on next version.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 243: BIOS_INFO
Probably more debug level?
ok, I would update on next version.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 244: (unsigned int)(unsigned long)
Why the double cast?
This is for print dram address of pcmdesc->base (dram address is for unsigned int and the value is from dram address of dyna_load_pcm[index].buf) Actually, it is for debug purpose only, maybe I need remove it, or use %p to print it.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 305: spm_load_firmware(index);
Did you add time-stamps for this? I thinks these thinks should be measured for how long the take.
I would try to add on next version.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 310: printk(BIOS_ERR, "SPM: firmware is not ready!!!\n");
As this is a user visible message, please add more information, what the user should do.
User need check dram type and if this driver could get right firmware. I would try to add more information on next version.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2: Code-Review+1
In the coreboot project (welcome by the way!) commit authors should not score their own commit.
suspend/resume test ok for LPDDR4 3200.
Please add that to the commit message.
==> ok, thank you for your kindly review
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: SPM: mt8183: support spm suspend in coreboot ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 77: unsigned int con1, retry = 0, timeout = 5000; You might want to add the unit to the variable name: timeout_us. coreboot’s stopwatch framework should help you with this.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#3).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving with suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. After linux PM suspend, SPM could turn off last CPU power and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal. And SPM need its' own firmware to do these power-save in right time with correct condition.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 735 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34545/3/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/3/src/soc/mediatek/mt8183/spm... PS3, Line 93: if (!wait_us(SPM_CORE_TIMEOUT, suspect code indent for conditional statements (8, 28)
https://review.coreboot.org/c/coreboot/+/34545/3/src/soc/mediatek/mt8183/spm... PS3, Line 110: if ((read32(&mtk_spm->pcm_reg1_data) == 0x1) && suspect code indent for conditional statements (8, 14)
https://review.coreboot.org/c/coreboot/+/34545/3/src/soc/mediatek/mt8183/spm... PS3, Line 278: __LINE__, dyna_load_pcm_path[index]); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34545/3/src/soc/mediatek/mt8183/spm... PS3, Line 297: while ((read32(&mtk_spm->pcm_fsm_sta) & (0x7 << 7)) != (0x4 << 7)) suspect code indent for conditional statements (8, 15)
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#4).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving with suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. After linux PM suspend, SPM could turn off last CPU power and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal. And SPM need its' own firmware to do these power-save in right time with correct condition.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 748 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/4
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#5).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving with suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. After linux PM suspend, SPM could turn off last CPU power and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal. And SPM need its' own firmware to do these power-save in right time with correct condition.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 6 files changed, 751 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/5
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#6).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving with suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. After linux PM suspend, SPM could turn off last CPU power and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal. And SPM need its' own firmware to do these power-save in right time with correct condition.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 749 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/6
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#7).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving with suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. After linux PM suspend, SPM could turn off last CPU power and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal. And SPM need its' own firmware to do these power-save in right time with correct condition.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 749 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/7
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#8).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving for suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 749 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/8
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 8:
Hi Paul/Hung-Te/Sirs, Actually, I always meet a build unstable issue since other patch did not include for this build environment. https://review.coreboot.org/c/blobs/+/34543
It always show this build unstable log, so I might ignore it first, and wait "https://review.coreboot.org/c/blobs/+/34543" merge to build this environment
Would you please keep going for reviewing this patch, thank you.
make[1]: *** No rule to make target '3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin', needed by '/cb-build/coreboot-gerrit.0/GOOGLE_KUKUI/coreboot.pre'. Stop. make[1]: Leaving directory '/home/coreboot/slave-root/workspace/coreboot-gerrit'
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Huayang Duan, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#9).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For power saving for suspend to ram of mt8183, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode, turn off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 751 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/9
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 9:
Hi Paul/Hung-Te/Sirs, Would you please keep going for reviewing this patch even there is an build unstable issue, thank you. Actually, this build unstable issue since another patch did not include for this build environment. In my opinion, it should not build unstable any more after "https://review.coreboot.org/c/blobs/+/34543" merge to build environment,
Here is the log for build unstable. make[1]: *** No rule to make target '3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin', needed by '/cb-build/coreboot-gerrit.0/GOOGLE_KUKUI/coreboot.pre'. Stop. make[1]: Leaving directory '/home/coreboot/slave-root/workspace/coreboot-gerrit'
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 9:
Hi Dawei,
I think the problem is you have to update submodule first, after the blobs are merged.
Something like this: https://review.coreboot.org/c/coreboot/+/34494
Please create such CL and put this one on top of it to fix the build failure.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 10:
Hi Hung-Te, Thank you for your help. I upload a new patch for 3rdparty/blobs submodule.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type()); I don't think this will work.
the get_sdram_config was only called in ROM stage, and your get_dram_type won't call get_sdram_config; which means when we call this in RAM stage, it'll be actually reading the static variable, which is only initialized to 0.
So we should just call get_sdram_config and pass the params.dram_type to spm_init.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type());
I don't think this will work. […]
Please try not to call get_sdram_config() from ramstage, it will have to load the whole blob from SPI flash again. Is there no way you can just determine the DRAM type by reading back some EMI registers (similar to how sdram_size() is implemented)? That's usually the best way to make that work.
(Alternatively, if there's no better way to do this, maybe load the SPM at the end of romstage instead?)
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type());
Please try not to call get_sdram_config() from ramstage, it will have to load the whole blob from SP […]
I just talk with MTK dram driver owner, how about if we move get_dram_type function to emi.c, and spm driver include emi.h to call get_dram_type.
int get_dram_type(void) { return params.dram_type; }
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type());
I just talk with MTK dram driver owner, how about if we move get_dram_type function to emi. […]
The point is that 'params' is not accessible in ramstage (or at least you shouldn't access it, for efficiency reasons). It doesn't matter which .c file you put the code in.
From looking at CB:34433 it seems like you're not actually using the dram_type thing anywhere else (i.e. not for the actual DDR init)? In that case, I see how it might be hard to interpret it back out of EMI hardware register state.
So I think you have two options: either move the thing that needs dram_type into romstage (so you only load the params from flash once and do everything you need to do with them in that stage), or you have to store the dram_type outside of the other params. For example, you could have a second lookup table in sdram_configs.c like this:
static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = ... };
static const enum dram_type sdram_types[] = { [1] = DRAM_TYPE_DISCRETE, [2] = ... };
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type());
The point is that 'params' is not accessible in ramstage (or at least you shouldn't access it, for e […]
Many thank you for your information, now we got the point. On next version, we would not run sdram_config.c in ram stage any more, and try to pass params.dram_type at ram stage if possible, thank you.
@Huayang, would you please comment for passing dram_type at ram stage, thank you.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#13).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 752 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/13
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#14).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 751 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/14
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 14:
(23 comments)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 50: u32 pcm_event_vector0; : u32 pcm_event_vector1; : u32 pcm_event_vector2; : u32 pcm_event_vector3; : u32 pcm_event_vector4; : u32 pcm_event_vector5; : u32 pcm_event_vector6; : u32 pcm_event_vector7; : u32 pcm_event_vector8; : u32 pcm_event_vector9; : u32 pcm_event_vector10; : u32 pcm_event_vector11; : u32 pcm_event_vector12; : u32 pcm_event_vector13; : u32 pcm_event_vector14; : u32 pcm_event_vector15; should we change these to pcm_event_vector[16];
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 476: check_member(mtk_spm_regs, poweron_config_set, 0x0000); : check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); : check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); : check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); : check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); : check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); : check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); : check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); : check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); : check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); : check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); : check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); : check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); : check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); : check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); : check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); : check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8); I don't think these are needed. Usually we just need to check few critical (or those very close to reserved) members, especially the last. Adding lots of regs here do not help.
(same for lines below)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 16: #ifndef __SPM_INIT__ I think we can move whole spm_init.h into spm.h. What do you think?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 137: WAKE_SRC_R12_PCM_TIMER = (1U << 0), for enum you don't need ()
just
WAKE_SRC_R12_PCM_TIMER = 1U << 0,
(same for lines below)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 178: u32 vec0; u32 vector[16];
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 196: pwr_ctrl this seems not used anywhere. do we need it?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 301: wake_status this seems not used anywhere. do we need it?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 46: if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) : printk(BIOS_ERR, "PCM reset failed\n"); : should we abort and return?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 94: unsigned int u32
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 102: wait_us should we abort and return on timeout?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 105: r15 Should we say something like timeout? this message seems obfuscated
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 117: unsigned int since we'll use these for write/read32 they should be u32.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 128: write32 sounds like you want clrsetbits32
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 138: 0x%x %p
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 162: unsigned int u32
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 174: nsigned int u32
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 184: ptr = (unsigned int)(unsigned long)(pcmdesc->base); so you only want to print base?
Just do
ptr=%p
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 185: len = pcmdesc->size - 1; just put that in printk.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 214: write32 change the regs to array and do a for-loop
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 260: 2; sizeof(firmware_size)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 323: void int
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif Use real code.
if (CONFIG(MT8183_DRAM_EMCP)) index = DYNA_LOAD_PCM...; else index = ....
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 346: return return 1 or return -1 to indicate failure
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 14:
(23 comments)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 50: u32 pcm_event_vector0; : u32 pcm_event_vector1; : u32 pcm_event_vector2; : u32 pcm_event_vector3; : u32 pcm_event_vector4; : u32 pcm_event_vector5; : u32 pcm_event_vector6; : u32 pcm_event_vector7; : u32 pcm_event_vector8; : u32 pcm_event_vector9; : u32 pcm_event_vector10; : u32 pcm_event_vector11; : u32 pcm_event_vector12; : u32 pcm_event_vector13; : u32 pcm_event_vector14; : u32 pcm_event_vector15;
should we change these to pcm_event_vector[16];
it is ok to me
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 476: check_member(mtk_spm_regs, poweron_config_set, 0x0000); : check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); : check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); : check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); : check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); : check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); : check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); : check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); : check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); : check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); : check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); : check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); : check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); : check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); : check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); : check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); : check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8);
I don't think these are needed. […]
Do you mean that we don't need to check every register what we use, just check the few critical register which is enough, especially the last one for close number, right?
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 16: #ifndef __SPM_INIT__
I think we can move whole spm_init.h into spm.h. […]
Actually, it's up to you and reviewer's comment, I could move to spm.h. In my opinion, since these are for SPM initial setting, so why don't add a new spm_init. How do you think
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 137: WAKE_SRC_R12_PCM_TIMER = (1U << 0),
for enum you don't need () […]
ok, I would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 178: u32 vec0;
u32 vector[16];
ok, I would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 196: pwr_ctrl
this seems not used anywhere. […]
Yes, I would remove these on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 301: wake_status
this seems not used anywhere. […]
Yes, I would remove these on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 46: if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) : printk(BIOS_ERR, "PCM reset failed\n"); :
should we abort and return?
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 94: unsigned int
u32
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 102: wait_us
should we abort and return on timeout?
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 105: r15
Should we say something like timeout? this message seems obfuscated
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 117: unsigned int
since we'll use these for write/read32 they should be u32.
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 128: write32
sounds like you want clrsetbits32
Yes, but I need write project code for high 16 bit to clear such register at the same time. pcm_con1 = pcm con1 | (0xb16 << 16) & ~PCM_TIMER_EN_LSB How do you suggest
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 138: 0x%x
%p
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 162: unsigned int
u32
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 174: nsigned int
u32
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 184: ptr = (unsigned int)(unsigned long)(pcmdesc->base);
so you only want to print base? […]
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 185: len = pcmdesc->size - 1;
just put that in printk.
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 214: write32
change the regs to array and do a for-loop
ok, I would try to update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 260: 2;
sizeof(firmware_size)
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 323: void
int
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif
Use real code. […]
ok, I would update it on next version.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 346: return
return 1 or return -1 to indicate failure
ok, I would update it on next version.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#15).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h A src/soc/mediatek/mt8183/spm.c 5 files changed, 562 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/15
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif
ok, I would update it on next version.
Hi Hung-Te, Would you know why build fail with real code "if (CONFIG(MT8183_DRAM_EMCP))" (refer to latest patch)
Fail log as following #!!!!! Error: Undefined Symbol 'MT8183_DRAM_EMCP' used at src/mainboard/google/kukui/Kconfig:45. #!!!!! Error: CONFIG() used on unknown value (MT8183_DRAM_EMCP) at src/soc/mediatek/mt8183/spm.c:330. # 2 errors
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif
Hi Hung-Te, […]
If you want to use CONFIG(), that must be 'if', not '#if'.
'#if' needs something like '#ifdef CONFIG_XXX' or '#if CONFIG_XXX'.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif
If you want to use CONFIG(), that must be 'if', not '#if'. […]
Hi Hung-Te, Actually, it is what my latest patch, please refer to https://review.coreboot.org/c/coreboot/+/34545/15/src/soc/mediatek/mt8183/sp... but it build fail, maybe I lose anything?
if (CONFIG(MT8183_DRAM_EMCP)) index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; else index = DYNA_LOAD_PCM_SUSPEND_LP4_3200;
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 15:
ok. in this chain you didn't include https://review.coreboot.org/c/coreboot/+/34989/1 so it can't find the right config (which should be defined in SOC Kconfig).
please rebase on top of that.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 16:
Hi Hung-Te, think you, it build pass now with https://review.coreboot.org/c/coreboot/+/34989/1
Dear Sirs, Please kindly keep to review this patch, thank you.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 16:
(17 comments)
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 65: 0x154
I would put a define for meaningful name on next version. […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 68: 0x3f
I would put a define for meaningful name on next version. […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 69: 0x8
I would put a define for meaningful name on next version. […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 77: 5000
retry for time, and next version that I would add udelay(1) on while loop […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 77: unsigned int con1, retry = 0, timeout = 5000;
You might want to add the unit to the variable name: timeout_us. […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 123: (PCM_WDT_WAKE_MODE_LSB)
ok, would fix on next version.
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 162: (unsigned int)(unsigned long)
This is for ptr get the dram address of pcmdesc->base […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 168: printk(BIOS_INFO, "spm_kick_im_to_fetch: ptr = 0x%x\n", ptr);
Prefer using '"%s... […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 169: printk(BIOS_INFO, "spm_kick_im_to_fetch: len = %d\n", len);
Prefer using '"%s... […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 208: static const char *dyna_load_pcm_path[] = {
static const char * array should probably be static const char * const
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 253: 128 - 1
ok, I would update it on next version for name and don't need to -1.
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 255:
ok, I would update it on next version.
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 276: printk(BIOS_INFO, "SPM spm_kick_pcm_to_run\n");
Prefer using '"%s... […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 288: printk(BIOS_INFO, "SPM spm_kick_pcm_to_run done\n");
Prefer using '"%s... […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 291: void
In my opinion, it maybe keep inside SOC since SPM HW is inside SOC, and we can't mount it on board. […]
That is the DRAM config we'll load from board folder.
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 297: DRAM_TYPE_EMCP
Hi Hung-Te, […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/1/src/soc/mediatek/mt8183/spm... PS1, Line 320: printk(BIOS_INFO, "SPM spm_init done\n");
Prefer using '"%s... […]
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 16:
(8 comments)
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@7 PS2, Line 7: SPM: mt8183: support spm suspend in coreboot
Please use the common prefix (see `git log --oneline`).
Ack
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@10 PS2, Line 10:
Test by powerd_dbus_suspend (it would call linux suspend to ram) […]
Ack
https://review.coreboot.org/c/coreboot/+/34545/2//COMMIT_MSG@11 PS2, Line 11: Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
ok, I would update on next version.
Ack
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 225: CBFS_TYPE_RAW);
ok, I would update on next version.
Ack
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 243: BIOS_INFO
ok, I would update on next version.
not updated yet?
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 244: (unsigned int)(unsigned long)
This is for print dram address of pcmdesc->base […]
this seems not fixed yet. please replace by %p without casting.
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 305: spm_load_firmware(index);
I would try to add on next version.
Ack
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 310: printk(BIOS_ERR, "SPM: firmware is not ready!!!\n");
User need check dram type and if this driver could get right firmware. […]
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/16/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/16/src/soc/mediatek/mt8183/in... PS16, Line 462: heck_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector[15], 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8); : check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); : check_member(mtk_spm_regs, pcm_reg15_data, 0x013c); : check_member(mtk_spm_regs, spm_irq_sta, 0x0158); : check_member(mtk_spm_regs, pcm_fsm_sta, 0x0178); : check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); : check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); : check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); : check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); : check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); : check_member(mtk_spm_regs, vde_pwr_con, 0x0300); : check_member(mtk_spm_regs, sysrom_con, 0x0354); : check_member(mtk_spm_regs, ufs_sram_con, 0x036c); : check_member(mtk_spm_regs, dummy_sram_con, 0x0380); : check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); : check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); : check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); : check_member(mtk_spm_regs, spm_mas_pause2_mask_b, 0x040c); : check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); : check_member(mtk_spm_regs, root_cputop_addr, 0x0570); : check_member(mtk_spm_regs, cpu_spare_con, 0x0580); : check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); : check_member(mtk_spm_regs, spare_ack_mask, 0x06f4); : check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); : check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); : check_member(mtk_spm_regs, spare_src_req_mask, 0x06c0); : check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); : check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); : check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); : check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780); : check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800); : check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0); : check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900); : check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920); : check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940); : check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960); I think we can delete all these. just keep first/last elements should be good enough.
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 16: #ifndef __SPM_INIT__
Actually, it's up to you and reviewer's comment, I could move to spm.h. […]
Moving everything to spm.h sounds ok to me.
Since the only thing we want to do for SPM inside firmware is simply to init, I see no reason having two different .c/.h files.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 476: check_member(mtk_spm_regs, poweron_config_set, 0x0000); : check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); : check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); : check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); : check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); : check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); : check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); : check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); : check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); : check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); : check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); : check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); : check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); : check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); : check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); : check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); : check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8);
Do you mean that we don't need to check every register what we use, just check the few critical regi […]
yes
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#17).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 517 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/17
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 243: BIOS_INFO
not updated yet?
Done
https://review.coreboot.org/c/coreboot/+/34545/2/src/soc/mediatek/mt8183/spm... PS2, Line 244: (unsigned int)(unsigned long)
this seems not fixed yet. please replace by %p without casting.
Done
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/16/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/16/src/soc/mediatek/mt8183/in... PS16, Line 462: heck_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector[15], 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8); : check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); : check_member(mtk_spm_regs, pcm_reg15_data, 0x013c); : check_member(mtk_spm_regs, spm_irq_sta, 0x0158); : check_member(mtk_spm_regs, pcm_fsm_sta, 0x0178); : check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); : check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); : check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); : check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); : check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); : check_member(mtk_spm_regs, vde_pwr_con, 0x0300); : check_member(mtk_spm_regs, sysrom_con, 0x0354); : check_member(mtk_spm_regs, ufs_sram_con, 0x036c); : check_member(mtk_spm_regs, dummy_sram_con, 0x0380); : check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); : check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); : check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); : check_member(mtk_spm_regs, spm_mas_pause2_mask_b, 0x040c); : check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); : check_member(mtk_spm_regs, root_cputop_addr, 0x0570); : check_member(mtk_spm_regs, cpu_spare_con, 0x0580); : check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); : check_member(mtk_spm_regs, spare_ack_mask, 0x06f4); : check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); : check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); : check_member(mtk_spm_regs, spare_src_req_mask, 0x06c0); : check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); : check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); : check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); : check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780); : check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800); : check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0); : check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900); : check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920); : check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940); : check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960);
I think we can delete all these. just keep first/last elements should be good enough.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 16: #ifndef __SPM_INIT__
Moving everything to spm.h sounds ok to me. […]
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 17:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... PS17, Line 161: SPM initial fail!!! SPM initialization failed, suspend/resume may fail.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... File src/soc/mediatek/mt8183/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... PS17, Line 72: 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin let's try to refactor this with the sspm one.
MT8183_BLOB_DIR := 3rdparty/blobs/src/mediatek/mt8183
... sspm.bin-file $(MT8183_BLOB_DIR)/sspm.bin ...
pcm_allinone_... := $(MT8183_BLOB_DIR)/pcm_allinone_lp4_3733.bin
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 80: write32(&mtk_spm->spare_ack_mask, : (read32(&mtk_spm->spare_ack_mask) & ~SPARE_ACK_MASK_B_BIT1) | : SPARE_ACK_MASK_B_BIT0); Is this equivalent to:
clrsetbits32(read32(&mtk_spm->spare_ack_mask), SPARE_ACK_MASK_B_BIT1, SPARE_ACK_MASK_B_BIT0);
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 88: write32 setbits32 ?
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 130: read32(&mtk_spm->pcm_reg0_data) wrong indent - this should be aligned to (
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 135: write32 clrsetbits32?
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 309: while should we do a wait_us or wait_ms here?
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 17:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... PS17, Line 161: SPM initial fail!!!
SPM initialization failed, suspend/resume may fail.
ok, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... File src/soc/mediatek/mt8183/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... PS17, Line 72: 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin
let's try to refactor this with the sspm one. […]
ok, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 80: write32(&mtk_spm->spare_ack_mask, : (read32(&mtk_spm->spare_ack_mask) & ~SPARE_ACK_MASK_B_BIT1) | : SPARE_ACK_MASK_B_BIT0);
Is this equivalent to: […]
Yes, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 88: write32
setbits32 ?
Yes, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 130: read32(&mtk_spm->pcm_reg0_data)
wrong indent - this should be aligned to (
ok, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 135: write32
clrsetbits32?
ok, would change it on next version.
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 309: while
should we do a wait_us or wait_ms here?
In my opinion, even usually spm don't take more time to switch status, we still need give SPM time until spm change new status to avoid SPM in wrong status and make sure spm could run pcm code. If there is any issue, I would rather stay to debug in this while loop than print a error message.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#18).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 522 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/18
Yu-Ping Wu has uploaded a new patch set (#25) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 522 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/25
Yu-Ping Wu has uploaded a new patch set (#26) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 522 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/26
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 25:
(24 comments)
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 50: u32 pcm_event_vector0; : u32 pcm_event_vector1; : u32 pcm_event_vector2; : u32 pcm_event_vector3; : u32 pcm_event_vector4; : u32 pcm_event_vector5; : u32 pcm_event_vector6; : u32 pcm_event_vector7; : u32 pcm_event_vector8; : u32 pcm_event_vector9; : u32 pcm_event_vector10; : u32 pcm_event_vector11; : u32 pcm_event_vector12; : u32 pcm_event_vector13; : u32 pcm_event_vector14; : u32 pcm_event_vector15;
it is ok to me
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 476: check_member(mtk_spm_regs, poweron_config_set, 0x0000); : check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); : check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); : check_member(mtk_spm_regs, spm_clk_con, 0x000c); : check_member(mtk_spm_regs, pcm_con0, 0x0018); : check_member(mtk_spm_regs, pcm_con1, 0x001c); : check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); : check_member(mtk_spm_regs, pcm_im_len, 0x0024); : check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); : check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); : check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); : check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); : check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); : check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); : check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); : check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); : check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); : check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); : check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); : check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); : check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); : check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); : check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); : check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); : check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); : check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); : check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); : check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); : check_member(mtk_spm_regs, spm_swint_clr, 0x0094); : check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); : check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); : check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); : check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8);
yes
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm_init.h:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 16: #ifndef __SPM_INIT__
Done
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 137: WAKE_SRC_R12_PCM_TIMER = (1U << 0),
ok, I would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 178: u32 vec0;
ok, I would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 196: pwr_ctrl
Yes, I would remove these on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/in... PS14, Line 301: wake_status
Yes, I would remove these on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 46: if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) : printk(BIOS_ERR, "PCM reset failed\n"); :
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 94: unsigned int
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 102: wait_us
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 105: r15
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 117: unsigned int
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 128: write32
Yes, but I need write project code for high 16 bit to clear such register at the same time. […]
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 138: 0x%x
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 162: unsigned int
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 174: nsigned int
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 184: ptr = (unsigned int)(unsigned long)(pcmdesc->base);
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 185: len = pcmdesc->size - 1;
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 214: write32
ok, I would try to update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 260: 2;
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 323: void
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 346: return
ok, I would update it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... PS25, Line 127: !(read32(&mtk_spm->pcm_reg15_data) == SPM_PCM_REG15_DATA_CHECK)) { Change !(x == y) to (x != y), and remove unnecessary parentheses.
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... PS25, Line 226: 16 Consider using ARRAY_SIZE(mtk_spm->pcm_event_vector).
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 26:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/26/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/26/src/soc/mediatek/mt8183/sp... PS26, Line 107: read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB)) { code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34545/26/src/soc/mediatek/mt8183/sp... PS26, Line 107: read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB)) { please, no space before tabs
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 26:
(6 comments)
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/mainboard/google/kukui... PS17, Line 161: SPM initial fail!!!
ok, would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... File src/soc/mediatek/mt8183/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/Ma... PS17, Line 72: 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin
ok, would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 80: write32(&mtk_spm->spare_ack_mask, : (read32(&mtk_spm->spare_ack_mask) & ~SPARE_ACK_MASK_B_BIT1) | : SPARE_ACK_MASK_B_BIT0);
Yes, would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 88: write32
Yes, would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 130: read32(&mtk_spm->pcm_reg0_data)
ok, would change it on next version.
Done
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 135: write32
ok, would change it on next version.
Done
Yu-Ping Wu has uploaded a new patch set (#31) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 517 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/31
Yu-Ping Wu has uploaded a new patch set (#32) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
For mt8133 power saving during suspend to ram, this patch supports SPM suspend and loading SPM firmware. SPM need its' own firmware to do these power-save in right time with correct condition. After linux PM suspend, SPM could turn off power for last CPU and do more power-save for SOC. such like DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume pass for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 519 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/32
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 32:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... PS25, Line 127: !(read32(&mtk_spm->pcm_reg15_data) == SPM_PCM_REG15_DATA_CHECK)) {
Change !(x == y) to (x != y), and remove unnecessary parentheses.
Done
https://review.coreboot.org/c/coreboot/+/34545/25/src/soc/mediatek/mt8183/sp... PS25, Line 226: 16
Consider using ARRAY_SIZE(mtk_spm->pcm_event_vector).
Done
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 35:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/12/src/mainboard/google/kukui... PS12, Line 59: spm_init(get_dram_type());
Many thank you for your information, now we got the point. […]
Done
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/14/src/soc/mediatek/mt8183/sp... PS14, Line 331: if CONFIG(MT8183_DRAM_EMCP) : index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; : #else : index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; : #endif
Hi Hung-Te, […]
Done
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 35:
(1 comment)
Patch Set 35:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 309: while
In my opinion, even usually spm don't take more time to switch status, we still need give SPM time u […]
Hi Hung-Te, I would change state to done if you don't have new comment, thank you.
Yu-Ping Wu has uploaded a new patch set (#36) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8133 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 519 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/36
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 37:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/17/src/soc/mediatek/mt8183/sp... PS17, Line 309: while
Hi Hung-Te, […]
Done
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, Huayang Duan, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34545
to look at the new patch set (#38).
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 519 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/38
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 38:
please rebase.
Yu-Ping Wu has uploaded a new patch set (#42) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 519 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/42
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 46:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34545/45/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/45/src/mainboard/google/kukui... PS45, Line 206: "SPM initialization failed, suspend/resume may fail.\n"); "Failed to init SPM, suspend/resume may fail.\n"
If that exceeds col 80, move to next line.
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 248: if (fw_size == 0) : printk(BIOS_ERR, "SPM file: %s not found!!!\n", : dyna_load_pcm_path[index]); : shouldn't we return now if fw_size is 0?
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 320: = NULL no need to init since we're not using it before it's assigned.
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 334: : if (dyna_load_pcm[index].ready) : pcmdesc = &(dyna_load_pcm[index].desc); : else { : printk(BIOS_ERR, "SPM: firmware is not ready!\n"); : printk(BIOS_ERR, "SPM: check dram type and firmware version!\n"); : return -1; : } if (!dyna_load_pcm[index].ready) { printf(BIOS_ERR,...); ... return -1; } pcmdesc = &(...);
Yu-Ping Wu has uploaded a new patch set (#49) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 520 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/49
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 49:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34545/45/src/mainboard/google/kukui... File src/mainboard/google/kukui/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34545/45/src/mainboard/google/kukui... PS45, Line 206: "SPM initialization failed, suspend/resume may fail.\n");
"Failed to init SPM, suspend/resume may fail.\n" […]
Done
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 320: = NULL
no need to init since we're not using it before it's assigned.
Done
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 334: : if (dyna_load_pcm[index].ready) : pcmdesc = &(dyna_load_pcm[index].desc); : else { : printk(BIOS_ERR, "SPM: firmware is not ready!\n"); : printk(BIOS_ERR, "SPM: check dram type and firmware version!\n"); : return -1; : }
if (!dyna_load_pcm[index].ready) { […]
Done
Yu-Ping Wu has uploaded a new patch set (#51) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 522 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/51
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 51:
(1 comment)
printk or die?
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/46/src/soc/mediatek/mt8183/sp... PS46, Line 248: if (fw_size == 0) : printk(BIOS_ERR, "SPM file: %s not found!!!\n", : dyna_load_pcm_path[index]); :
shouldn't we return now if fw_size is 0?
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 53: Code-Review+2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 53:
(19 comments)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 574: const char *version; /* PCM code version */ Rather than doing complicated offsetof calculations in your code, please just define a sub-structure for the parts of this that are actually in the binary format, and nest the two.
edit: or rather, get rid of these first two members entirely because you can get the same thing from struct dyna_load_pcm_t (see other comment).
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 576: const Your code is writing into these, you shouldn't call them const.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 590: dyna_load_pcm_t nit: we generally don't end struct names in a _t
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 591: char path[128]; Why is this here? You don't seem to be using it.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 600: check_member(mtk_spm_regs, poweron_config_set, 0x0000); nit: there's really no need to check the first member
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 601: check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974); nit: put right under the struct
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 27: struct dyna_load_pcm_t dyna_load_pcm[DYNA_LOAD_PCM_MAX]; I don't understand the purpose of this struct. You're only loading a single PCM blob per boot, you'll only ever fill out one of these elements. There's no reason why this needs to be an array *or* a global, you should be able to get by with just a single, stack-local dyna_load_pcm_t in spm_init().
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 229: [DYNA_LOAD_PCM_MAX] = "pcm_path_max", This doesn't seem to be used?
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 250: dyna_load_pcm_path[index]); nit: just use file_name and it might fit on the same line? (Also, extra exclamation marks don't really add anything...)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 255: offset = 0; I'm really having a lot of trouble following the data layout you're parsing here. Can you please add a big comment somewhere explaining the layout, e.g.:
/* * u16 firmware_size; -- counts in u32s * u8 firmware_code[firmware_size * 4]; * struct pcm_desc descriptor; * char version[]; */
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 259: printk(BIOS_INFO, "spm: copy_size = %d\n", copy_size); nit: This always prints "2", do you really need this (especially at INFO)?
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 260: printk(BIOS_INFO, "spm: firmware_size = %d\n", firmware_size); nit: Isn't this just the size of the PCM descriptor? Also, I think it would be clearer to print it in bytes (not dwords).
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 263: offset += copy_size; You should check that you're not overrunning the amount of data you loaded (fw_size) with all of these (especially the snprintf() at the end).
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 268: dyna_load_pcm[index].buf); nit: This is always going to print the same address, do you really need that in production code?
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 270: /* start of pcm_desc */ I assume there's some external reason why this data format needs to be like this (firmware binary first, then descriptor)? Because it would be much easier to parse if you packaged it the other way round...
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 277: snprintf(dyna_load_pcm[index].version, Something needs to make sure the input string is terminated here. If you don't store the length of this in the format I guess the best you can do is
spm_bin[fw_size - 1] = '\0';
Also, is there any reason you're even copying this out? I don't really see it. If all you want to do is print it, I would just print it here and be done with it (or at least only pass a pointer to it around).
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 281: pdesc->base = (u32 *)dyna_load_pcm[index].buf; I am super confused why you have this complicated structure layout, where version and data pointer are stored in dyna_load_pcm_t, and dyna_load_pcm_t contains the struct pcm_desc, but the struct pcm_desc also has a pointer back to the other two things. Why do you need that?
It seems to me that you shouldn't need to store version and base in struct pcm_desc at all. You could just pass the struct dyna_load_pcm_t around to all the functions that currently take a struct pcm_desc, and then you have the version and data pointer in there already.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 283: dyna_load_pcm[index].ready = 1; Does this do anything useful? If you want the caller to know whether the function succeeded (which seems to be the only thing this does), just give it a return value.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 291: printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__, nit: would consider consolidating all this output a little (e.g. you don't really need to print the function name and line), or move some of it to lower notification level. I'd say as a rule of thumb that the whole spm_init() should not print more than one line at INFO when there are no errors.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 53: -Code-Review
Yu-Ping Wu has uploaded a new patch set (#54) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 524 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/54
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 54:
(17 comments)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 574: const char *version; /* PCM code version */
Rather than doing complicated offsetof calculations in your code, please just define a sub-structure […]
"version" and "base" removed.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 576: const
Your code is writing into these, you shouldn't call them const.
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 577: sess These are also not used.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 590: dyna_load_pcm_t
nit: we generally don't end struct names in a _t
Renamed
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 600: check_member(mtk_spm_regs, poweron_config_set, 0x0000);
nit: there's really no need to check the first member
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 601: check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974);
nit: put right under the struct
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 27: struct dyna_load_pcm_t dyna_load_pcm[DYNA_LOAD_PCM_MAX];
I don't understand the purpose of this struct. […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 229: [DYNA_LOAD_PCM_MAX] = "pcm_path_max",
This doesn't seem to be used?
Removed
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 250: dyna_load_pcm_path[index]);
nit: just use file_name and it might fit on the same line? (Also, extra exclamation marks don't real […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 255: offset = 0;
I'm really having a lot of trouble following the data layout you're parsing here. […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 259: printk(BIOS_INFO, "spm: copy_size = %d\n", copy_size);
nit: This always prints "2", do you really need this (especially at INFO)?
Removed
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 263: offset += copy_size;
You should check that you're not overrunning the amount of data you loaded (fw_size) with all of the […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 268: dyna_load_pcm[index].buf);
nit: This is always going to print the same address, do you really need that in production code?
@dawei Please respond to this.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 270: /* start of pcm_desc */
I assume there's some external reason why this data format needs to be like this (firmware binary fi […]
@dawei Any comment on this?
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 281: pdesc->base = (u32 *)dyna_load_pcm[index].buf;
I am super confused why you have this complicated structure layout, where version and data pointer a […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 283: dyna_load_pcm[index].ready = 1;
Does this do anything useful? If you want the caller to know whether the function succeeded (which s […]
Done
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 291: printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__,
nit: would consider consolidating all this output a little (e.g. […]
@dawei Please address this.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 54:
(3 comments)
Thanks Yu-Ping support, and Hung-Te/Julius review this patch.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 268: dyna_load_pcm[index].buf);
@dawei Please respond to this.
It is just for debug purpose only. (If we meet issue, we might know address and dump whole dram context by ICE/T32) Actually I agree that we don't really need it, we can remove it.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 270: /* start of pcm_desc */
@dawei Any comment on this?
Do you mean if we could use the other format to package this FW? If yes, sorry that please understand that we really can't change it since it was a fixed version for few years.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 291: printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__,
@dawei Please address this.
Could we change all INFO to DEBUG here, and I could remove function name and line as well.
Yu-Ping Wu has uploaded a new patch set (#55) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 522 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/55
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 55:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 591: char path[128];
Why is this here? You don't seem to be using it.
@dawei
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 268: dyna_load_pcm[index].buf);
It is just for debug purpose only. […]
Debugging message removed.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 270: /* start of pcm_desc */
Do you mean if we could use the other format to package this FW? If yes, sorry that please understan […]
I think that's understandable.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 277: snprintf(dyna_load_pcm[index].version,
Something needs to make sure the input string is terminated here. […]
@dawei Do we really need 'version'?
https://review.coreboot.org/c/coreboot/+/34545/55/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/55/src/soc/mediatek/mt8183/sp... PS55, Line 286: assert(offset <= file_size); @jwerner @hungte I'm not sure if this is correct.
DAWEI CHIEN has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 55:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 277: snprintf(dyna_load_pcm[index].version,
@dawei Do we really need 'version'?
Hi Yu-Ping, Yes, I agree that we could just print "version" here as well, and don't need define a struct member for it. (version number is for debug purpose)
Yu-Ping Wu has uploaded a new patch set (#56) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch supports SPM suspend and SPM firmware loading. SPM needs its own firmware to do these power-save in the right time with correct condition. After linux PM suspends, SPM could turn off power for the last CPU and do more power-save for SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 512 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/56
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 56:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 277: snprintf(dyna_load_pcm[index].version,
Hi Yu-Ping, […]
"version" removed from struct dyna_load_pcm.
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/sp... PS53, Line 291: printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__,
Could we change all INFO to DEBUG here, and I could remove function name and line as well.
I changed all INFO's to DEBUG's except 2 of them.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 56:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/55/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/55/src/soc/mediatek/mt8183/sp... PS55, Line 286: assert(offset <= file_size);
@jwerner @hungte […]
I'll tested by myself.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 56: Code-Review-1
Not tested yet.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 56:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 577: sess
These are also not used.
Ack
Yu-Ping Wu has uploaded a new patch set (#57) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 509 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/57
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 57: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/57/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/57/src/soc/mediatek/mt8183/sp... PS57, Line 236: * u8 binary[firmware_size * 4] Change to u32 binary[firmware_size]
Yu-Ping Wu has uploaded a new patch set (#58) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 508 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/58
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 58: Code-Review-1
(1 comment)
Not tested yet.
https://review.coreboot.org/c/coreboot/+/34545/57/src/soc/mediatek/mt8183/sp... File src/soc/mediatek/mt8183/spm.c:
https://review.coreboot.org/c/coreboot/+/34545/57/src/soc/mediatek/mt8183/sp... PS57, Line 236: * u8 binary[firmware_size * 4]
Change to […]
Done
Yu-Ping Wu has uploaded a new patch set (#59) to the change originally created by DAWEI CHIEN. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 507 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/59
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 59:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/spm.h:
https://review.coreboot.org/c/coreboot/+/34545/53/src/soc/mediatek/mt8183/in... PS53, Line 591: char path[128];
@dawei
'path' removed from struct dyna_load_pcm.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 59: Code-Review+1
Suspend/resume passes
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
Patch Set 59: Code-Review+2
Seems issues all addressed, thanks so much!
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34545 )
Change subject: mediatek/mt8183: Init SPM driver ......................................................................
mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal.
BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien dawei.chien@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/spm.c 4 files changed, 507 insertions(+), 49 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 7b00d94..844496d 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -28,6 +28,7 @@ #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> +#include <soc/spm.h> #include <soc/usb.h> #include <string.h>
@@ -201,6 +202,9 @@ configure_emmc(); configure_usb(); configure_audio(); + if (spm_init()) + printk(BIOS_ERR, + "SPM initialization failed, suspend/resume may fail.\n");
register_reset_to_bl31(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b6c3a33..d1171ef 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += spm.c ramstage-y += sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c @@ -62,8 +63,20 @@ ramstage-y += ../common/wdt.c ramstage-y += md_ctrl.c
+MT8183_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8183 + +cbfs-files-y += pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-file := $(MT8183_BLOB_DIR)/pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-type := raw +pcm_allinone_lp4_3200.bin-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-file := $(MT8183_BLOB_DIR)/pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-type := raw +pcm_allinone_lp4_3733.bin-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += sspm.bin -sspm.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/sspm.bin +sspm.bin-file := $(MT8183_BLOB_DIR)/sspm.bin sspm.bin-type := raw sspm.bin-compression := $(CBFS_COMPRESS_FLAG)
diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 5e7770e..4ca72b6 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -16,12 +16,122 @@ #ifndef SOC_MEDIATEK_MT8183_SPM_H #define SOC_MEDIATEK_MT8183_SPM_H
+#include <arch/barrier.h> +#include <console/console.h> #include <soc/addressmap.h> +#include <string.h> +#include <stdint.h> #include <types.h>
-enum { - SPM_PROJECT_CODE = 0xb16 -}; +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ + +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK (1U << 6) /* 1b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ + +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ + +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define WAKEUP_EVENT_MASK_B_BIT0 (1U << 0) /* 1b */ + +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ + +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_OFFSET (1U << 3) /* 1b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ + +/* SPM_SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_BIT0 (1U << 0) /* 1b */ +#define SPARE_ACK_MASK_B_BIT1 (1U << 1) /* 1b */ + +/************************************** + * Config and Parameter + **************************************/ +#define CONN_DDR_EN_DBC_LEN (0x00000154 << 20) +#define IFR_SRAMROM_ROM_PDN (0x0000003f) +#define IM_STATE (0x4 << 7) +#define IM_STATE_MASK (0x7 << 7) +#define MD_DDR_EN_0_DBC_LEN (0x00000154) +#define MD_DDR_EN_1_DBC_LEN (0x00000154 << 10) +#define PCM_FSM_STA_DEF (0x00108490) +#define PCM_FSM_STA_MASK (0x7FFFFF) +#define POWER_ON_VAL1_DEF (0x00015800) +#define SPM_CORE_TIMEOUT (5000) +#define SPM_MAS_PAUSE_MASK_B_VAL (0xFFFFFFFF) +#define SPM_MAS_PAUSE2_MASK_B_VAL (0xFFFFFFFF) +#define SPM_PCM_REG1_DATA_CHECK (0x1) +#define SPM_PCM_REG15_DATA_CHECK (0x0) +#define SPM_WAKEUP_EVENT_MASK_DEF (0xF0F92218) +#define SYSCLK1_EN_CTRL (0x3 << 2) +#define SYSCLK1_SRC_MASK_B (0x10 << 23) + +/************************************** + * Define and Declare + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ_AUX (0x3FF00) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM (ISRS_TWAM) +#define ISRC_ALL_EXC_TWAM (ISRS_PCM_RETURN) +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL (0x3FF)
enum { DISP_SRAM_PDN_MASK = 0x1 << 8, @@ -30,6 +140,8 @@ AUDIO_SRAM_ACK_MASK = 0xf << 12, };
+#define PCM_EVENT_VECTOR_NUM 16 + struct mtk_spm_regs { u32 poweron_config_set; u32 spm_power_on_val0; @@ -47,22 +159,7 @@ u32 pcm_wdt_val; u32 pcm_im_host_rw_ptr; u32 pcm_im_host_rw_dat; - u32 pcm_event_vector0; - u32 pcm_event_vector1; - u32 pcm_event_vector2; - u32 pcm_event_vector3; - u32 pcm_event_vector4; - u32 pcm_event_vector5; - u32 pcm_event_vector6; - u32 pcm_event_vector7; - u32 pcm_event_vector8; - u32 pcm_event_vector9; - u32 pcm_event_vector10; - u32 pcm_event_vector11; - u32 pcm_event_vector12; - u32 pcm_event_vector13; - u32 pcm_event_vector14; - u32 pcm_event_vector15; + u32 pcm_event_vector[PCM_EVENT_VECTOR_NUM]; u32 pcm_event_vector_en; u32 reserved1[1]; u32 spm_sram_rsv_con; @@ -472,37 +569,30 @@ u32 spm_ack_chk_sta4; u32 spm_ack_chk_latch4; }; - -check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); -check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); -check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); -check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); -check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); -check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); -check_member(mtk_spm_regs, vde_pwr_con, 0x0300); -check_member(mtk_spm_regs, ufs_sram_con, 0x036c); -check_member(mtk_spm_regs, dummy_sram_con, 0x0380); -check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); -check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); -check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); -check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); -check_member(mtk_spm_regs, root_cputop_addr, 0x0570); -check_member(mtk_spm_regs, cpu_spare_con, 0x0580); -check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); -check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); -check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); -check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); -check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); -check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); -check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780); -check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800); -check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0); -check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900); -check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920); -check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940); -check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960); check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
+enum dyna_load_pcm_index { + DYNA_LOAD_PCM_SUSPEND_LP4_3733 = 0, + DYNA_LOAD_PCM_SUSPEND_LP4_3200, + DYNA_LOAD_PCM_MAX, +}; + +struct pcm_desc { + u16 size; /* binary array size */ + u8 sess; /* session number */ + u8 replace; /* replace mode */ + u16 addr_2nd; /* 2nd binary array size */ + u16 reserved; /* for 32bit alignment */ + u32 vector[PCM_EVENT_VECTOR_NUM]; /* event vector config */ +}; + +struct dyna_load_pcm { + u32 *buf; /* binary array */ + struct pcm_desc desc; +}; + +int spm_init(void); + #endif /* SOC_MEDIATEK_MT8183_SPM_H */ diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c new file mode 100644 index 0000000..669970f --- /dev/null +++ b/src/soc/mediatek/mt8183/spm.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <cbfs.h> +#include <delay.h> +#include <device/mmio.h> +#include <endian.h> +#include <soc/emi.h> +#include <soc/spm.h> +#include <timer.h> + +#define BUF_SIZE (16 * KiB) +static uint8_t spm_bin[BUF_SIZE] __aligned(8); + +static int spm_register_init(void) +{ + u32 pcm_fsm_sta; + + write32(&mtk_spm->poweron_config_set, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta); + + if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) { + printk(BIOS_ERR, "PCM reset failed\n"); + return -1; + } + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | EVENT_LOCK_EN_LSB | + SPM_SRAM_ISOINT_B_LSB | MIF_APBEN_LSB | + SCP_APB_INTERNAL_EN_LSB); + write32(&mtk_spm->pcm_im_ptr, 0); + write32(&mtk_spm->pcm_im_len, 0); + + write32(&mtk_spm->spm_clk_con, + read32(&mtk_spm->spm_clk_con) | SYSCLK1_EN_CTRL | + SPM_LOCK_INFRA_DCM_LSB | EXT_SRCCLKEN_MASK | + CXO32K_REMOVE_EN_MD1_LSB | + CLKSQ1_SEL_CTRL_LSB | SRCLKEN0_EN_LSB | SYSCLK1_SRC_MASK_B); + + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->ddr_en_dbc_len, + MD_DDR_EN_0_DBC_LEN | + MD_DDR_EN_1_DBC_LEN | + CONN_DDR_EN_DBC_LEN); + + clrsetbits_le32(&mtk_spm->spare_ack_mask, + SPARE_ACK_MASK_B_BIT1, + SPARE_ACK_MASK_B_BIT0); + + write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN); + write32(&mtk_spm->spm_pc_trace_con, + SPM_PC_TRACE_OFFSET | + SPM_PC_TRACE_HW_EN_LSB); + + setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); + + return 0; +} + +static int spm_code_swapping(void) +{ + u32 con1; + + con1 = read32(&mtk_spm->spm_wakeup_event_mask); + + write32(&mtk_spm->spm_wakeup_event_mask, + con1 & ~WAKEUP_EVENT_MASK_B_BIT0); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + + if (!wait_us(SPM_CORE_TIMEOUT, + read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB)) { + printk(BIOS_ERR, + "timeout: r15=%#x, pcmsta=%#x, irqsta=%#x [%d]\n", + read32(&mtk_spm->pcm_reg15_data), + read32(&mtk_spm->pcm_fsm_sta), + read32(&mtk_spm->spm_irq_sta), + SPM_CORE_TIMEOUT); + return -1; + } + + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, con1); + return 0; +} + +static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) +{ + u32 con1, pcm_fsm_sta; + + if (read32(&mtk_spm->pcm_reg1_data) == SPM_PCM_REG1_DATA_CHECK && + read32(&mtk_spm->pcm_reg15_data) != SPM_PCM_REG15_DATA_CHECK) { + if (spm_code_swapping()) + return -1; + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + write32(&mtk_spm->pcm_pwr_io_en, 0); + + clrsetbits_le32(&mtk_spm->pcm_con1, + PCM_TIMER_EN_LSB, + SPM_REGWR_CFG_KEY); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta); + + if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) { + printk(BIOS_ERR, "reset pcm(PCM_FSM_STA=%#x)\n", + read32(&mtk_spm->pcm_fsm_sta)); + return -1; + } + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + + con1 = read32(&mtk_spm->pcm_con1) & PCM_WDT_WAKE_MODE_LSB; + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + EVENT_LOCK_EN_LSB | SPM_SRAM_ISOINT_B_LSB | + (pcmdesc->replace ? 0 : IM_NONRP_EN_LSB) | + MIF_APBEN_LSB | SCP_APB_INTERNAL_EN_LSB); + + return 0; +} + +static void spm_load_pcm_code(const struct dyna_load_pcm *pcm) +{ + int i; + + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | IM_SLAVE_LSB); + + for (i = 0; i < pcm->desc.size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, + PCM_IM_HOST_EN_LSB | PCM_IM_HOST_W_EN_LSB | i); + write32(&mtk_spm->pcm_im_host_rw_dat, + (u32) *(pcm->buf + i)); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_check_pcm_code(const struct dyna_load_pcm *pcm) +{ + int i; + + for (i = 0; i < pcm->desc.size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | i); + if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != + (u32) *(pcm->buf + i)) + spm_load_pcm_code(pcm); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) +{ + u32 con0; + + spm_load_pcm_code(pcm); + spm_check_pcm_code(pcm); + + printk(BIOS_DEBUG, "%s: ptr = %p\n", __func__, pcm->buf); + printk(BIOS_DEBUG, "%s: len = %d\n", __func__, pcm->desc.size); + + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | + PCM_CK_EN_LSB | IM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + for (int i = 0; i < PCM_EVENT_VECTOR_NUM; i++) + write32(&mtk_spm->pcm_event_vector[i], pcmdesc->vector[i]); +} + +static const char * const dyna_load_pcm_path[] = { + [DYNA_LOAD_PCM_SUSPEND_LP4_3733] = "pcm_allinone_lp4_3733.bin", + [DYNA_LOAD_PCM_SUSPEND_LP4_3200] = "pcm_allinone_lp4_3200.bin", +}; + +static int spm_load_firmware(enum dyna_load_pcm_index index, + struct dyna_load_pcm *pcm) +{ + /* + * Layout: + * u16 firmware_size + * u32 binary[firmware_size] + * struct pcm_desc descriptor + * char *version + */ + u16 firmware_size; + int copy_size; + const char *file_name = dyna_load_pcm_path[index]; + struct stopwatch sw; + + stopwatch_init(&sw); + + size_t file_size = cbfs_boot_load_file(file_name, spm_bin, + sizeof(spm_bin), CBFS_TYPE_RAW); + + if (file_size == 0) { + printk(BIOS_ERR, "SPM binary %s not found\n", file_name); + return -1; + } + + int offset = 0; + + /* firmware size */ + copy_size = sizeof(firmware_size); + memcpy(&firmware_size, spm_bin + offset, copy_size); + printk(BIOS_DEBUG, "SPM: binary array size = %d\n", firmware_size); + offset += copy_size; + + /* binary */ + assert(offset < file_size); + copy_size = firmware_size * 4; + pcm->buf = (u32 *)(spm_bin + offset); + offset += copy_size; + + /* descriptor */ + assert(offset < file_size); + copy_size = sizeof(struct pcm_desc); + memcpy((void *)&(pcm->desc.size), spm_bin + offset, copy_size); + offset += copy_size; + + /* version */ + /* The termintating character should be contained in the spm binary */ + assert(spm_bin[file_size - 1] == '\0'); + assert(offset < file_size); + printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset); + + printk(BIOS_INFO, "SPM binary loaded in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + return 0; +} + +static void spm_kick_pcm_to_run(void) +{ + uint32_t con0; + + write32(&mtk_spm->spm_mas_pause_mask_b, SPM_MAS_PAUSE_MASK_B_VAL); + write32(&mtk_spm->spm_mas_pause2_mask_b, SPM_MAS_PAUSE2_MASK_B_VAL); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + write32(&mtk_spm->pcm_pwr_io_en, PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7); + + printk(BIOS_DEBUG, "SPM: %s\n", __func__); + + /* check IM ready */ + while ((read32(&mtk_spm->pcm_fsm_sta) & IM_STATE_MASK) != IM_STATE) + ; + + /* kick PCM to run, and toggle PCM_KICK */ + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + printk(BIOS_DEBUG, "SPM: %s done\n", __func__); +} + +int spm_init(void) +{ + struct pcm_desc *pcmdesc; + enum dyna_load_pcm_index index; + struct stopwatch sw; + + stopwatch_init(&sw); + + if (CONFIG(MT8183_DRAM_EMCP)) + index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; + else + index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; + + printk(BIOS_DEBUG, "SPM: pcm index = %d\n", index); + + struct dyna_load_pcm pcm; + if (spm_load_firmware(index, &pcm)) { + printk(BIOS_ERR, "SPM: firmware is not ready\n"); + printk(BIOS_ERR, "SPM: check dram type and firmware version\n"); + return -1; + } + + pcmdesc = &pcm.desc; + + if (spm_register_init()) + return -1; + + if (spm_reset_and_init_pcm(pcmdesc)) + return -1; + + spm_kick_im_to_fetch(&pcm); + spm_init_pcm_register(); + spm_init_event_vector(pcmdesc); + spm_kick_pcm_to_run(); + + printk(BIOS_INFO, "SPM: %s done in %ld msecs\n", __func__, + stopwatch_duration_msecs(&sw)); + + return 0; +}
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