coreboot-gerrit June 2019

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Change in ...coreboot[master]: crossgcc: Upgrade GCC to 9.1.0
by HAOUAS Elyes (Code Review) 15 Mar '20

15 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32564 Change subject: crossgcc: Upgrade GCC to 9.1.0 ...................................................................... crossgcc: Upgrade GCC to 9.1.0 Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch R util/crossgcc/patches/gcc-9.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-9.1.0_gnat.patch R util/crossgcc/patches/gcc-9.1.0_libgcc.patch D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum A util/crossgcc/sum/gcc-9.1.0.tar.xz.cksum 7 files changed, 2 insertions(+), 21,021 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32564/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Gerrit-Change-Number: 32564 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: add support for CannonPoint-LP
by Matt DeVillier (Code Review) 15 Mar '20

15 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33411 Change subject: inteltool: add support for CannonPoint-LP ...................................................................... inteltool: add support for CannonPoint-LP Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from Intel 300 Series Chipset Family On-Package Platform Controller Hub, Datasheet volume 1 of 2, document #337867-002 Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 --- M util/inteltool/Makefile M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c M util/inteltool/platform.h A util/inteltool/platform_cannonlake_lp.c 8 files changed, 373 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33411/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index c71c711..0ee1991 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,8 @@ CPPFLAGS += -I$(top)/src/commonlib/include PLATFORMS = platform_sunrise.o platform_apollolake.o platform_cannonlake.o \ - platform_denverton.o platform_lynxpoint.o platform_i631x.o + platform_cannonlake_lp.o platform_denverton.o \ + platform_lynxpoint.o platform_i631x.o OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 670ecf3..e9a919f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -345,6 +345,7 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 27df34b..f3743bf 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -129,6 +129,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: + community_count = cannonlake_pch_lp_communities_count; + communities = cannonlake_pch_lp_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 7e02510..f1a4c76 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -137,6 +137,10 @@ "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1, + "8th generation (Coffee Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2, + "8th generation (Whiskey Lake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -246,6 +250,8 @@ "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM, + "Cannon Point-LP U Premium/CoffeeLake/Whiskeylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c930..e26c229 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -155,6 +155,7 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b +#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -276,6 +277,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */ /* Intel GPUs */ diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620..9323362 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -119,6 +119,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: sbbar_phys = 0xfd000000; use_p2sb = false; break; diff --git a/util/inteltool/platform.h b/util/inteltool/platform.h index d5fa8e6..8fd674b 100644 --- a/util/inteltool/platform.h +++ b/util/inteltool/platform.h @@ -25,6 +25,9 @@ extern const struct gpio_community *const cannonlake_pch_h_communities[]; size_t cannonlake_pch_h_communities_count; +extern const struct gpio_community *const cannonlake_pch_lp_communities[]; +size_t cannonlake_pch_lp_communities_count; + extern const struct gpio_community *const denverton_communities[]; size_t denverton_communities_count; diff --git a/util/inteltool/platform_cannonlake_lp.c b/util/inteltool/platform_cannonlake_lp.c new file mode 100644 index 0000000..b3a2eaf --- /dev/null +++ b/util/inteltool/platform_cannonlake_lp.c @@ -0,0 +1,351 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2019 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "inteltool.h" +#include "gpio.h" +#include "platform.h" + +const char *const cannonlake_pch_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_a_names, +}; + +const char *const cannonlake_pch_lp_group_b_names[] = { + "GPP_B0", "Reserved", "n/a", + "GPP_B1", "Reserved", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", +}; + +const struct gpio_group cannonlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_b_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_b_names, +}; + +const char *const cannonlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_c_names, +}; + +const char *const cannonlake_pch_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_d_names, +}; + +const char *const cannonlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "n/a", "n/a", + "GPP_E2", "SATAXPCIE2", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "DISP_MISC0", "n/a", + "GPP_E14", "DDPC_HPD1", "DISP_MISC1", "n/a", + "GPP_E15", "DDPD_HPD2", "DISP_MISC2", "n/a", + "GPP_E16", "n/a", "DISP_MISC3", "n/a", + "GPP_E17", "EDP_HPD", "DISP_MISC4", "n/a", + "GPP_E18", "DPPB_CTRLCLK", "n/a", "CNV_BT_HOST_WAKE#", + "GPP_E19", "DPPB_CTRLDATA", "n/a", "CNV_BT_IF_SELECT", + "GPP_E20", "DPPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DPPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "DPPD_CTRLCLK", "n/a", "n/a", + "GPP_E23", "DPPD_CTRLDATA", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_e_names, +}; + +const char *const cannonlake_pch_lp_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", + "GPP_F14", "n/a", "PS_ON#", + "GPP_F15", "USB2_OC4#", "n/a", + "GPP_F16", "USB2_OC5#", "n/a", + "GPP_F17", "USB2_OC6#", "n/a", + "GPP_F18", "USB2_OC7#", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", + "GPP_F22", "DDPF_CTRLCLK", "n/a", + "GPP_F23", "DDPF_CTRLDATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_f_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_f_names, +}; + +const char *const cannonlake_pch_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", + "GPP_G1", "SD_DATA0", + "GPP_G2", "SD_DATA1", + "GPP_G3", "SD_DATA2", + "GPP_G4", "SD_DATA3", + "GPP_G5", "SD3_CD#", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +const struct gpio_group cannonlake_pch_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_g_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_g_names, +}; + +const char *const cannonlake_pch_lp_group_h_names[] = { + "GPP_H0", "I2S2_SCLK", "CNV_BT_I2S_SCLK", "n/a", + "GPP_H1", "I2S2_SFRM", "CNV_BT_I2S_BCLK", "CNV_RF_RESET#", + "GPP_H2", "I2S2_TXD", "CNV_BT_I2S_SDI", "MODEM_CLKREQ", + "GPP_H3", "I2S2_RXD", "CNV_BT_I2S_SDO", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "n/a", "n/a", + "GPP_H9", "I2C4_SCL", "n/a", "n/a", + "GPP_H10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_H11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "n/a", "n/a", "n/a", + "GPP_H17", "n/a", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "n/a", "n/a", "n/a", + "GPP_H22", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_h_names, +}; + +const char *const cannonlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; +const struct gpio_group cannonlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_gpd_names, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { + &cannonlake_pch_lp_group_a, + &cannonlake_pch_lp_group_b, + &cannonlake_pch_lp_group_g, +}; +const struct gpio_community cannonlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_0_groups), + .groups = cannonlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = { + &cannonlake_pch_lp_group_d, + &cannonlake_pch_lp_group_f, + &cannonlake_pch_lp_group_h, +}; +const struct gpio_community cannonlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_1_groups), + .groups = cannonlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_2_groups[] = { + &cannonlake_pch_lp_group_gpd, +}; + +const struct gpio_community cannonlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_2_groups), + .groups = cannonlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { + &cannonlake_pch_lp_group_c, + &cannonlake_pch_lp_group_e, +}; + +const struct gpio_community cannonlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_4_groups), + .groups = cannonlake_pch_lp_community_4_groups, +}; + +const struct gpio_community *const cannonlake_pch_lp_communities[] = { + &cannonlake_pch_lp_community_0, + &cannonlake_pch_lp_community_1, + &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_4, +}; + +size_t cannonlake_pch_lp_communities_count = ARRAY_SIZE(cannonlake_pch_lp_communities); -- To view, visit https://review.coreboot.org/c/coreboot/+/33411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 Gerrit-Change-Number: 33411 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in ...coreboot[master]: google/kukui: DRAM freq switch to 2400Mbps
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30613 Change subject: google/kukui: DRAM freq switch to 2400Mbps ...................................................................... google/kukui: DRAM freq switch to 2400Mbps Forcing DRAM frequency 2400Mbps. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/emi.c 3 files changed, 53 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30613/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d2..555bb02 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -17,8 +17,8 @@ struct sdram_params params = { .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} + [ODT_OFF] = {0x5, 0x6, 0x0, 0xF}, + [ODT_ON] = {0x6, 0x9, 0x0, 0xE} }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9197ceb..551205f 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -126,17 +126,17 @@ {&ch[0].phy.pll2, 0x00000000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607c0}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[0].phy.shu[0].pll[4], 0xe5780000}, {&ch[0].phy.shu[0].pll[6], 0xe5780000}, @@ -146,15 +146,15 @@ {&ch[0].ao.dvfsdll, 0x00000000}, {&ch[0].phy.shu[0].ca_dll[0], 0x00698619}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.b[0].dq[7], 0x00000055}, {&ch[0].phy.b[1].dq[7], 0x00000055}, {&ch[0].phy.ca_cmd[7], 0x00000055}, {&ch[0].phy.ca_cmd[2], 0x00200000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.pll4, 0x000c0000}, {&ch[0].phy.pll1, 0x00000000}, {&ch[0].phy.pll2, 0x00000000}, @@ -169,26 +169,26 @@ {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[0].phy.shu[0].pll[8], 0x00040000}, {&ch[0].phy.shu[0].pll[10], 0x00040000}, - {&ch[0].phy.shu[0].pll[5], 0x7b000002}, - {&ch[0].phy.shu[0].pll[7], 0x7b000002}, + {&ch[0].phy.shu[0].pll[5], 0x5c000002}, + {&ch[0].phy.shu[0].pll[7], 0x5c000002}, {&ch[0].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[0].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[0].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x028604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x02C607C0}, {&ch[0].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.pll1, 0x80000000}, {&ch[0].phy.pll2, 0x80000000}, {&ch[0].phy.pll4, 0x004d0000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, {&ch[0].phy.ca_dll_fine_tune[3], 0x000ba000}, {&ch[0].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[0].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -208,14 +208,6 @@ {&ch[0].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[0].phy.shu[0].pll[5], 0x7b000003}, - {&ch[0].phy.shu[0].pll[7], 0x7b000003}, - {&ch[0].phy.shu[0].pll[14], 0x00000002}, - {&ch[0].phy.shu[0].pll20, 0x00000002}, - {&ch[0].phy.shu[0].pll[14], 0x02080002}, - {&ch[0].phy.shu[0].pll20, 0x02080002}, - {&ch[0].phy.shu[0].pll[15], 0x0c030000}, - {&ch[0].phy.shu[0].pll21, 0x0c030000}, {&ch[1].phy.shu[0].pll[4], 0x00000000}, {&ch[1].phy.shu[0].pll[6], 0x00000000}, {&ch[1].phy.misc_shu_opt, 0x00090909}, @@ -224,15 +216,15 @@ {&ch[1].ao.dvfsdll, 0x00000000}, {&ch[1].phy.shu[0].ca_dll[0], 0xc0778609}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.b[0].dq[7], 0x00000055}, {&ch[1].phy.b[1].dq[7], 0x00000055}, {&ch[1].phy.ca_cmd[7], 0x00000055}, {&ch[1].phy.ca_cmd[2], 0x00200000}, {&ch[1].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.pll4, 0x00000000}, {&ch[1].phy.pll1, 0x00000000}, {&ch[1].phy.pll2, 0x00000000}, @@ -247,26 +239,26 @@ {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[1].phy.shu[0].pll[8], 0x00040000}, {&ch[1].phy.shu[0].pll[10], 0x00040000}, - {&ch[1].phy.shu[0].pll[5], 0x7b000000}, - {&ch[1].phy.shu[0].pll[7], 0x7b000000}, + {&ch[1].phy.shu[0].pll[5], 0x5c000000}, + {&ch[1].phy.shu[0].pll[7], 0x5c000000}, {&ch[1].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[1].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[1].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x02860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x02C60740}, {&ch[1].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.pll1, 0x80000000}, {&ch[1].phy.pll2, 0x80000000}, {&ch[1].phy.pll4, 0x00410000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&ch[1].phy.ca_dll_fine_tune[3], 0x0003a000}, {&ch[1].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[1].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -286,14 +278,6 @@ {&ch[1].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[1].phy.shu[0].pll[5], 0x00000001}, - {&ch[1].phy.shu[0].pll[7], 0x00000001}, - {&ch[1].phy.shu[0].pll[14], 0x00000002}, - {&ch[1].phy.shu[0].pll20, 0x00000002}, - {&ch[1].phy.shu[0].pll[14], 0x02080000}, - {&ch[1].phy.shu[0].pll20, 0x02080000}, - {&ch[1].phy.shu[0].pll[15], 0x0c030000}, - {&ch[1].phy.shu[0].pll21, 0x0c030000}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.drsctrl, 0x20080000}, {&ch[0].ao.ckectrl, 0x08100400}, @@ -431,12 +415,12 @@ {&ch[0].ao.shu[0].rk[1].selph_dq[2], 0x33333333}, {&ch[0].ao.shu[0].rk[1].selph_dq[3], 0x33333333}, {&ch[0].ao.shu[0].dqsg_retry, 0x8120050c}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].ao.shu[0].dqs2dq_tx, 0x00000000}, {&ch[0].ao.shu[0].odtctrl, 0xc0010003}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].phy.r[0].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[1].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[0].b[1].rxdvs[2], 0x20000000}, @@ -468,10 +452,10 @@ {&ch[0].phy.b[0].dq[6], 0x010352e9}, {&ch[0].phy.b[1].dq[6], 0x010352e9}, {&ch[0].phy.ca_cmd[6], 0x00034269}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.b[0].dq[5], 0x82110e00}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.b[1].dq[5], 0x82110e00}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.b[0].dq[5], 0x82110E00}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, + {&ch[0].phy.b[1].dq[5], 0x82110E00}, {&ch[0].phy.b[0].dq[8], 0x00000007}, {&ch[0].phy.b[1].dq[8], 0x00000007}, {&ch[0].phy.ca_cmd[9], 0x00010007}, @@ -502,16 +486,16 @@ {&ch[0].phy.ca_cmd[8], 0x00080a0a}, {&ch[0].ao.shu[0].misc, 0x0000f132}, {&ch[0].ao.shu[0].dqsg, 0x02a19800}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, {&ch[0].phy.shu[0].ca_cmd[5], 0x00000000}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.shu[0].impcal1, 0x81080004}, {&ch[0].ao.srefctrl, 0x4840f000}, @@ -600,10 +584,10 @@ /* dramc duty calibration */ {&ch[0].phy.shu[0].rk[0].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x00000000}, + {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x11000000}, {&ch[0].phy.shu[0].rk[1].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[3], 0x00000400}, + {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x11000000}, + {&ch[0].phy.shu[0].ca_cmd[3], 0x00000600}, {&ch[0].phy.shu[0].rk[0].b[0].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[0].b[1].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[1].b[0].dq[1], 0x00110000}, diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index bb617f9..4d05dd0 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -272,10 +272,10 @@ { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); + 0xff << 16, 0x48 << 16); clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, 0x5B << 0); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Gerrit-Change-Number: 30613 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Use absolute jump address
by Nitheesh Sekar (Code Review) 11 Mar '20

11 Mar '20

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32388 Change subject: TEMP: NOT FOR REVIEW: Use absolute jump address ...................................................................... TEMP: NOT FOR REVIEW: Use absolute jump address When the qcs405 soc jumps from qc_sec to bootblock, the pc is at 0x0 address mapped to actual SRAM address(0x8c30000). The mapping happens in a hardware block 'boot-remapper' only for a maximum of 128K possible. If the bootflow continues from the 0x0 address, bootblock references variable beyond 128K crashing the boot. So change the PC to start execting from the absolute address instead. Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32388/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..7dc8b0f 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -23,7 +23,9 @@ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu + ldr x15, =arm64_init_cpu + blr x15 - bl main + ldr x15, =main + blr x15 ENDPROC(_start) -- To view, visit https://review.coreboot.org/c/coreboot/+/32388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Gerrit-Change-Number: 32388 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: drivers/i2c: Add LP5562 LED driver
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

Hello Yuji Sasaki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32692 to review the following change. Change subject: drivers/i2c: Add LP5562 LED driver ...................................................................... drivers/i2c: Add LP5562 LED driver Add LP5562 LED driver in Coreboot. BUG=b:116352348 TEST=Apply board support for LP5562 LED driver, build coreboot. Signed-off-by: Yuji Sasaki <sasakiy(a)chromium.org> Change-Id: I0206dc6bfd367a258af88ab61e0928e32e9aa60f --- A src/drivers/i2c/Kconfig A src/drivers/i2c/Makefile.inc A src/drivers/i2c/lp5562/Kconfig A src/drivers/i2c/lp5562/Makefile.inc A src/drivers/i2c/lp5562/led_lp5562.c A src/drivers/i2c/lp5562/led_lp5562.h A src/drivers/i2c/lp5562/led_lp5562_programs.c A src/drivers/i2c/lp5562/led_lp5562_programs.h 8 files changed, 863 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32692/1 diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig new file mode 100644 index 0000000..47b79e6 --- /dev/null +++ b/src/drivers/i2c/Kconfig @@ -0,0 +1,28 @@ +source src/drivers/i2c/adm1026/Kconfig +source src/drivers/i2c/adm1027/Kconfig +source src/drivers/i2c/adt7463/Kconfig +source src/drivers/i2c/at24rf08c/Kconfig +source src/drivers/i2c/ck505/Kconfig +source src/drivers/i2c/da7219/Kconfig +source src/drivers/i2c/designware/Kconfig +source src/drivers/i2c/generic/Kconfig +source src/drivers/i2c/hid/Kconfig +source src/drivers/i2c/i2cmux/Kconfig +source src/drivers/i2c/i2cmux2/Kconfig +source src/drivers/i2c/lm63/Kconfig +source src/drivers/i2c/lm96000/Kconfig +source src/drivers/i2c/lp5562/Kconfig +source src/drivers/i2c/max98373/Kconfig +source src/drivers/i2c/max98927/Kconfig +source src/drivers/i2c/nau8825/Kconfig +source src/drivers/i2c/nct7802y/Kconfig +source src/drivers/i2c/pca9538/Kconfig +source src/drivers/i2c/pcf8523/Kconfig +source src/drivers/i2c/rt5663/Kconfig +source src/drivers/i2c/rtd2132/Kconfig +source src/drivers/i2c/rx6110sa/Kconfig +source src/drivers/i2c/sx9310/Kconfig +source src/drivers/i2c/tpm/Kconfig +source src/drivers/i2c/w83793/Kconfig +source src/drivers/i2c/w83795/Kconfig +source src/drivers/i2c/ww_ring/Kconfig diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc new file mode 100644 index 0000000..7b5ae0c --- /dev/null +++ b/src/drivers/i2c/Makefile.inc @@ -0,0 +1,28 @@ +subdirs-y += adm1026 +subdirs-y += adm1027 +subdirs-y += adt7463 +subdirs-y += at24rf08c +subdirs-y += ck505 +subdirs-y += da7219 +subdirs-y += designware +subdirs-y += generic +subdirs-y += hid +subdirs-y += i2cmux +subdirs-y += i2cmux2 +subdirs-y += lm63 +subdirs-y += lm96000 +subdirs-y += lp5562 +subdirs-y += max98373 +subdirs-y += max98927 +subdirs-y += nau8825 +subdirs-y += nct7802y +subdirs-y += pca9538 +subdirs-y += pcf8523 +subdirs-y += rt5663 +subdirs-y += rtd2132 +subdirs-y += rx6110sa +subdirs-y += sx9310 +subdirs-y += tpm +subdirs-y += w83793 +subdirs-y += w83795 +subdirs-y += ww_ring diff --git a/src/drivers/i2c/lp5562/Kconfig b/src/drivers/i2c/lp5562/Kconfig new file mode 100644 index 0000000..cd7041a --- /dev/null +++ b/src/drivers/i2c/lp5562/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_LED_LP5562 + bool diff --git a/src/drivers/i2c/lp5562/Makefile.inc b/src/drivers/i2c/lp5562/Makefile.inc new file mode 100644 index 0000000..bfdb408 --- /dev/null +++ b/src/drivers/i2c/lp5562/Makefile.inc @@ -0,0 +1,5 @@ +verstage-$(CONFIG_DRIVERS_I2C_LED_LP5562) += led_lp5562.c +verstage-$(CONFIG_DRIVERS_I2C_LED_LP5562) += led_lp5562_programs.c + +ramstage-$(CONFIG_DRIVERS_I2C_LED_LP5562) += led_lp5562.c +ramstage-$(CONFIG_DRIVERS_I2C_LED_LP5562) += led_lp5562_programs.c diff --git a/src/drivers/i2c/lp5562/led_lp5562.c b/src/drivers/i2c/lp5562/led_lp5562.c new file mode 100644 index 0000000..6eafee3 --- /dev/null +++ b/src/drivers/i2c/lp5562/led_lp5562.c @@ -0,0 +1,430 @@ +/* + * Copyright (C) 2019 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is a driver for the TI LP5562 (http://www.ti.com/product/lp5562), + * driving a tri-color LED. + * + * The only connection between the LED and the main board is an i2c bus. + * + * This driver imitates a depthcharge display device. On initialization the + * driver sets up the controllers to prepare them to accept programs to run. + * + * When a certain vboot state needs to be indicated, the program for that + * state is loaded into the controllers, resulting in the state appropriate + * LED behavior. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/i2c_simple.h> +#include <string.h> + +#include "drivers/i2c/lp5562/led_lp5562_programs.h" + +/* Key lp5562 registers. */ +#define LP5562_ENABLE_REG 0x00 +#define LP5562_OPMODE_REG 0x01 +#define LP5562_PWMREG_B 0x02 +#define LP5562_PWMREG_G 0x03 +#define LP5562_PWMREG_R 0x04 +#define LP5562_CURRENT_B 0x05 +#define LP5562_CURRENT_G 0x06 +#define LP5562_CURRENT_R 0x07 +#define LP5562_CONFIG_REG 0x08 +#define LP5562_ENGINE1_PC 0x09 +#define LP5562_ENGINE2_PC 0x0a +#define LP5562_ENGINE3_PC 0x0b +#define LP5562_STATUS_REG 0x0c +#define LP5562_RESET_REG 0x0d +#define LP5562_PWMREG_W 0x0e +#define LP5562_CURRENT_W 0x0f +#define LP5562_LED_MAP_REG 0x70 +#define LP5562_PROG_MEM_ENG1 0x10 +#define LP5562_PROG_MEM_ENG2 0x30 +#define LP5562_PROG_MEM_ENG3 0x50 + +/* LP5562 ENABLE REG fields. */ +#define LP5562_ENABLE_LOG_EN 0x80 +#define LP5562_ENABLE_CHIP_EN 0x40 +#define LP5562_ENABLE_EXEC_HOLD 0x00 +#define LP5562_ENABLE_EXEC_STEP 0x01 +#define LP5562_ENABLE_EXEC_RUN 0x02 +#define LP5562_ENABLE_EXEC_MASK 0x03 +#define LP5562_ENABLE_ENG1_SHIFT 4 +#define LP5562_ENABLE_ENG2_SHIFT 2 +#define LP5562_ENABLE_ENG3_SHIFT 0 +#define LP5562_ENABLE_ALL_MASK 0x3f +#define LP5562_ENABLE_ALL_HOLD 0x00 +#define LP5562_ENABLE_ALL_RUN 0x2a + +/* LP5562 OPMODE REG fields. */ +#define LP5562_OPMODE_DISABLED 0x00 +#define LP5562_OPMODE_LOAD 0x01 +#define LP5562_OPMODE_RUN 0x02 +#define LP5562_OPMODE_DIRECT 0x03 +#define LP5562_OPMODE_MASK 0x03 +#define LP5562_OPMODE_ENG1_SHIFT 4 +#define LP5562_OPMODE_ENG2_SHIFT 2 +#define LP5562_OPMODE_ENG3_SHIFT 0 +#define LP5562_OPMODE_ALL_DISABLE 0x00 +#define LP5562_OPMODE_ALL_LOAD 0x15 +#define LP5562_OPMODE_ALL_RUN 0x2a + +/* + * LP5562_ENABLE_REG, default value + */ +#define LP5562_ENABLE_REG_DEFAULT (LP5562_ENABLE_CHIP_EN) + +/* + * LP5562_CONFIG_REG, default value + * PWM_HF=0(256Hz) + * PWRSAVE_EN=0 (Disable) + * CLKDET_EN/INT_CLK_EN=1 (Internal Clock) + */ +#define LP5562_CONFIG_REG_DEFAULT 0x03 + +/* + * LP5562_LED_MAP_REG, default value + * B:ENG1, G:ENG2, R:ENG3 + */ +#define LP5562_LED_MAP_REG_DEFAULT 0x39 + +/* LP5562 Current default value, applies to all four of them */ +#define LP5562_CRT_CTRL_DEFAULT 0xaf + +/* Goes into LP5562_RESET_REG to reset the chip. */ +#define LP5562_RESET_VALUE 0xff + +/* + * The controller has 96 bytes of SRAM for code/data, availabe as three 32 byte + * pages. + */ +#define LP5562_PROG_PAGE_SIZE 32 +#define LP5562_PROG_PAGES 3 +#define LP5562_MAX_PROG_SIZE LP5562_PROG_PAGE_SIZE + +/* + * Structure to cache data relevant to accessing one controller. I2c interface + * to use, device address on the i2c bus and a data buffer for write + * transactions. The most bytes sent at a time is the register address plus + * the program page size. + */ +typedef struct { + unsigned i2c_bus; + uint8_t dev_addr; + uint8_t data_buffer[LP5562_PROG_PAGE_SIZE + 1]; +} TiLp5562; + +static void led_lp5562_init(unsigned i2c_bus); + +/* Controller descriptors. */ +static TiLp5562 lp5562s[LED_LP5562_NUM_LED_CONTROLLERS]; + +/* + * i2c transfer function for the driver. To keep things simple, the function + * repeats the transfer, if the first attempt fails. This is OK with the + * controller and makes it easier to handle errors. + * + * Note that the reset register accesses are expected to fail on writes, but + * due to a bug in the ipq806x i2c controller, the error is reported on the + * following read attempt. + * + * To work around this the driver writes and then reads the reset register, + * the transfer function ignores errors when accessing the reset register. + */ +static int ledc_transfer(TiLp5562 *ledc, struct i2c_msg *segs, + int seg_count, int reset) +{ + int rv, max_attempts = 2; + + while (max_attempts--) { + rv = i2c_transfer(ledc->i2c_bus, segs, seg_count); + + /* Accessing reset regsiter is expected to fail. */ + if (!rv || reset) + break; + } + + if (rv) { + if (!reset) + printk(BIOS_WARNING, + "%s: dev %#x, reg %#x, %s transaction error.\n", + __func__, segs->slave, segs->buf[0], + seg_count == 1 ? "write" : "read"); + else + rv = 0; + } + + return rv; +} + +/* + * The controller is programmed to autoincrement on writes, so up to page size + * bytes can be transmitted in one write transaction. + */ +static int ledc_write(TiLp5562 *ledc, uint8_t start_addr, + const uint8_t *data, unsigned count) +{ + struct i2c_msg seg; + + if (count > (sizeof(ledc->data_buffer) - 1)) { + printk(BIOS_WARNING, "%s: transfer size too large (%d bytes)\n", + __func__, count); + return -1; + } + + memcpy(ledc->data_buffer + 1, data, count); + ledc->data_buffer[0] = start_addr; + + seg.flags = 0; + seg.slave = ledc->dev_addr; + seg.buf = ledc->data_buffer; + seg.len = count + 1; + + return ledc_transfer(ledc, &seg, 1, start_addr == LP5562_RESET_REG); +} + +/* To keep things simple, read is limited to one byte at a time. */ +static int ledc_read(TiLp5562 *ledc, uint8_t addr, uint8_t *data) +{ + struct i2c_msg seg[2]; + + seg[0].flags = 0; + seg[0].slave = ledc->dev_addr; + seg[0].buf = &addr; + seg[0].len = 1; + + seg[1].flags = I2C_M_RD; + seg[1].slave = ledc->dev_addr; + seg[1].buf = data; + seg[1].len = 1; + + return ledc_transfer(ledc, seg, ARRAY_SIZE(seg), + addr == LP5562_RESET_REG); +} + +/* + * Reset transaction is expected to result in a failing i2c command. But even + * before trying it, read the reset register, which is supposed to always + * return 0. If this fails - there is no lp5562 at this address. + * + * Return 0 on success, -1 on failure to detect controller. + */ +static int ledc_reset(TiLp5562 *ledc) +{ + uint8_t data; + + data = ~0; + ledc_read(ledc, LP5562_RESET_REG, &data); + if (data) { + printk(BIOS_WARNING, + "LED_LP5562: no controller found at address %#2.2x\n", + ledc->dev_addr); + return -1; + } + + data = LP5562_RESET_VALUE; + ledc_write(ledc, LP5562_RESET_REG, &data, 1); + + /* + * This read is not necessary for the chip reset, but is required to + * work around the i2c driver bug where the missing ACK on the last + * byte of the write transaction is ignored, but the next transaction + * fails. + */ + ledc_read(ledc, LP5562_RESET_REG, &data); + return 0; +} + +/* + * Write a program into the internal lp5562 memory. + */ +static void ledc_write_program(TiLp5562 *ledc, uint8_t load_addr, + const uint8_t *program, unsigned count) +{ + if (count > LP5562_MAX_PROG_SIZE) { + printk(BIOS_WARNING, + "%s: program of size %#x does not fit at addr %#x\n", + __func__, count, load_addr); + return; + } + ledc_write(ledc, load_addr, program, count); +} + +static void ledc_write_enable(TiLp5562 *ledc, uint8_t value) +{ + ledc_write(ledc, LP5562_ENABLE_REG, &value, 1); + udelay(500); /* Must wait longer than 488usec */ +} + +static void ledc_write_opmode(TiLp5562 *ledc, uint8_t value) +{ + ledc_write(ledc, LP5562_OPMODE_REG, &value, 1); + udelay(160); /* Must wait longer than 153usec */ +} + +/* Run an lp5562 program on a controller. */ +static void ledc_run_program(TiLp5562 *ledc, + const TiLp5562Program *program_desc) +{ + int i; + uint8_t data; + uint8_t enable_reg; + uint8_t load_addr; + + /* All engines on hold. */ + ledc_read(ledc, LP5562_ENABLE_REG, &enable_reg); + enable_reg &= ~LP5562_ENABLE_ALL_MASK; + enable_reg |= LP5562_ENABLE_CHIP_EN; + enable_reg |= LP5562_ENABLE_ALL_HOLD; + ledc_write_enable(ledc, enable_reg); + + /* All engines in LOAD mode. */ + ledc_write_opmode(ledc, LP5562_OPMODE_ALL_LOAD); + + /* Inject program code for each engine and start address */ + load_addr = LP5562_PROG_MEM_ENG1; + for (i = 0; i < LED_LP5562_NUM_OF_ENGINES; i++) { + ledc_write_program(ledc, load_addr, + program_desc->engine_program[i].program_text, + program_desc->engine_program[i].program_size); + data = program_desc->engine_program[i].engine_start_addr; + ledc_write(ledc, LP5562_ENGINE1_PC + i, &data, 1); + udelay(160); /* Must wait longer than 153usec */ + load_addr += LP5562_PROG_PAGE_SIZE; + } + + /* All engines on run. */ + ledc_write_opmode(ledc, LP5562_OPMODE_ALL_RUN); + + enable_reg &= ~LP5562_ENABLE_ALL_MASK; + enable_reg |= LP5562_ENABLE_ALL_RUN; + ledc_write_enable(ledc, enable_reg); +} + +/* + * Initialize a controller to a state were it is ready to accept programs, and + * try to confirm that we are in fact talking to a lp5562 + */ +static int ledc_init_validate(TiLp5562 *ledc) +{ + uint8_t data; + int i; + + if (ledc_reset(ledc)) + return -1; + + /* Enable the chip, keep engines in hold state. */ + ledc_write_enable(ledc, LP5562_ENABLE_REG_DEFAULT | LP5562_ENABLE_ALL_HOLD); + + data = LP5562_CONFIG_REG_DEFAULT; + ledc_write(ledc, LP5562_CONFIG_REG, &data, 1); + + data = LP5562_LED_MAP_REG_DEFAULT; + ledc_write(ledc, LP5562_LED_MAP_REG, &data, 1); + + /* + * All four current control registers are supposed to return the same + * value at reset. + */ + for (i = 0; i < 4; i++) { + uint8_t reg = (i < 3) ? LP5562_CURRENT_B + i : LP5562_CURRENT_W; + ledc_read(ledc, reg, &data); + if (data != LP5562_CRT_CTRL_DEFAULT) { + printk(BIOS_WARNING, + "%s: read %#2.2x from register %#x\n", __func__, + data, reg); + return -1; + } + } + + return 0; +} + +/* + * Find a program matching screen type, and run it on both controllers, if + * found. + */ +int led_lp5562_display_pattern(unsigned i2c_bus, enum display_pattern pattern) +{ + static int initted; + const Led5562StateProg *led_prog; + + if (!initted) { + led_lp5562_init(i2c_bus); + initted = 1; + } + + /* Last entry does not have any actual programs defined. */ + for (led_prog = led_lp5562_state_programs; led_prog->programs[0]; led_prog++) + if (led_prog->led_pattern == pattern) { + int j; + + /* + * First stop all running programs to avoid + * inerference between the controllers. + */ + for (j = 0; j < LED_LP5562_NUM_LED_CONTROLLERS; j++) { + if (!lp5562s[j].dev_addr) + continue; + ledc_write_opmode + (lp5562s + j, + LP5562_OPMODE_ALL_DISABLE); + } + + for (j = 0; j < LED_LP5562_NUM_LED_CONTROLLERS; j++) { + if (!lp5562s[j].dev_addr) + continue; + ledc_run_program(lp5562s + j, + led_prog->programs[j]); + } + return 0; + } + + printk(BIOS_WARNING, "%s: did not find program for pattern %d\n", + __func__, pattern); + + return -1; +} + +#define LP5562_I2C_BASE_ADDR 0x30 + +static void led_lp5562_init(unsigned i2c_bus) +{ + TiLp5562 *ledc; + int i, count = 0; + + for (i = 0, ledc = lp5562s; + i < LED_LP5562_NUM_LED_CONTROLLERS; + i++, ledc++) { + + ledc->i2c_bus = i2c_bus; + ledc->dev_addr = LP5562_I2C_BASE_ADDR + i; + + if (!ledc_init_validate(ledc)) + count++; + else + ledc->dev_addr = 0; /* Mark disabled. */ + } + + printk(BIOS_INFO, "LED_LP5562: initialized %d out of %d\n", count, i); + if (count != i) { + if (count) + printk(BIOS_WARNING, + "LED_LP5562: will keep going anyway\n"); + else + printk(BIOS_WARNING, + "LED_LP5562: LED ring not present\n"); + } +} diff --git a/src/drivers/i2c/lp5562/led_lp5562.h b/src/drivers/i2c/lp5562/led_lp5562.h new file mode 100644 index 0000000..3c202eb --- /dev/null +++ b/src/drivers/i2c/lp5562/led_lp5562.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2019 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SRC_DRIVERS_VIDEO_LED_LP5562__H__ +#define __SRC_DRIVERS_VIDEO_LED_LP5562__H__ + +/* + * Different types of display patterns to be shown by the LED while + * contrlled by coreboot. + */ +enum display_pattern { + LED_ALL_OFF, /* Turn the LEDs off. */ + LED_RECOVERY_PUSHED, /* Recovery button push detected on start up. */ + LED_WIPEOUT_REQUEST, /* Held long enough for wipout request. */ + LED_RECOVERY_REQUEST, /* Held long enough for recovery request. */ + LED_NORMAL_BOOT /* No buttons pressed, normal boot sequence. */ +}; +/* + * led_lp5562_display_pattern + * + * Display pattern on the ring LEDs. + */ +int led_lp5562_display_pattern(unsigned i2c_bus, enum display_pattern pattern); + +#endif diff --git a/src/drivers/i2c/lp5562/led_lp5562_programs.c b/src/drivers/i2c/lp5562/led_lp5562_programs.c new file mode 100644 index 0000000..f322f6a --- /dev/null +++ b/src/drivers/i2c/lp5562/led_lp5562_programs.c @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2019 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is a driver for the TI LP5562 (http://www.ti.com/product/lp5562), + * driving a tri-color LED. + * + * The only connection between the LED and the main board is an i2c bus. + * + * This driver imitates a depthcharge display device. On initialization the + * driver sets up the controllers to prepare them to accept programs to run. + * + * When a certain vboot state needs to be indicated, the program for that + * state is loaded into the controllers, resulting in the state appropriate + * LED behavior. + */ + +#include "drivers/i2c/lp5562/led_lp5562_programs.h" + +/**************************************************************** + * LED ring program definitions for different patterns. + * + * Comments below are real lp5562 source code, they are compiled using + * lasm.exe, the TI tool available from their Web site (search for lp5562) + * and running only on Windows :P. + * + * Different hex dumps are results of tweaking the source code parameters to + * achieve desirable LED ring behavior. It is possible to use just one code + * dump and replace certain values in the body to achieve different behaviour + * with the same basic dump, but keeping track of location to tweak with every + * code change would be quite tedious. + */ + +/* + * Solid LED display, the arguments of the set_pwm commands set intensity and + * color of the display: + + 1 00 .ENGINE1(R) + 2 00 4080 set_pwm 128 + 3 01 C000 end + 4 + 5 10 .ENGINE2(G) + 6 10 4080 set_pwm 128 + 7 11 C000 end + 8 + 9 20 .ENGINE3(B) + 10 20 4080 set_pwm 128 + 11 21 C000 end +*/ + +/* RGB set to 000000, resulting in all LEDs off. */ +static const uint8_t solid_00_text[] = { + 0x40, 0x00, 0xc0, 0x00 +}; + +/* Rgb set to 128, resulting in a brightish white color. */ +static const uint8_t solid_80_text[] = { + 0x40, 0x80, 0xc0, 0x00 +}; + +static const TiLp5562Program solid_000000_program = { + { + { /* Engine1:Blue */ + solid_00_text, + sizeof(solid_00_text), + 0, + }, + { /* Engine2:Green */ + solid_00_text, + sizeof(solid_00_text), + 0, + }, + { /* Engine3:Red */ + solid_00_text, + sizeof(solid_00_text), + 0, + }, + } +}; + +static const TiLp5562Program solid_808080_program = { + { + { /* Engine1:Blue */ + solid_80_text, + sizeof(solid_80_text), + 0, + }, + { /* Engine2:Green */ + solid_80_text, + sizeof(solid_80_text), + 0, + }, + { /* Engine3:Red */ + solid_80_text, + sizeof(solid_80_text), + 0, + }, + } +}; + +/* + 1 00 .ENGINE1(B) + 2 00 E200 trigger w3 + 3 01 409B set_pwm 155 + 4 02 E200 trigger w3 + 5 03 4000 set_pwm 0 + 6 04 0000 gotostart + 7 + 8 10 .ENGINE2(G) + 9 10 E200 trigger w3 + 10 11 4032 set_pwm 50 + 11 12 E200 trigger w3 + 12 13 4000 set_pwm 0 + 13 14 0000 gotostart + 14 + 15 20 .ENGINE3(R) + 16 20 E006 trigger s21 + 17 21 4001 set_pwm 1 + 18 22 5300 wait 300 + 19 23 E006 trigger s21 + 20 24 4000 set_pwm 0 + 21 25 5300 wait 300 + 22 26 0000 gotostart +*/ + +static const uint8_t blink_wipeout1_b_text[] = { + 0xe2, 0x00, 0x40, 155, 0xe2, 0x00, 0x40, 0, + 0x00, 0x00, +}; + +static const uint8_t blink_wipeout1_g_text[] = { + 0xe2, 0x00, 0x40, 50, 0xe2, 0x00, 0x40, 0, + 0x00, 0x00, +}; + +static const uint8_t blink_wipeout1_r_text[] = { + 0xe0, 0x06, 0x40, 1, 0x53, 0x00, 0xe0, 0x06, + 0x40, 0, 0x53, 0x00, 0x00, 0x00 +}; + +static const TiLp5562Program blink_wipeout1_program = { + { + { + blink_wipeout1_b_text, + sizeof(blink_wipeout1_b_text), + 0, + }, + { + blink_wipeout1_g_text, + sizeof(blink_wipeout1_g_text), + 0, + }, + { + blink_wipeout1_r_text, + sizeof(blink_wipeout1_r_text), + 0, + }, + } +}; + +static const uint8_t blink_recovery1_b_text[] = { + 0xe2, 0x00, 0x40, 10, 0xe2, 0x00, 0x40, 0, + 0x00, 0x00, +}; + +static const uint8_t blink_recovery1_g_text[] = { + 0xe2, 0x00, 0x40, 100, 0xe2, 0x00, 0x40, 0, + 0x00, 0x00, +}; + +static const uint8_t blink_recovery1_r_text[] = { + 0xe0, 0x06, 0x40, 255, 0x53, 0x00, 0xe0, 0x06, + 0x40, 0, 0x53, 0x00, 0x00, 0x00 +}; + +static const TiLp5562Program blink_recovery1_program = { + { + { + blink_recovery1_b_text, + sizeof(blink_wipeout1_b_text), + 0, + }, + { + blink_recovery1_g_text, + sizeof(blink_wipeout1_g_text), + 0, + }, + { + blink_recovery1_r_text, + sizeof(blink_wipeout1_r_text), + 0, + }, + } +}; + +/* + * fade_in1.src + * + 1 00 .ENGINE1(B) + 2 00 4000 set_pwm 0 + 3 01 E200 trigger w3 + 4 02 1B4C ramp 1000, 77 # ramp up to 155 for 2 seconds + 5 03 1A4D ramp 1000, 78 + 6 04 C000 end + 7 + 8 10 .ENGINE2(G) + 9 10 4000 set_pwm 0 + 10 11 E200 trigger w3 + 11 12 4318 ramp 1000, 25 # ramp up to 50 for 2 seconds + 12 13 4318 ramp 1000, 25 + 13 14 C000 end + 14 + 15 20 .ENGINE3(R) + 16 20 E006 trigger s21 + 17 21 4001 set_pwm 1 + 18 22 E006 trigger s21 + 19 23 C000 end +*/ + +static const uint8_t fade_in1_b_text[] = { + 0x40, 0, 0xe2, 0x00, 0x1b, 0x4c, 0x1a, 0x4d, + 0xc0, 0x00 +}; +static const uint8_t fade_in1_g_text[] = { + 0x40, 0, 0xe2, 0x00, 0x43, 0x18, 0x43, 0x18, + 0xc0, 0x00 +}; +static const uint8_t fade_in1_r_text[] = { + 0xe0, 0x06, 0x40, 1, 0xe0, 0x06, 0x00 +}; + +static const TiLp5562Program fade_in1_program = { + { + { + fade_in1_b_text, + sizeof(fade_in1_b_text), + 0, + }, + { + fade_in1_g_text, + sizeof(fade_in1_g_text), + 0, + }, + { + fade_in1_r_text, + sizeof(fade_in1_r_text), + 0, + }, + } +}; + +const Led5562StateProg led_lp5562_state_programs[] = { + /* + * for test purposes the blank screen program is set to blinking, will + * be changed soon. + */ + {LED_ALL_OFF, {&solid_000000_program} }, + {LED_RECOVERY_PUSHED, {&solid_808080_program} }, + {LED_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {LED_RECOVERY_REQUEST, {&blink_recovery1_program} }, + {LED_NORMAL_BOOT, {&fade_in1_program} }, + {}, /* Empty record to mark the end of the table. */ +}; diff --git a/src/drivers/i2c/lp5562/led_lp5562_programs.h b/src/drivers/i2c/lp5562/led_lp5562_programs.h new file mode 100644 index 0000000..e5373c0 --- /dev/null +++ b/src/drivers/i2c/lp5562/led_lp5562_programs.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2019 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is a driver for the TI LP5562 (http://www.ti.com/product/lp5562), + * driving a tri-color LED. + * + * The only connection between the LED and the main board is an i2c bus. + * + * This driver imitates a depthcharge display device. On initialization the + * driver sets up the controllers to prepare them to accept programs to run. + * + * When a certain vboot state needs to be indicated, the program for that + * state is loaded into the controllers, resulting in the state appropriate + * LED behavior. + */ + +#ifndef __THIRD_PARTY_COREBOOT_SRC_DRIVERS_I2C_LED_LP5562_LED_LP5562_PROGRAMS_H__ +#define __THIRD_PARTY_COREBOOT_SRC_DRIVERS_I2C_LED_LP5562_LED_LP5562_PROGRAMS_H__ + +#include <stdint.h> +#include "drivers/i2c/lp5562/led_lp5562.h" + +/* There are threee independent engines/cores in the controller. */ +#define LED_LP5562_NUM_OF_ENGINES 3 + +/* Number of LP5562 controllers on this implementation */ +#define LED_LP5562_NUM_LED_CONTROLLERS 1 + +/* + * Structure to describe an lp5562 program: pointer to the text of the + * program, its size for each engines, and start address relative to + * each engine program memory. Program memory address for each engine is + * fixed on LP5562. + */ +typedef struct { + struct { + const uint8_t *program_text; + uint8_t program_size; + uint8_t engine_start_addr; + } engine_program[LED_LP5562_NUM_OF_ENGINES]; +} TiLp5562Program; + +/* A structure to bind controller programs to a vboot state. */ +typedef struct { + enum display_pattern led_pattern; + const TiLp5562Program *programs[LED_LP5562_NUM_LED_CONTROLLERS]; +} Led5562StateProg; + +extern const Led5562StateProg led_lp5562_state_programs[]; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0206dc6bfd367a258af88ab61e0928e32e9aa60f Gerrit-Change-Number: 32692 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-Reviewer: Yuji Sasaki <sasakiy(a)chromium.org> Gerrit-MessageType: newchange

6 14

Change in ...coreboot[master]: qcs405: Add support for specifying mbn_version
by Nitheesh Sekar (Code Review) 11 Mar '20

11 Mar '20

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33425 Change subject: qcs405: Add support for specifying mbn_version ...................................................................... qcs405: Add support for specifying mbn_version Change-Id: Ic6e269e0f290692871875000586410217c25fc08 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M util/qualcomm/createxbl.py M util/qualcomm/mbn_tools.py 3 files changed, 62 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33425/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index cf8268b..4faaffc 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -126,18 +126,12 @@ qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf - python util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + python util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.elf \ -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ -a 64 -d 32 -c 32 -ifeq ($(CONFIG_QC_FLASH_SIMULATE_SDCARD),y) - @printf "\nqgpt.py 512 sector size\n" - python util/qualcomm/qgpt.py -s 512 $(objcbfs)/merged_bb_qcsec.mbn \ - $(objcbfs)/bootblock.bin -else @printf "\nqgpt.py 4K sector size\n" python util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ $(objcbfs)/bootblock.bin -endif else $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 4a21854..ad5934d 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -44,6 +44,7 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ +# 05/21/19 rissha Added --mbn_version to add MBN header accordingly # 03/26/18 tv Added -e to enable extended MBNV5 support # 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature @@ -119,6 +120,10 @@ help="Removes ZI segments that have addresses greater" + \ " than 32 bits when converting from a 64 to 32 bit ELF") + parser.add_option("--mbn_version", + action="store", type="int", dest="mbn_version", + help="Add mbn header in elf image. '5' or '6'") + (options, args) = parser.parse_args() if not options.elf_inp_file1: @@ -206,11 +211,16 @@ else: zi_oob_enabled = True - if options.elf_inp_xbl_sec: + header_version = None + + if options.elf_inp_xbl_sec or options.mbn_version == 5: is_ext_mbn_v5 = True + header_version = 5 else: is_ext_mbn_v5 = False + if options.mbn_version: + header_version = options.mbn_version mbn_type = 'elf' header_format = 'reg' @@ -259,7 +269,7 @@ source_elf, target_hash, elf_out_file_name = target_phdr_elf, - secure_type = image_header_secflag) + secure_type = image_header_secflag, header_version = header_version ) if rv: raise RuntimeError, "Failed to run pboot_gen_elf" @@ -270,7 +280,8 @@ target_hash_hd, image_header_secflag, is_ext_mbn_v5, - elf_file_name = source_elf) + elf_file_name = source_elf, + header_version = header_version) if rv: raise RuntimeError, "Failed to create image header for hash segment" diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 12dc210..c702f96 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384 # 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and @@ -69,6 +70,7 @@ SHA256_SIGNATURE_SIZE = 256 # Support SHA256 MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type) +MI_BOOT_IMG_HDR_SIZE_v6 = 48 # sizeof(mi_boot_image_header_type) for v6 header MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements @@ -551,7 +553,7 @@ def getLength(self): return BOOT_HEADER_LENGTH - def writePackedData(self, target, write_full_hdr): + def writePackedData(self, target, write_full_hdr, header_version = None): values = [self.image_id, self.flash_parti_ver, self.image_src, @@ -573,6 +575,10 @@ self.reserved_2, self.reserved_3 ] + if header_version == 6: + values.insert(10, self.metadata_size_qti) + values.insert(11, self.metadata_size) + if self.image_dest_ptr >= 0x100000000: values[3] = 0xFFFFFFFF @@ -584,8 +590,12 @@ # Write 10 entries(40B) or 20 entries(80B) of boot header if write_full_hdr is False: - s = struct.Struct('I'* 10) - values = values[:10] + if header_version == 6: + s = struct.Struct('I'* 12) + values = values[:12] + else: + s = struct.Struct('I'* 10) + values = values[:10] else: s = struct.Struct('I' * self.getLength()) @@ -912,7 +922,8 @@ write_full_hdr = False, in_code_size = None, cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, - num_of_pages = None): + num_of_pages = None, + header_version = None): # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): @@ -947,7 +958,7 @@ # For ELF or hashed images, image destination will be determined from an ELF input file if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf': - image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE + image_dest = get_hash_address(elf_file_name) + (MI_BOOT_IMG_HDR_SIZE_v6 if header_version == 6 else MI_BOOT_IMG_HDR_SIZE) elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin': image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST'] image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE'] @@ -993,17 +1004,24 @@ boot_header.cert_chain_size = cert_chain_size if is_ext_mbn_v5 == True: - # If platform image integrity check is enabled - boot_header.flash_parti_ver = 5 # version - boot_header.image_src = 0 # sig_size_qc - boot_header.image_dest_ptr = 0 # cert_chain_size_qc + # If platform image integrity check is enabled + boot_header.flash_parti_ver = 5 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + + if header_version == 6: + boot_header.flash_parti_ver = 6 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr =0 # cert_chain_size_qc + boot_header.metadata_size_qti = 0 # qti_metadata size + boot_header.metadata_size = 0 # oem_metadata size # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: boot_header = image_preamble(gen_dict, preamble_file_name, boot_header, num_of_pages) # Package up the header and write to output file - boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr) + boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr, header_version = header_version) else: raise RuntimeError, "Header format not supported: " + str(header_format) @@ -1021,13 +1039,23 @@ last_phys_addr = None, append_xml_hdr = False, is_sha256_algo = True, - cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE): + cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, + header_version = None): + is_sha384_algo = False + if header_version == 6: + is_sha384_algo = True global MI_PROG_BOOT_DIGEST_SIZE + image_header_size = MI_BOOT_IMG_HDR_SIZE + if (is_sha256_algo is True): MI_PROG_BOOT_DIGEST_SIZE = 32 else: MI_PROG_BOOT_DIGEST_SIZE = 20 + if is_sha384_algo: + MI_PROG_BOOT_DIGEST_SIZE = 48 + image_header_size = MI_BOOT_IMG_HDR_SIZE_v6 + # Open Files elf_in_fp = OPEN(elf_in_file_name, "rb") hash_out_fp = OPEN(hash_out_file_name, "wb+") @@ -1110,7 +1138,7 @@ fbuf = elf_in_fp.read(hash_size) if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: - hash = generate_hash(fbuf, is_sha256_algo) + hash = generate_hash(fbuf, is_sha256_algo, is_sha384_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1129,7 +1157,7 @@ file_buff = elf_in_fp.read(data_len) if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): - hash = generate_hash(file_buff, is_sha256_algo) + hash = generate_hash(file_buff, is_sha256_algo, is_sha384_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1151,7 +1179,7 @@ # Initialize the hash table program header [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \ - initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64) + initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64) # Check if hash segment max size parameter was passed if (hash_seg_max_size is not None): @@ -1252,7 +1280,7 @@ # Read the program header and compute hash proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size) - hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo) + hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo, is_sha384_algo) # Write hash to file as first hash table entry hash_out_fp.seek(0) @@ -2101,9 +2129,11 @@ #---------------------------------------------------------------------------- # sha1/sha256 hash routine wrapper #---------------------------------------------------------------------------- -def generate_hash(in_buf, is_sha256_algo): +def generate_hash(in_buf, is_sha256_algo, is_sha384_algo = False): # Initialize a SHA1 object from the Python hash library - if (is_sha256_algo is True): + if is_sha384_algo: + m = hashlib.sha384() + elif (is_sha256_algo is True): m = hashlib.sha256() else: m = hashlib.sha1() -- To view, visit https://review.coreboot.org/c/coreboot/+/33425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6e269e0f290692871875000586410217c25fc08 Gerrit-Change-Number: 33425 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: google/mistrtal: Add board ID API.
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31426 Change subject: google/mistrtal: Add board ID API. ...................................................................... google/mistrtal: Add board ID API. BUG=None TEST=Verified GPIO assignment and board ID values. BRANCH=None Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/boardid.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31426/1 diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index e9013af..ae418f2 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += chromeos.c bootblock-y += bootblock.c +verstage-y += boardid.c verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += verstage.c @@ -10,7 +11,9 @@ romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c new file mode 100644 index 0000000..f20960c --- /dev/null +++ b/src/mainboard/google/mistral/boardid.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> + +/* + * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106 + * and 107. + */ + +static uint32_t board_id_val = UNDEFINED_STRAPPING_ID; + +static uint32_t get_board_id(void) +{ + uint32_t bid; + const gpio_t pins[] = {[2] = GPIO(107), [1] = GPIO(106), [0] = GPIO(105)}; + + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint32_t board_id(void) +{ + if (board_id_val == UNDEFINED_STRAPPING_ID) + board_id_val = get_board_id(); + + return board_id_val; +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/31426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Gerrit-Change-Number: 31426 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: google/mistrtal: Setup required Chromeos GPIOs.
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31459 Change subject: google/mistrtal: Setup required Chromeos GPIOs. ...................................................................... google/mistrtal: Setup required Chromeos GPIOs. Setup Flash write protect, recovery and h1 interrupt gpios to requires state at boot. BUG=None TEST=Verified GPIO state and its functionalities. BRANCH=None Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/bootblock.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31459/1 diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 6718d52..c72856d 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -15,8 +15,9 @@ #include <bootblock_common.h> #include <timestamp.h> +#include "board.h" void bootblock_mainboard_init(void) { - + setup_chromeos_gpios(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Gerrit-Change-Number: 31459 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31826 Change subject: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button ...................................................................... TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31826/1 diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h index 2e23ce3..51e4bf2 100644 --- a/src/mainboard/google/mistral/board.h +++ b/src/mainboard/google/mistral/board.h @@ -19,7 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> - +#define GPIO_DEV_STATE GPIO(45) #define GPIO_H1_AP_INT GPIO(53) #define GPIO_WP_STATE GPIO(54) #define GPIO_REC_STATE GPIO(77) diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 838691b..9b69a4f 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -24,11 +24,14 @@ { gpio_input(GPIO_WP_STATE); gpio_input(GPIO_REC_STATE); + gpio_input(GPIO_DEV_STATE); } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { + {GPIO_DEV_STATE.addr, ACTIVE_HIGH, + gpio_get(GPIO_DEV_STATE), "developer"}, {GPIO_REC_STATE.addr, ACTIVE_LOW, gpio_get(GPIO_REC_STATE), "recovery"}, {GPIO_WP_STATE.addr, ACTIVE_LOW, -- To view, visit https://review.coreboot.org/c/coreboot/+/31826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Gerrit-Change-Number: 31826 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: mb/google/mistral: Ignore REC switch if TPM isn't ready
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Hello SANTHOSH JANARDHANA HASSAN, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32272 to review the following change. Change subject: mb/google/mistral: Ignore REC switch if TPM isn't ready ...................................................................... mb/google/mistral: Ignore REC switch if TPM isn't ready The recovery button's state is cached in the TPM, but on first boot Cr50 isn't ready yet for this task, which leads to a reboot further down the road (to get TPM up). To not confuse matters further, only act on the recovery button if the TPM is in fact able to cache the state. BUG=b:129878075 BRANCH=none TEST=recovery button is only read on second boot Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32272/1 diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 9b69a4f..e0306b16 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -72,6 +72,9 @@ gpio_t rec_sw; static enum switch_state saved_state = not_probed; + if (is_tpm_detected() == 0) + return saved_state; + if (saved_state != not_probed) return saved_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/32272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Gerrit-Change-Number: 32272 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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