coreboot-gerrit June 2019

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Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review) 04 Jul '20

04 Jul '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504 Change subject: util/inteltool: Refactor code of GPIO groups ...................................................................... util/inteltool: Refactor code of GPIO groups Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A util/inteltool/gpio.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_sunrise.h 4 files changed, 865 insertions(+), 816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1 diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h new file mode 100644 index 0000000..64f62f8 --- /dev/null +++ b/util/inteltool/gpio.h @@ -0,0 +1,29 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +struct gpio_group { + const char *display; + size_t pad_count; + size_t func_count; + const char *const *pad_names; /* indexed by 'pad * func_count + func' */ +}; + +struct gpio_community { + const char *name; + uint8_t pcr_port_id; + size_t group_count; + const struct gpio_group *const *groups; +}; diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h new file mode 100644 index 0000000..e745b44 --- /dev/null +++ b/util/inteltool/gpio_denverton.h @@ -0,0 +1,237 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const denverton_group_north_all_names[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +static const struct gpio_group denverton_group_north_all = { + .display = "------- GPIO Group North All -------", + .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, + .func_count = 1, + .pad_names = denverton_group_north_all_names, +}; + +static const struct gpio_group *const denverton_community_north_groups[] = { + &denverton_group_north_all, +}; + +static const struct gpio_community denverton_community_north = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xc2, + .group_count = ARRAY_SIZE(denverton_community_north_groups), + .groups = denverton_community_north_groups, +}; + +static const char *const denverton_group_south_dfx_names[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", +}; + +static const struct gpio_group denverton_group_south_dfx = { + .display = "------- GPIO Group South DFX -------", + .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_dfx_names, +}; + +static const char *const denverton_group_south_group0_names[] = { + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", +}; + +static const struct gpio_group denverton_group_south_group0 = { + .display = "------- GPIO Group South Group0 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group0_names, +}; + +static const char *const denverton_group_south_group1_names[] = { + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + +static const struct gpio_group denverton_group_south_group1 = { + .display = "------- GPIO Group South Group1 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group1_names, +}; + +static const struct gpio_group *const denverton_community_south_groups[] = { + &denverton_group_south_dfx, + &denverton_group_south_group0, + &denverton_group_south_group1, +}; + +static const struct gpio_community denverton_community_south = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(denverton_community_south_groups), + .groups = denverton_community_south_groups, +}; + +static const struct gpio_community *const denverton_communities[] = { + &denverton_community_north, &denverton_community_south, +}; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 53a8eb9..c7ab186 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,826 +22,13 @@ #include <inttypes.h> #include "inteltool.h" #include "pcr.h" +#include "gpio.h" +#include "gpio_denverton.h" +#include "gpio_sunrise.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -struct gpio_group { - const char *display; - size_t pad_count; - size_t func_count; - const char *const *pad_names; /* indexed by 'pad * func_count + func' */ -}; - -struct gpio_community { - const char *name; - uint8_t pcr_port_id; - size_t group_count; - const struct gpio_group *const *groups; -}; - -static const char *const sunrise_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "ISH_GP7", "n/a", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_a_names, -}; - -static const char *const sunrise_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "n/a", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "n/a", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_a = { - .display = "------- GPIO group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_a_names, -}; - -static const char *const sunrise_group_b_names[] = { - "GPP_B0", "n/a", "n/a", "n/a", - "GPP_B1", "n/a", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPIO_CS#", "n/a", "n/a", - "GPP_B16", "GSPIO_CLK", "n/a", "n/a", - "GPP_B17", "GSPIO_MISO", "n/a", "n/a", - "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_b_names, -}; - -static const char *const sunrise_lp_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPI0_CS#", "n/a", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_b_names, -}; - -static const struct gpio_group *const sunrise_community_ab_groups[] = { - &sunrise_group_a, &sunrise_group_b, -}; - -static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { - &sunrise_lp_group_a, &sunrise_lp_group_b, -}; - -static const struct gpio_community sunrise_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_community_ab_groups), - .groups = sunrise_community_ab_groups, -}; - -static const struct gpio_community sunrise_lp_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), - .groups = sunrise_lp_community_ab_groups, -}; - -static const char *const sunrise_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "n/a", "n/a", - "GPP_C4", "SML0DATA", "n/a", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", "n/a", - "GPP_C6", "SML1CLK", "n/a", "n/a", - "GPP_C7", "SML1DATA", "n/a", "n/a", - "GPP_C8", "UART0_RXD", "n/a", "n/a", - "GPP_C9", "UART0_TXD", "n/a", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", - "GPP_C16", "I2C0_SDA", "n/a", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", "n/a", - "GPP_C20", "UART2_RXD", "n/a", "n/a", - "GPP_C21", "UART2_TXD", "n/a", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_c_names, -}; - -static const char *const sunrise_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "n/a", - "GPP_D1", "n/a", "n/a", "n/a", - "GPP_D2", "n/a", "n/a", "n/a", - "GPP_D3", "n/a", "n/a", "n/a", - "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", - "GPP_D5", "I2S_SFRM", "n/a", "n/a", - "GPP_D6", "I2S_TXD", "n/a", "n/a", - "GPP_D7", "I2S_RXD", "n/a", "n/a", - "GPP_D8", "I2S_SCLK", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "n/a", - "GPP_D22", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", -}; - -static const struct gpio_group sunrise_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_d_names, -}; - -static const char *const sunrise_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "n/a", - "GPP_D1", "SPI1_CLK", "n/a", "n/a", - "GPP_D2", "SPI1_MISO", "n/a", "n/a", - "GPP_D3", "SPI1_MOSI", "n/a", "n/a", - "GPP_D4", "FLASHTRIG", "n/a", "n/a", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_d_names, -}; - -static const char *const sunrise_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATA_LED#", "n/a", "n/a", - "GPP_E9", "USB_OC0#", "n/a", "n/a", - "GPP_E10", "USB_OC1#", "n/a", "n/a", - "GPP_E11", "USB_OC2#", "n/a", "n/a", - "GPP_E12", "USB_OC3#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const sunrise_lp_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATALED#", "n/a", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", "n/a", - "GPP_E13", "DDPB_HPD0", "n/a", "n/a", - "GPP_E14", "DDPC_HPD1", "n/a", "n/a", - "GPP_E15", "DDPD_HPD2", "n/a", "n/a", - "GPP_E16", "DDPE_HPD3", "n/a", "n/a", - "GPP_E17", "EDP_HPD", "n/a", "n/a", - "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_E22", "n/a", "n/a", "n/a", - "GPP_E23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_e_names, -}; - -static const char *const sunrise_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", - "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", - "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", - "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", - "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "n/a", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_f_names, -}; - -static const char *const sunrise_lp_group_f_names[] = { - "GPP_F0", "I2S2_SCLK", "n/a", "n/a", - "GPP_F1", "I2S2_SFRM", "n/a", "n/a", - "GPP_F2", "I2S2_TXD", "n/a", "n/a", - "GPP_F3", "I2S2_RXD", "n/a", "n/a", - "GPP_F4", "I2C2_SDA", "n/a", "n/a", - "GPP_F5", "I2C2_SCL", "n/a", "n/a", - "GPP_F6", "I2C3_SDA", "n/a", "n/a", - "GPP_F7", "I2C3_SCL", "n/a", "n/a", - "GPP_F8", "I2C4_SDA", "n/a", "n/a", - "GPP_F9", "I2C4_SCL", "n/a", "n/a", - "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", - "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", - "GPP_F12", "EMMC_CMD", "n/a", "n/a", - "GPP_F13", "EMMC_DATA0", "n/a", "n/a", - "GPP_F14", "EMMC_DATA1", "n/a", "n/a", - "GPP_F15", "EMMC_DATA2", "n/a", "n/a", - "GPP_F16", "EMMC_DATA3", "n/a", "n/a", - "GPP_F17", "EMMC_DATA4", "n/a", "n/a", - "GPP_F18", "EMMC_DATA5", "n/a", "n/a", - "GPP_F19", "EMMC_DATA6", "n/a", "n/a", - "GPP_F20", "EMMC_DATA7", "n/a", "n/a", - "GPP_F21", "EMMC_RCLK", "n/a", "n/a", - "GPP_F22", "EMMC_CLK", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_f_names, -}; - -static const char *const sunrise_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "n/a", "n/a", - "GPP_G1", "FAN_TACH_1", "n/a", "n/a", - "GPP_G2", "FAN_TACH_2", "n/a", "n/a", - "GPP_G3", "FAN_TACH_3", "n/a", "n/a", - "GPP_G4", "FAN_TACH_4", "n/a", "n/a", - "GPP_G5", "FAN_TACH_5", "n/a", "n/a", - "GPP_G6", "FAN_TACH_6", "n/a", "n/a", - "GPP_G7", "FAN_TACH_7", "n/a", "n/a", - "GPP_G8", "FAN_PWM_0", "n/a", "n/a", - "GPP_G9", "FAN_PWM_1", "n/a", "n/a", - "GPP_G10", "FAN_PWM_2", "n/a", "n/a", - "GPP_G11", "FAN_PWM_3", "n/a", "n/a", - "GPP_G12", "GSXDOUT", "n/a", "n/a", - "GPP_G13", "GSXSLOAD", "n/a", "n/a", - "GPP_G14", "GSXDIN", "n/a", "n/a", - "GPP_G15", "GSXRESET#", "n/a", "n/a", - "GPP_G16", "GSXCLK", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "n/a", "n/a", - "GPP_G21", "n/a", "n/a", "n/a", - "GPP_G22", "n/a", "n/a", "n/a", - "GPP_G23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_g_names, -}; - -static const char *const sunrise_lp_group_g_names[] = { - "GPP_G0", "SD_CMD", "n/a", "n/a", - "GPP_G1", "SD_DATA0", "n/a", "n/a", - "GPP_G2", "SD_DATA1", "n/a", "n/a", - "GPP_G3", "SD_DATA2", "n/a", "n/a", - "GPP_G4", "SD_DATA3", "n/a", "n/a", - "GPP_G5", "SD_CD#", "n/a", "n/a", - "GPP_G6", "SD_CLK", "n/a", "n/a", - "GPP_G7", "SD_WP", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_g_names, -}; - -static const char *const sunrise_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "n/a", "n/a", - "GPP_H11", "SML2DATA", "n/a", "n/a", - "GPP_H12", "SML2ALERT#", "n/a", "n/a", - "GPP_H13", "SML3CLK", "n/a", "n/a", - "GPP_H14", "SML3DATA", "n/a", "n/a", - "GPP_H15", "SML3ALERT#", "n/a", "n/a", - "GPP_H16", "SML4CLK", "n/a", "n/a", - "GPP_H17", "SML4DATA", "n/a", "n/a", - "GPP_H18", "SML4ALERT#", "n/a", "n/a", - "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_H23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_h_names, -}; - -static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { - &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, - &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, -}; - -static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { - &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, -}; - -static const struct gpio_community sunrise_community_cdefgh = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), - .groups = sunrise_community_cdefgh_groups, -}; - -static const struct gpio_community sunrise_lp_community_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), - .groups = sunrise_lp_community_cde_groups, -}; - -static const char *const sunrise_group_gpd_names[] = { - "GPD0", "BATLOW#", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "LAN_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "SLP_WLAN#", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "LANPHYPC", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_gpd_names, -}; - -static const struct gpio_group *const sunrise_community_gpd_groups[] = { - &sunrise_group_gpd, -}; - -static const struct gpio_community sunrise_community_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), - .groups = sunrise_community_gpd_groups, -}; - -static const char *const sunrise_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "n/a", "n/a", - "GPP_I1", "DDPC_HPD1", "n/a", "n/a", - "GPP_I2", "DDPD_HPD2", "n/a", "n/a", - "GPP_I3", "DDPE_HPD3", "n/a", "n/a", - "GPP_I4", "EDP_HPD", "n/a", "n/a", - "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_i_names, -}; - -static const struct gpio_group *const sunrise_community_i_groups[] = { - &sunrise_group_i, -}; - -static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { - &sunrise_lp_group_f, &sunrise_lp_group_g, -}; - -static const struct gpio_community sunrise_community_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_community_i_groups), - .groups = sunrise_community_i_groups, -}; - -static const struct gpio_community sunrise_lp_community_fg = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), - .groups = sunrise_lp_community_fg_groups, -}; - -static const struct gpio_community *const sunrise_communities[] = { - &sunrise_community_ab, &sunrise_community_cdefgh, - &sunrise_community_gpd, &sunrise_community_i, -}; - -static const struct gpio_community *const sunrise_lp_communities[] = { - &sunrise_lp_community_ab, &sunrise_lp_community_cde, - &sunrise_community_gpd, &sunrise_lp_community_fg, -}; - -static const char *const denverton_group_north_all_names[] = { - "NORTH_ALL_GBE0_SDP0", - "NORTH_ALL_GBE1_SDP0", - "NORTH_ALL_GBE0_SDP1", - "NORTH_ALL_GBE1_SDP1", - "NORTH_ALL_GBE0_SDP2", - "NORTH_ALL_GBE1_SDP2", - "NORTH_ALL_GBE0_SDP3", - "NORTH_ALL_GBE1_SDP3", - "NORTH_ALL_GBE2_LED0", - "NORTH_ALL_GBE2_LED1", - "NORTH_ALL_GBE0_I2C_CLK", - "NORTH_ALL_GBE0_I2C_DATA", - "NORTH_ALL_GBE1_I2C_CLK", - "NORTH_ALL_GBE1_I2C_DATA", - "NORTH_ALL_NCSI_RXD0", - "NORTH_ALL_NCSI_CLK_IN", - "NORTH_ALL_NCSI_RXD1", - "NORTH_ALL_NCSI_CRS_DV", - "NORTH_ALL_NCSI_ARB_IN", - "NORTH_ALL_NCSI_TX_EN", - "NORTH_ALL_NCSI_TXD0", - "NORTH_ALL_NCSI_TXD1", - "NORTH_ALL_NCSI_ARB_OUT", - "NORTH_ALL_GBE0_LED0", - "NORTH_ALL_GBE0_LED1", - "NORTH_ALL_GBE1_LED0", - "NORTH_ALL_GBE1_LED1", - "NORTH_ALL_GPIO_0", - "NORTH_ALL_PCIE_CLKREQ0_N", - "NORTH_ALL_PCIE_CLKREQ1_N", - "NORTH_ALL_PCIE_CLKREQ2_N", - "NORTH_ALL_PCIE_CLKREQ3_N", - "NORTH_ALL_PCIE_CLKREQ4_N", - "NORTH_ALL_GPIO_1", - "NORTH_ALL_GPIO_2", - "NORTH_ALL_SVID_ALERT_N", - "NORTH_ALL_SVID_DATA", - "NORTH_ALL_SVID_CLK", - "NORTH_ALL_THERMTRIP_N", - "NORTH_ALL_PROCHOT_N", - "NORTH_ALL_MEMHOT_N", -}; - -static const struct gpio_group denverton_group_north_all = { - .display = "------- GPIO Group North All -------", - .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, - .func_count = 1, - .pad_names = denverton_group_north_all_names, -}; - -static const struct gpio_group *const denverton_community_north_groups[] = { - &denverton_group_north_all, -}; - -static const struct gpio_community denverton_community_north = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xc2, - .group_count = ARRAY_SIZE(denverton_community_north_groups), - .groups = denverton_community_north_groups, -}; - -static const char *const denverton_group_south_dfx_names[] = { - "SOUTH_DFX_DFX_PORT_CLK0", - "SOUTH_DFX_DFX_PORT_CLK1", - "SOUTH_DFX_DFX_PORT0", - "SOUTH_DFX_DFX_PORT1", - "SOUTH_DFX_DFX_PORT2", - "SOUTH_DFX_DFX_PORT3", - "SOUTH_DFX_DFX_PORT4", - "SOUTH_DFX_DFX_PORT5", - "SOUTH_DFX_DFX_PORT6", - "SOUTH_DFX_DFX_PORT7", - "SOUTH_DFX_DFX_PORT8", - "SOUTH_DFX_DFX_PORT9", - "SOUTH_DFX_DFX_PORT10", - "SOUTH_DFX_DFX_PORT11", - "SOUTH_DFX_DFX_PORT12", - "SOUTH_DFX_DFX_PORT13", - "SOUTH_DFX_DFX_PORT14", - "SOUTH_DFX_DFX_PORT15", -}; - -static const struct gpio_group denverton_group_south_dfx = { - .display = "------- GPIO Group South DFX -------", - .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_dfx_names, -}; - -static const char *const denverton_group_south_group0_names[] = { - "SOUTH_GROUP0_GPIO_12", - "SOUTH_GROUP0_SMB5_GBE_ALRT_N", - "SOUTH_GROUP0_PCIE_CLKREQ5_N", - "SOUTH_GROUP0_PCIE_CLKREQ6_N", - "SOUTH_GROUP0_PCIE_CLKREQ7_N", - "SOUTH_GROUP0_UART0_RXD", - "SOUTH_GROUP0_UART0_TXD", - "SOUTH_GROUP0_SMB5_GBE_CLK", - "SOUTH_GROUP0_SMB5_GBE_DATA", - "SOUTH_GROUP0_ERROR2_N", - "SOUTH_GROUP0_ERROR1_N", - "SOUTH_GROUP0_ERROR0_N", - "SOUTH_GROUP0_IERR_N", - "SOUTH_GROUP0_MCERR_N", - "SOUTH_GROUP0_SMB0_LEG_CLK", - "SOUTH_GROUP0_SMB0_LEG_DATA", - "SOUTH_GROUP0_SMB0_LEG_ALRT_N", - "SOUTH_GROUP0_SMB1_HOST_DATA", - "SOUTH_GROUP0_SMB1_HOST_CLK", - "SOUTH_GROUP0_SMB2_PECI_DATA", - "SOUTH_GROUP0_SMB2_PECI_CLK", - "SOUTH_GROUP0_SMB4_CSME0_DATA", - "SOUTH_GROUP0_SMB4_CSME0_CLK", - "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", - "SOUTH_GROUP0_USB_OC0_N", - "SOUTH_GROUP0_FLEX_CLK_SE0", - "SOUTH_GROUP0_FLEX_CLK_SE1", - "SOUTH_GROUP0_GPIO_4", - "SOUTH_GROUP0_GPIO_5", - "SOUTH_GROUP0_GPIO_6", - "SOUTH_GROUP0_GPIO_7", - "SOUTH_GROUP0_SATA0_LED_N", - "SOUTH_GROUP0_SATA1_LED_N", - "SOUTH_GROUP0_SATA_PDETECT0", - "SOUTH_GROUP0_SATA_PDETECT1", - "SOUTH_GROUP0_SATA0_SDOUT", - "SOUTH_GROUP0_SATA1_SDOUT", - "SOUTH_GROUP0_UART1_RXD", - "SOUTH_GROUP0_UART1_TXD", - "SOUTH_GROUP0_GPIO_8", - "SOUTH_GROUP0_GPIO_9", - "SOUTH_GROUP0_TCK", - "SOUTH_GROUP0_TRST_N", - "SOUTH_GROUP0_TMS", - "SOUTH_GROUP0_TDI", - "SOUTH_GROUP0_TDO", - "SOUTH_GROUP0_CX_PRDY_N", - "SOUTH_GROUP0_CX_PREQ_N", - "SOUTH_GROUP0_CTBTRIGINOUT", - "SOUTH_GROUP0_CTBTRIGOUT", - "SOUTH_GROUP0_DFX_SPARE2", - "SOUTH_GROUP0_DFX_SPARE3", - "SOUTH_GROUP0_DFX_SPARE4", -}; - -static const struct gpio_group denverton_group_south_group0 = { - .display = "------- GPIO Group South Group0 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group0_names, -}; - -static const char *const denverton_group_south_group1_names[] = { - "SOUTH_GROUP1_SUSPWRDNACK", - "SOUTH_GROUP1_PMU_SUSCLK", - "SOUTH_GROUP1_ADR_TRIGGER", - "SOUTH_GROUP1_PMU_SLP_S45_N", - "SOUTH_GROUP1_PMU_SLP_S3_N", - "SOUTH_GROUP1_PMU_WAKE_N", - "SOUTH_GROUP1_PMU_PWRBTN_N", - "SOUTH_GROUP1_PMU_RESETBUTTON_N", - "SOUTH_GROUP1_PMU_PLTRST_N", - "SOUTH_GROUP1_SUS_STAT_N", - "SOUTH_GROUP1_SLP_S0IX_N", - "SOUTH_GROUP1_SPI_CS0_N", - "SOUTH_GROUP1_SPI_CS1_N", - "SOUTH_GROUP1_SPI_MOSI_IO0", - "SOUTH_GROUP1_SPI_MISO_IO1", - "SOUTH_GROUP1_SPI_IO2", - "SOUTH_GROUP1_SPI_IO3", - "SOUTH_GROUP1_SPI_CLK", - "SOUTH_GROUP1_SPI_CLK_LOOPBK", - "SOUTH_GROUP1_ESPI_IO0", - "SOUTH_GROUP1_ESPI_IO1", - "SOUTH_GROUP1_ESPI_IO2", - "SOUTH_GROUP1_ESPI_IO3", - "SOUTH_GROUP1_ESPI_CS0_N", - "SOUTH_GROUP1_ESPI_CLK", - "SOUTH_GROUP1_ESPI_RST_N", - "SOUTH_GROUP1_ESPI_ALRT0_N", - "SOUTH_GROUP1_GPIO_10", - "SOUTH_GROUP1_GPIO_11", - "SOUTH_GROUP1_ESPI_CLK_LOOPBK", - "SOUTH_GROUP1_EMMC_CMD", - "SOUTH_GROUP1_EMMC_STROBE", - "SOUTH_GROUP1_EMMC_CLK", - "SOUTH_GROUP1_EMMC_D0", - "SOUTH_GROUP1_EMMC_D1", - "SOUTH_GROUP1_EMMC_D2", - "SOUTH_GROUP1_EMMC_D3", - "SOUTH_GROUP1_EMMC_D4", - "SOUTH_GROUP1_EMMC_D5", - "SOUTH_GROUP1_EMMC_D6", - "SOUTH_GROUP1_EMMC_D7", - "SOUTH_GROUP1_GPIO_3", -}; - -static const struct gpio_group denverton_group_south_group1 = { - .display = "------- GPIO Group South Group1 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group1_names, -}; - -static const struct gpio_group *const denverton_community_south_groups[] = { - &denverton_group_south_dfx, - &denverton_group_south_group0, - &denverton_group_south_group1, -}; - -static const struct gpio_community denverton_community_south = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(denverton_community_south_groups), - .groups = denverton_community_south_groups, -}; - -static const struct gpio_community *const denverton_communities[] = { - &denverton_community_north, &denverton_community_south, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h new file mode 100644 index 0000000..5553b7d --- /dev/null +++ b/util/inteltool/gpio_sunrise.h @@ -0,0 +1,595 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const sunrise_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_a_names, +}; + +static const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +static const char *const sunrise_group_b_names[] = { + "GPP_B0", "n/a", "n/a", "n/a", + "GPP_B1", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPIO_CS#", "n/a", "n/a", + "GPP_B16", "GSPIO_CLK", "n/a", "n/a", + "GPP_B17", "GSPIO_MISO", "n/a", "n/a", + "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_b_names, +}; + +static const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +static const struct gpio_group *const sunrise_community_ab_groups[] = { + &sunrise_group_a, &sunrise_group_b, +}; + +static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +static const struct gpio_community sunrise_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_community_ab_groups), + .groups = sunrise_community_ab_groups, +}; + +static const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +static const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +static const char *const sunrise_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "n/a", + "GPP_D1", "n/a", "n/a", "n/a", + "GPP_D2", "n/a", "n/a", "n/a", + "GPP_D3", "n/a", "n/a", "n/a", + "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", + "GPP_D5", "I2S_SFRM", "n/a", "n/a", + "GPP_D6", "I2S_TXD", "n/a", "n/a", + "GPP_D7", "I2S_RXD", "n/a", "n/a", + "GPP_D8", "I2S_SCLK", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "n/a", + "GPP_D22", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", +}; + +static const struct gpio_group sunrise_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_d_names, +}; + +static const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +static const char *const sunrise_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +static const char *const sunrise_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "n/a", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_f_names, +}; + +static const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +static const char *const sunrise_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", + "GPP_G8", "FAN_PWM_0", "n/a", "n/a", + "GPP_G9", "FAN_PWM_1", "n/a", "n/a", + "GPP_G10", "FAN_PWM_2", "n/a", "n/a", + "GPP_G11", "FAN_PWM_3", "n/a", "n/a", + "GPP_G12", "GSXDOUT", "n/a", "n/a", + "GPP_G13", "GSXSLOAD", "n/a", "n/a", + "GPP_G14", "GSXDIN", "n/a", "n/a", + "GPP_G15", "GSXRESET#", "n/a", "n/a", + "GPP_G16", "GSXCLK", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "n/a", "n/a", + "GPP_G21", "n/a", "n/a", "n/a", + "GPP_G22", "n/a", "n/a", "n/a", + "GPP_G23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_g_names, +}; + +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +static const char *const sunrise_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_h_names, +}; + +static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, + &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, +}; + +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +static const struct gpio_community sunrise_community_cdefgh = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), + .groups = sunrise_community_cdefgh_groups, +}; + +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +static const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +static const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +static const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +static const char *const sunrise_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "n/a", "n/a", + "GPP_I1", "DDPC_HPD1", "n/a", "n/a", + "GPP_I2", "DDPD_HPD2", "n/a", "n/a", + "GPP_I3", "DDPE_HPD3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_i_names, +}; + +static const struct gpio_group *const sunrise_community_i_groups[] = { + &sunrise_group_i, +}; + +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +static const struct gpio_community sunrise_community_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_community_i_groups), + .groups = sunrise_community_i_groups, +}; + +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +static const struct gpio_community *const sunrise_communities[] = { + &sunrise_community_ab, &sunrise_community_cdefgh, + &sunrise_community_gpd, &sunrise_community_i, +}; + +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Gerrit-Change-Number: 31504 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

7 34

Change in ...coreboot[master]: drivers/intel/mipi_camera: add functionality
by Matt Delco (Code Review) 26 Jun '20

26 Jun '20

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31163 Change subject: drivers/intel/mipi_camera: add functionality ...................................................................... drivers/intel/mipi_camera: add functionality Some boards & variants are using raw asl files to define the ACPI devices (and related properties) required by Linux MIPI camera drivers. These asl files lack the SSDB property that's required by Windows MIPI camera drivers. The mipi_camera driver can provide a SSDB property, but it's missing some properties needed for Linux (and my scan of the source code didn't find any current users of it). This change updates the mipi_camera driver so it can provide a combined superset of what's required by Linux and Windows. I've also expanded the support so it has support for the IMGU and CIO2 devices. BUG=none BRANCH=none TEST=Verified that the ACPI state generated by the driver (with appropriate devicetree changes) is extremely comparible to what's generated by the asl files. Verified that the camera still works in CrOS on Atlas. Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h M src/mainboard/google/poppy/dsdt.asl 3 files changed, 624 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31163/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 0cea0ba..8844206 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -15,69 +15,599 @@ #include <arch/acpi.h> #include <arch/acpi_device.h> +#include <arch/acpi_pld.h> #include <arch/acpigen.h> #include <console/console.h> #include <device/i2c_simple.h> #include <device/device.h> #include <device/path.h> +#include <device/pci_def.h> #include <string.h> #include "chip.h" +#define CIO2_PCI_DEV 0x14 +#define CIO2_PCI_FN 0x3 + +/* + * This implementation assumes there is only 1 endpoint at each end of every + * data port. It also assumes there are no clock lanes. It also assumes + * that any VCM or NVM for a CAM is on the same I2C bus as the CAM. + */ + +/* + * Adds settings for a CIO2 device (typically at "\_SB.PCI0.CIO2"). A _DSD is + * added that specifies a child table for each port (e.g., PRT0 for "port0" + * and PRT1 for "port1"). Each PRTx table specifies a table for each endpoint + * (though only 1 endpoint is supported by this implementation so the table + * only has an "endpoint0" that points to a EPx0 table). The EPx0 table + * primarily describes the # of lanes in "data-lines" and specifies the name + * of the other side in "remote-endpoint" (the name is usually of the form + * "\_SB.PCI0.I2Cx.CAM0" for the first port/cam and "\_SB.PCI0.I2Cx.CAM1" + * if there's a second port/cam). + */ +static void camera_fill_cio2(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + char *ep_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_name[MAX_PORT_ENTRIES] = {NULL}; + uint32_t i = 0; + char name[BUS_PATH_MAX]; + + if (!dsd) + return; + + for (i = 0; i < config->cio2_num_ports; ++i) { + struct acpi_dp *ep_table = NULL; + struct acpi_dp *port_table = NULL; + snprintf(name, sizeof(name), "EP%u0", i); + ep_table_name[i] = strdup(name); + if (!ep_table_name[i]) + break; + ep_table = acpi_dp_new_table(ep_table_name[i]); + if (!ep_table) + break; + acpi_dp_add_integer(ep_table, "endpoint", 0); + acpi_dp_add_integer(ep_table, "clock-lanes", 0); + if (config->cio2_lanes_used[i] > 0) { + struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); + if (lanes) { + uint32_t j; + for (j = 1; j <= config->cio2_lanes_used[i]; + ++j) { + acpi_dp_add_integer(lanes, NULL, j); + } + acpi_dp_add_array(ep_table, lanes); + } + } + if (config->cio2_lane_endpoint[i]) { + struct acpi_dp *remote = + acpi_dp_new_table("remote-endpoint"); + if (remote) { + acpi_dp_add_reference(remote, NULL, + config->cio2_lane_endpoint[i]); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_array(ep_table, remote); + } + } + snprintf(name, sizeof(name), "PRT%u", i); + port_table_name[i] = strdup(name); + if (!port_table_name[i]) { + // acpi_dp_free(ep_table); + break; + } + port_table = acpi_dp_new_table(port_table_name[i]); + if (!port_table) { + // acpi_dp_free(ep_table); + break; + } + acpi_dp_add_integer(port_table, "port", i); + acpi_dp_add_child(port_table, "endpoint0", ep_table); + + snprintf(name, sizeof(name), "port%u", i); + port_name[i] = strdup(name); + if (!port_name[i]) { + // acpi_dp_free(port_table); + break; + } + acpi_dp_add_child(dsd, port_name[i], port_table); + } + acpi_dp_write(dsd); + + for (i = 0; i < config->cio2_num_ports; ++i) { + free(ep_table_name[i]); + free(port_table_name[i]); + free(port_name[i]); + } +} + +/* + * Adds settings for a camera sensor device (typically at + * "\_SB.PCI0.I2Cx.CAMy"). The drivers for Linux tends to expect the camera + * sensor device and any related nvram / vcm devices to be separate ACPI + * devices, while the drivers for Windows want all of these to be grouped + * together in the camera sensor ACPI device. This implementation tries to + * satisfy both, though the unfortunate tradeoff is that the same I2C address + * for nvram and vcm is advertised by multiple devices in ACPI (via "_CRS"). + * The Windows driver can use the "_DSM" method to disambiguate the I2C + * resources in the camera sensor ACPI device. Drivers for Windows typically + * query "SSDB" for configuration information (represented as a binary blob + * dump of struct), while Linux drivers typically consult individual parameters + * in "_DSD". + * + * The tree of tables in "_DSD" is analogous to what's used for the "CIO2" + * device. The _DSD specifies a child table for the sensor's port (e.g., PRT0 + * for "port0"--this implementation assumes a camera only has 1 port). The + * PRT0 table specifies a table for each endpoint (though only 1 endpoint is + * supported by this implementation so the table only has an "endpoint0" that + * points to a EP00 table). The EP00 table primarily describes the # of lanes + * in "data-lines", a list of frequencies in "list-frequencies", and specifies + * the name of the other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2"). + */ +static void camera_fill_sensor(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *ep00 = NULL; + struct acpi_dp *prt0 = NULL; + struct acpi_dp *dsd = NULL; + uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF; + uint16_t i2c_addr = dev->path.i2c.device; + + if (config->use_pld && !config->disable_pld_defaults) { + if (!config->pld.ignore_color) + config->pld.ignore_color = 1; + if (!config->pld.visible) + config->pld.visible = 1; + if (!config->pld.vertical_offset) + config->pld.vertical_offset = 0xffff; + if (!config->pld.horizontal_offset) + config->pld.horizontal_offset = 0xffff; + /* + * PLD_PANEL_TOP has a value of zero, so the following + * will change any instance of PLD_PANEL_TOP to + * PLD_PANEL_FRONT unless disable_pld_defaults is set. + */ + if (!config->pld.panel) + config->pld.panel = PLD_PANEL_FRONT; + /* + * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so + * the following will change any instance of that value + * to PLD_HORIZONTAL_POSITION_CENTER unless + * disable_pld_defaults is set. + */ + if (!config->pld.horizontal_position) { + config->pld.horizontal_position = + PLD_HORIZONTAL_POSITION_CENTER; + } + /* + * The desired default for |vertical_position| is + * PLD_VERTICAL_POSITION_UPPER, which has a value of + * zero so no work is needed to set a default. The + * same applies for setting |shape| to PLD_SHAPE_ROUND. + */ + } + if (config->use_pld) + acpigen_write_pld(&config->pld); + + if (!config->disable_ssdb_defaults) { + if (!config->ssdb.bdf_value) { + config->ssdb.bdf_value = (CIO2_PCI_DEV << 3) | + CIO2_PCI_FN; + } + if (!config->ssdb.platform) + config->ssdb.platform = 9; + if (!config->ssdb.flash_support) + config->ssdb.flash_support = 2; + if (!config->ssdb.privacy_led) + config->ssdb.privacy_led = 1; + if (!config->ssdb.mipi_define) + config->ssdb.mipi_define = 1; + if (!config->ssdb.mclk_speed) + config->ssdb.mclk_speed = 19200000; + if (!config->ssdb.lanes_used) { + struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, + CIO2_PCI_FN); + struct drivers_intel_mipi_camera_config *cio2_config; + cio2_config = cio2 ? cio2->chip_info : NULL; + if (!cio2_config) { + printk(BIOS_ERR, "Failed to get CIO2 config\n"); + } else if (cio2_config->device_type != + INTEL_ACPI_CAMERA_CIO2) { + printk(BIOS_ERR, "Device type isn't CIO2: %u\n", + (u32)cio2_config->device_type); + } else if (config->ssdb.link_used >= + cio2_config->cio2_num_ports) { + printk(BIOS_ERR, "%u exceeds CIO2's %u links\n", + (u32)config->ssdb.link_used, + (u32)cio2_config->cio2_num_ports); + } else { + config->ssdb.lanes_used = + cio2_config->cio2_lanes_used[ + config->ssdb.link_used]; + } + } + } + + /* Method (_DSM, 4, NotSerialized) */ + acpigen_write_method("_DSM", 0x4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee"); + acpigen_write_return_string(config->sensor_name ? + config->sensor_name : "UNKNOWN"); + acpigen_pop_len(); /* If */ + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881"); + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + + /* If (LEqual (Local1, 1)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) + + (config->ssdb.rom_type ? 1 : 0) + 1); + acpigen_pop_len(); /* If Arg2=1 */ + + /* If (LEqual (Local1, 2)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 2); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)i2c_addr) << 8 | + 0x0); /* type 0 for sensor */ + acpigen_pop_len(); /* If Arg2=2 */ + + if (config->ssdb.vcm_type) { + /* If (LEqual (Local1, 3)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)config->vcm_address) + << 8 | + 0x01); /* type 1 for vcm */ + acpigen_pop_len(); /* If Arg2=3 */ + } + if (config->ssdb.rom_type) { + /* If (LEqual (Local1, 3 or 4)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + + (config->ssdb.vcm_type ? 1 : 0)); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)config->rom_address) + << 8 | + 0x02); /* type 2 for rom */ + acpigen_pop_len(); /* If Arg2=3 or 4 */ + } + + acpigen_pop_len(); /* If uuid */ + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Method _DSM */ + + /* end of _dsm */ + + ep00 = acpi_dp_new_table("EP00"); + if (ep00) { + struct acpi_dp *remote = NULL; + acpi_dp_add_integer(ep00, "endpoint", 0); + acpi_dp_add_integer(ep00, "clock-lanes", 0); + if (config->ssdb.lanes_used > 0) { + struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); + if (lanes) { + uint32_t i; + for (i = 1; i <= config->ssdb.lanes_used; ++i) + acpi_dp_add_integer(lanes, NULL, i); + acpi_dp_add_array(ep00, lanes); + } + } + if (config->num_freq_entries > 0) { + struct acpi_dp *freq = + acpi_dp_new_table("link-frequencies"); + if (freq) { + uint32_t i; + for (i = 0; i < config->num_freq_entries && + i < MAX_LINK_FREQ_ENTRIES; ++i) { + acpi_dp_add_integer(freq, NULL, + config->link_freq[i]); + } + acpi_dp_add_array(ep00, freq); + } + } + remote = acpi_dp_new_table("remote-endpoint"); + if (remote) { + const char *remote_name = NULL; + struct device *cio2 = NULL; + if (config->remote_name) { + remote_name = config->remote_name; + } else { + cio2 = pcidev_on_root(CIO2_PCI_DEV, + CIO2_PCI_FN); + if (cio2) + remote_name = acpi_device_path(cio2); + else + remote_name = "\\_SB.PCI0.CIO2"; + } + acpi_dp_add_reference(remote, NULL, remote_name); + acpi_dp_add_integer(remote, NULL, + config->ssdb.link_used); + acpi_dp_add_integer(remote, NULL, 0); /* endpoint? */ + acpi_dp_add_array(ep00, remote); + } + prt0 = acpi_dp_new_table("PRT0"); + } + if (!prt0) { + // acpi_dp_free(ep00); + } else { + acpi_dp_add_integer(prt0, "port", 0); + acpi_dp_add_child(prt0, "endpoint0", ep00); + dsd = acpi_dp_new_table("_DSD"); + } + if (!dsd) { + // acpi_dp_free(prt0); + } else { + const char *vcm_name = NULL; + acpi_dp_add_integer(dsd, "clock-frequency", + config->ssdb.mclk_speed); + if (config->ssdb.degree) + acpi_dp_add_integer(dsd, "rotation", 180); + if (config->ssdb.vcm_type) { + if (config->vcm_name) { + vcm_name = config->vcm_name; + } else { + const struct device_path path = { + .type = DEVICE_PATH_I2C, + .i2c.device = config->vcm_address, + }; + struct device *vcm_dev = find_dev_path(dev->bus, + &path); + struct drivers_intel_mipi_camera_config * + vcm_config; + vcm_config = vcm_dev ? vcm_dev->chip_info : + NULL; + if (!vcm_config) { + printk(BIOS_ERR, "Failed to get VCM\n"); + } else if (vcm_config->device_type != + INTEL_ACPI_CAMERA_VCM) { + printk(BIOS_ERR, "Device isn't VCM\n"); + } else { + vcm_name = acpi_device_path(vcm_dev); + } + } + } + if (vcm_name) + acpi_dp_add_reference(dsd, "lens-focus", vcm_name); + acpi_dp_add_child(dsd, "port0", prt0); + acpi_dp_write(dsd); + } + + acpigen_write_method_serialized("SSDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, + sizeof(config->ssdb)); + acpigen_pop_len(); /* Method */ + + /* Fill Power Sequencing Data */ + if (config->num_pwdb_entries > 0) { + acpigen_write_method_serialized("PWDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, + sizeof(struct intel_pwdb) * + config->num_pwdb_entries); + acpigen_pop_len(); /* Method */ + } +} + +static void camera_fill_nvm(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + if (!dsd) + return; + + /* It might be possible to default size or width based on type. */ + if (!config->disable_nvm_defaults && !config->nvm_pagesize) + config->nvm_pagesize = 1; + if (!config->disable_nvm_defaults && !config->nvm_readonly) + config->nvm_readonly = 1; + + if (config->nvm_size) + acpi_dp_add_integer(dsd, "size", config->nvm_size); + if (config->nvm_pagesize) + acpi_dp_add_integer(dsd, "pagesize", config->nvm_pagesize); + if (config->nvm_readonly) + acpi_dp_add_integer(dsd, "read-only", config->nvm_readonly); + if (config->nvm_width) + acpi_dp_add_integer(dsd, "address-width", config->nvm_width); + acpi_dp_write(dsd); +} + +static void camera_fill_vcm(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd; + + if (!config->vcm_compat) + return; + + dsd = acpi_dp_new_table("_DSD"); + if (!dsd) + return; + acpi_dp_add_string(dsd, "compatible", config->vcm_compat); + acpi_dp_write(dsd); +} + static void camera_fill_ssdt(struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); - struct acpi_i2c i2c = { - .address = dev->path.i2c.device, - .mode_10bit = dev->path.i2c.mode_10bit, - .speed = I2C_SPEED_FAST, - .resource = scope, - }; if (!dev->enabled || !scope) return; /* Device */ - acpigen_write_scope(scope); - acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_string("_HID", config->acpi_hid); - acpigen_write_name_integer("_UID", config->acpi_uid); - acpigen_write_name_string("_DDN", config->chip_name); - acpigen_write_STA(acpi_device_status(dev)); + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU) { + u32 address; - /* Resources */ - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - acpi_device_write_i2c(&i2c); - acpigen_write_resourcetemplate_footer(); + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); + return; + } + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + acpigen_write_name_string("_DDN", + config->device_type == INTEL_ACPI_CAMERA_CIO2 ? + "Camera and Imaging Subsystem" : "Imaging Unit"); + } else { + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; - /* Mark it as Camera related device */ - acpigen_write_name_integer("CAMD", config->device_type); + if (dev->path.type != DEVICE_PATH_I2C) { + printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); + return; + } - /* Create Device specific data */ - if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) { - acpigen_write_method_serialized("SSDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, - sizeof(config->ssdb)); - acpigen_pop_len(); /* Method */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) + acpigen_write_name_integer("_ADR", 0); + if (config->acpi_hid) + acpigen_write_name_string("_HID", config->acpi_hid); + else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + acpigen_write_name_string("_HID", + ACPI_DT_NAMESPACE_HID); + else if (config->device_type == INTEL_ACPI_CAMERA_NVM) + acpigen_write_name_string("_HID", "INT3499"); + acpigen_write_name_integer("_UID", config->acpi_uid); + acpigen_write_name_string("_DDN", config->chip_name); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + /* + * The optional vcm/nvram devices are presumed to be on the + * same I2C bus as the camera sensor. + */ + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.vcm_type) { + struct acpi_i2c i2c_vcm = i2c; + i2c_vcm.address = config->vcm_address; + acpi_device_write_i2c(&i2c_vcm); + } + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.rom_type) { + struct acpi_i2c i2c_rom = i2c; + i2c_rom.address = config->rom_address; + acpi_device_write_i2c(&i2c_rom); + } + acpigen_write_resourcetemplate_footer(); } - /* Fill Power Sequencing Data */ - acpigen_write_method_serialized("PWDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, - (sizeof(struct intel_pwdb) * config->num_pwdb_entries)); - acpigen_pop_len(); /* Method */ + /* Mark it as Camera related device */ + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU || + config->device_type == INTEL_ACPI_CAMERA_SENSOR || + config->device_type == INTEL_ACPI_CAMERA_VCM) { + acpigen_write_name_integer("CAMD", config->device_type); + } + + if (config->dep) { + acpigen_write_name("_DEP"); + acpigen_write_package(1); + acpigen_emit_namestring(config->dep); + acpigen_pop_len(); + } + if (config->pr0) { + acpigen_write_name("_PR0"); + acpigen_write_package(1); + acpigen_emit_namestring(config->pr0); + acpigen_pop_len(); + } + /* It's very unlikely you need _PR3 for any camera device */ + if (config->pr3) { + acpigen_write_name("_PR3"); + acpigen_write_package(1); + acpigen_emit_namestring(config->pr3); + acpigen_pop_len(); + } + + if (config->device_type == INTEL_ACPI_CAMERA_CIO2) + camera_fill_cio2(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) + camera_fill_sensor(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_NVM) + camera_fill_nvm(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + camera_fill_vcm(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev), - dev->chip_ops->name, dev->path.i2c.device); + if (dev->path.type == DEVICE_PATH_PCI) { + printk(BIOS_INFO, "%s: %s PCI address 0%x\n", + acpi_device_path(dev), + dev->chip_ops->name, dev->path.pci.devfn); + } else { + printk(BIOS_INFO, "%s: %s I2C address 0%xh\n", + acpi_device_path(dev), + dev->chip_ops->name, dev->path.i2c.device); + } } static const char *camera_acpi_name(const struct device *dev) { + const char *prefix = NULL; + static char name[BUS_PATH_MAX]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; - return config->acpi_name; + if (config->acpi_name) + return config->acpi_name; + if (config->device_type == INTEL_ACPI_CAMERA_CIO2) + return "CIO2"; + else if (config->device_type == INTEL_ACPI_CAMERA_IMGU) + return "IMGU"; + else if (config->device_type == INTEL_ACPI_CAMERA_PMIC) + return "PMIC"; + + switch (config->device_type) { + case INTEL_ACPI_CAMERA_SENSOR: + prefix = "CAM"; + break; + case INTEL_ACPI_CAMERA_VCM: + prefix = "VCM"; + break; + case INTEL_ACPI_CAMERA_NVM: + prefix = "NVM"; + break; + default: + prefix = "ERR"; /* Error */ + break; + } + /* + * The cameras know which link # they use, so that's used + * as the basis for the instance #. The VCM and NVM don't + * have this information, so the best we can go on is the + * _UID. + */ + snprintf(name, sizeof(name), "%s%u", prefix, + config->device_type == INTEL_ACPI_CAMERA_SENSOR ? + config->ssdb.link_used : config->acpi_uid); + return name; } static struct device_operations camera_ops = { diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 741ae8e..50b757c 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -17,14 +17,19 @@ #define __INTEL_MIPI_CAMERA_CHIP_H__ #include <stdint.h> +#include <arch/acpi_pld.h> #define MAX_PWDB_ENTRIES 12 +#define MAX_PORT_ENTRIES 4 +#define MAX_LINK_FREQ_ENTRIES 4 enum intel_camera_device_type { INTEL_ACPI_CAMERA_CIO2, INTEL_ACPI_CAMERA_IMGU, INTEL_ACPI_CAMERA_SENSOR, INTEL_ACPI_CAMERA_VCM, + /* Value for NVM might might not be appropriate for CAMD */ + INTEL_ACPI_CAMERA_NVM, INTEL_ACPI_CAMERA_PMIC = 100, }; @@ -77,12 +82,14 @@ uint8_t degree; /* Camera Orientation */ uint8_t mipi_define; /* MIPI info defined in ACPI or sensor driver */ - uint32_t mclk; /* Clock info for sensor */ + uint32_t mclk_speed; /* Clock info for sensor */ uint8_t control_logic_id; /* PMIC device node used for the camera sensor */ uint8_t mipi_data_format; /* MIPI data format */ uint8_t silicon_version; /* Silicon version */ uint8_t customer_id; /* Customer ID */ + uint8_t mclk_port; + uint8_t reserved[13]; } __packed; struct intel_pwdb { @@ -95,14 +102,59 @@ } __packed; struct drivers_intel_mipi_camera_config { + /* Generic settings */ + enum intel_camera_device_type device_type; + + /* Settings that should not need to be set since defaults sane. */ + const char *acpi_name; /* defaults: CIO2,IMGU,PMIC,CAMx,VCMx,NVMx */ + + /* + * General settings that can be used for any type (but doesn't + * necessarily need to be used/specified for each device. + */ + const char *chip_name; + const char *acpi_hid; /* vcm and nvm have defaults */ + unsigned int acpi_uid; + const char *dep; + const char *pr0; + const char *pr3; /* _PR3 shouldn't be needed */ + + /* Settings specific to CIO2 device */ + uint32_t cio2_num_ports; + uint32_t cio2_lanes_used[MAX_PORT_ENTRIES]; + const char *cio2_lane_endpoint[MAX_PORT_ENTRIES]; + + /* Settings specific to camera sensor */ + bool disable_ssdb_defaults; struct intel_ssdb ssdb; struct intel_pwdb pwdb[MAX_PWDB_ENTRIES]; - enum intel_camera_device_type device_type; uint8_t num_pwdb_entries; - const char *acpi_hid; - const char *acpi_name; - const char *chip_name; - unsigned int acpi_uid; + uint8_t num_freq_entries; /* # of elements in link_freq */ + uint32_t link_freq[MAX_LINK_FREQ_ENTRIES]; + const char *sensor_name; /* default "UNKNOWN" */ + const char *remote_name; /* default "\_SB.PCI0.CIO2" */ + const char *vcm_name; /* defaults to |vcm_address| device */ + bool use_pld; + bool disable_pld_defaults; + struct acpi_pld pld; + uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ + uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */ + + /* + * Settings specific to nvram. Many values, if left as zero, + * will be assigned a default. Set disable_nvm_defaults to + * non-zero if you want to disable the defaulting behavior so + * you can use zero for a value. + */ + + bool disable_nvm_defaults; + uint32_t nvm_size; + uint32_t nvm_pagesize; + uint32_t nvm_readonly; + uint32_t nvm_width; + + /* Settings specific to vcm */ + const char *vcm_compat; }; #endif diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 0001867..d923ba5 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -39,8 +39,10 @@ { Device (PCI0) { - /* Image processing unit */ +#if !IS_ENABLED(CONFIG_DRIVERS_INTEL_MIPI_CAMERA) + /* Image processing unit, if not using MIPI driver */ #include <soc/intel/skylake/acpi/ipu.asl> +#endif #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/31163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08 Gerrit-Change-Number: 31163 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: _WIP_ mb/amd/mandolin: Add Picasso CRB
by Marshall Dawson (Code Review) 21 Jun '20

21 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33772 Change subject: _WIP_ mb/amd/mandolin: Add Picasso CRB ...................................................................... _WIP_ mb/amd/mandolin: Add Picasso CRB We can get into ramstage with the state of Mandolin. Still no AGESA running, and therefore we hang when trying to scan the PCI bus. Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/mainboard/amd/mandolin/Kconfig A src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/acpi/gpe.asl A src/mainboard/amd/mandolin/acpi/mainboard.asl A src/mainboard/amd/mandolin/acpi/routing.asl A src/mainboard/amd/mandolin/acpi/sleep.asl A src/mainboard/amd/mandolin/acpi/usb_oc.asl A src/mainboard/amd/mandolin/acpi_tables.c A src/mainboard/amd/mandolin/board_info.txt A src/mainboard/amd/mandolin/devicetree.cb A src/mainboard/amd/mandolin/dsdt.asl A src/mainboard/amd/mandolin/gpio.c A src/mainboard/amd/mandolin/gpio.h A src/mainboard/amd/mandolin/irq_tables.c A src/mainboard/amd/mandolin/mainboard.c A src/mainboard/amd/mandolin/mptable.c A src/mainboard/amd/mandolin/romstage.c 18 files changed, 1,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33772/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig new file mode 100644 index 0000000..5d1c287 --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig @@ -0,0 +1,98 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_MANDOLIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_PICASSO + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config AMD_LPC_DEBUG_CARD + bool "Enable LPC-Serial debug card on the debug header" + default n + select SUPERIO_SMSC_SIO1036 + help + AMD's debug card contains an SMSC SIO1036 device which provides + an I/O-based UART in the system. This feature is not compatible with + CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. + Note that Kconfig does not currently enforce this restriction. + +config CBFS_SIZE + default 0x400000 + help + TODO: Adjust this! Right now it's simply making a lot of room for + amdfw.rom and EC firmware. + +config MAINBOARD_DIR + string + default amd/mandolin + +config MAINBOARD_PART_NUMBER + string + default "MANDOLIN" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config PICASSO_LEGACY_FREE + bool + default y + +config MANDOLIN_HAVE_APCB_BLOB + bool "Have AGESA PSP Customization Block file?" + default n + help + The PSP requires the APCB file to know how to configure memory, as + well as other settings it will initialize. To build an image that + will get to POST, select 'y' and provide the file path/name. The + default of 'n' allows the board to build successfully but it avoids + redistributing the APCB blob extracted from UEFI. + TODO: Add the ability to construct APCB on the fly for any mainboard. + +config PSP_APCB_FILE + string "APCB file" + depends on MANDOLIN_HAVE_APCB_BLOB + default "3rdparty/blobs/mainboard/amd/mandolin/apcb.bin" + help + The name of the AGESA Parameter Customization Block. TODO: will we + be able to generate this at build-time? Build it offline for + inclusion? + +config MANDOLIN_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + select AMDFW_OUTSIDE_CBFS + # todo: fix build the "inside" build. + +config MANDOLIN_MCHP_FW_FILE + string + depends on MANDOLIN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin" + +endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name new file mode 100644 index 0000000..7dbfc3f --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MANDOLIN + bool "Mandolin" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc new file mode 100644 index 0000000..fe17e8e --- /dev/null +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -0,0 +1,41 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += gpio.c +ramstage-y += gpio.c + +PHONY+=add_mchp_fw +INTERMEDIATE+=add_mchp_fw + +ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) + +MANDOLIN_MICROCHIP_FW_OFFSET=0 +add_mchp_fw: + printf " DD Adding Microchip firmware at ROM offset 0x%x\n" \ + "$(MANDOLIN_MICROCHIP_FW_OFFSET)" + dd if=$(CONFIG_MANDOLIN_MCHP_FW_FILE) \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 \ + seek=$(MANDOLIN_MICROCHIP_FW_OFFSET) >/dev/null 2>&1 + +else +files_added:: warn_no_mchp +endif # CONFIG_MANDOLIN_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC.\n" + printf "Do not flash this image. Your Mandolin's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/mandolin/acpi/gpe.asl b/src/mainboard/amd/mandolin/acpi/gpe.asl new file mode 100644 index 0000000..d3c89fd --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/gpe.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/mandolin/acpi/mainboard.asl b/src/mainboard/amd/mandolin/acpi/mainboard.asl new file mode 100644 index 0000000..d73fbea --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/mainboard.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/mandolin/acpi/routing.asl b/src/mainboard/amd/mandolin/acpi/routing.asl new file mode 100644 index 0000000..969def7 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/routing.asl @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, +}) + + +/* GPP 0 */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl new file mode 100644 index 0000000..baf3ca5 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/sleep.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/mandolin/acpi/usb_oc.asl b/src/mainboard/amd/mandolin/acpi/usb_oc.asl new file mode 100644 index 0000000..ea7bd27 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/usb_oc.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// - file had a todo to update for Gardenia +// +// +// + +/* simple name description */ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ diff --git a/src/mainboard/amd/mandolin/acpi_tables.c b/src/mainboard/amd/mandolin/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/mandolin/board_info.txt b/src/mainboard/amd/mandolin/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/mandolin/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb new file mode 100644 index 0000000..8cb7da9 --- /dev/null +++ b/src/mainboard/amd/mandolin/devicetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/picasso + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.2 on end # Bridge + device pci 1.3 on end # Bridge + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on end # Bridge + device pci 8.2 on end # Bridge + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + device i2c 51 on end + end + chip superio/smsc/sio1036 # optional debug card + end + end # SM + device pci 14.3 on end # LPC + device pci 14.6 on end # + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + # todo: on a separate bus now: + # 2:0.0 15D8 display controller + # 2:0.1 15DE HD Audio + # 2:0.2 15DF Crypto Coprocessor + # 2:0.3 15E0 serial + # 2:0.4 15E1 serial + # 2:0.5 15E2 Audio Processor + # 2:0.6 15E3 Audio Processor - HD Audio Controller + # 2:0.7 15E6 Non-Sensor Fusion hub device + # 3:0.0 7901 SATA + # 3:0.1 1458 10GbE (per HDT) + # 3:0.2 1458 10GbE (per HDT) +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl new file mode 100644 index 0000000..25c0e78 --- /dev/null +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// +// +// +// todo: check file for accuracy +// +// +// + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c new file mode 100644 index 0000000..aa16826 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/southbridge.h> +#include <stdlib.h> +#include <soc/gpio.h> + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC5_L */ + PAD_GPI(GPIO_13, PULL_UP), + /* not USB_OC4_L */ + PAD_GPI(GPIO_14, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe SSD power enable */ + PAD_GPO(GPIO_23, HIGH), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0_S5, PULL_NONE), + /* SATA Express DEVSLP */ + PAD_NF(GPIO_6, DEVSLP1_S5, PULL_NONE), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h new file mode 100644 index 0000000..1d3a8a2 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mandolin/irq_tables.c b/src/mainboard/amd/mandolin/irq_tables.c new file mode 100644 index 0000000..bf1daec --- /dev/null +++ b/src/mainboard/amd/mandolin/irq_tables.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c new file mode 100644 index 0000000..6f2d1d9 --- /dev/null +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/southbridge.h> + +#include "gpio.h" +// +// +// +// todo: check file for accuracy +// +// +// + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in mandolin board. + *************************************************/ +static void mandolin_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mandolin_enable, +}; diff --git a/src/mainboard/amd/mandolin/mptable.c b/src/mainboard/amd/mandolin/mptable.c new file mode 100644 index 0000000..4e80ce1 --- /dev/null +++ b/src/mainboard/amd/mandolin/mptable.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/x86/lapic.h> +#include <soc/southbridge.h> +#include <amdblocks/amd_pci_util.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c new file mode 100644 index 0000000..1741a39 --- /dev/null +++ b/src/mainboard/amd/mandolin/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <superio/smsc/sio1036/sio1036.h> +#include <soc/gpio.h> +#include "gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) + +void romstage_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + + if (CONFIG(SUPERIO_SMSC_SIO1036)) + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Gerrit-Change-Number: 33772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 65

Change in ...coreboot[master]: google_chromeec_command: makes the error status consistent
by YH Lin (Code Review) 20 Jun '20

20 Jun '20

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31626 Change subject: google_chromeec_command: makes the error status consistent ...................................................................... google_chromeec_command: makes the error status consistent Currently various google_chromeec_command() implementation the error can be returned differently (LPC: -1 for v3, 1 for v1, SPI: -1/1, I2C: 1). This patch attempts to make it consistent across all implementations by using only negative number as error. All direct/indirect callers of google_chromeec_command() have also been modified accordingly as well. BRANCH=None BUG=chromium:935038 Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29 --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/mainboard/google/gru/mainboard.c M src/security/vboot/vboot_logic.c 10 files changed, 35 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31626/1 diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 2043347..603f1df 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -246,7 +246,7 @@ int rv = send_command_proto3(cec_command, crosec_io, context); if (rv < 0) { cec_command->cmd_code = rv; - return 1; + return -1; } return 0; } diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 09357b0..897dceb 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -363,7 +363,7 @@ cmd.cmd_size_out = sizeof(rsp); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) == 0) + if (google_chromeec_command(&cmd) >= 0) return rsp.event_mask; return 0; } @@ -404,7 +404,7 @@ cmd.cmd_size_out = sizeof(rsp); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) == 0) + if (google_chromeec_command(&cmd) >= 0) return rsp.event_mask; return 0; } @@ -507,7 +507,7 @@ cmd.cmd_size_out = sizeof(r); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; if (feature >= 8 * sizeof(r.flags)) @@ -531,7 +531,7 @@ cmd.cmd_size_out = 0; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; return 0; @@ -550,7 +550,7 @@ cmd.cmd_size_out = sizeof(r); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; return rtc_to_tm(r.time, time); @@ -658,7 +658,7 @@ cmd.cmd_data_out = &board_v; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd)) + if (google_chromeec_command(&cmd) < 0) return -1; *version = board_v.board_version; @@ -677,7 +677,7 @@ cmd.cmd_data_out = &sku_v; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return 0; return sku_v.sku_id; @@ -708,7 +708,7 @@ if (!is_read) memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE); - if (google_chromeec_command(&cec_cmd)) { + if (google_chromeec_command(&cec_cmd) < 0) { printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n", is_read ? "read" : "write", (int)cec_cmd.cmd_code); mdelay(10); /* just in case */ @@ -792,7 +792,7 @@ cmd.cmd_size_out = sizeof(*r) + read_len; cmd.cmd_dev_index = 0; rv = google_chromeec_command(&cmd); - if (rv != 0) + if (rv < 0) return rv; /* Parse response */ @@ -875,7 +875,7 @@ }; struct usb_chg_measures m; int rv = google_chromeec_command(&cmd); - if (rv != 0) + if (rv < 0) return rv; /* values are given in milliAmps and milliVolts */ *type = rsp.type; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 7a38336..51124f6 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -108,7 +108,7 @@ * * @param type charger type * @param max_watts charger max wattage - * @return non-zero for error, otherwise 0. + * @return 0 on success or negative integer for errors. */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, u32 *max_watts); @@ -118,7 +118,7 @@ * * @param current_lim Max current in mA * @param voltage_lim Max voltage in mV - * @return non-zero for error, otherwise 0. + * @return 0 on success or negative integer for errors. */ int google_chromeec_override_dedicated_charger_limit(u16 current_lim, u16 voltage_lim); @@ -150,6 +150,8 @@ * The lower level transport works on the buffers handed out to the * upper level. Therefore, only the size of the request and response * are required. + * + * @return 0 on success or negative integer for errors. */ typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context); int crosec_command_proto(struct chromeec_command *cec_command, @@ -159,7 +161,7 @@ * Send a command to a CrOS EC * * @param cec_command: CrOS EC command to send - * @return 0 for success. Non-zero for error. + * @return 0 on success or negative integer for errors. */ int google_chromeec_command(struct chromeec_command *cec_command); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 22b491a..7f2ead5 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -205,7 +205,7 @@ __func__, cec_command->cmd_size_in, cec_command->cmd_size_out); cec_command->cmd_code = EC_RES_INVALID_PARAM; - return 1; + return -1; } /* Construct command. */ @@ -221,13 +221,13 @@ printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; - return 1; + return -1; } if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) { printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; - return 1; + return -1; } /* Verify and return response */ @@ -235,17 +235,17 @@ if (resp.response != EC_RES_SUCCESS) { printk(BIOS_DEBUG, "%s: Received bad result code %d\n", __func__, (int)resp.response); - return 1; + return -1; } if (resp.length > cec_command->cmd_size_out) { printk(BIOS_ERR, "%s: Received len %#02x too large\n", __func__, (int)resp.length); cec_command->cmd_code = EC_RES_INVALID_RESPONSE; - return 1; + return -1; } if (!ec_verify_checksum(&resp)) { cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; - return 1; + return -1; } cec_command->cmd_size_out = resp.length; memcpy(cec_command->cmd_data_out, resp.data, resp.length); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 61005d3..097b1b4 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -330,13 +330,13 @@ if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", cec_command->cmd_code); - return 1; + return -1; } /* Check result */ cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA); if (cec_command->cmd_code) - return 1; + return -1; /* Read back args */ read_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL); @@ -348,12 +348,12 @@ */ if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) { printk(BIOS_ERR, "EC protocol mismatch\n"); - return 1; + return -1; } if (args.data_size > cec_command->cmd_size_out) { printk(BIOS_ERR, "EC returned too much data\n"); - return 1; + return -1; } cec_command->cmd_size_out = args.data_size; @@ -369,7 +369,7 @@ /* Verify checksum */ if (args.checksum != csum) { printk(BIOS_ERR, "EC response has invalid checksum\n"); - return 1; + return -1; } return 0; diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index cab7192..3f703f9 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -54,7 +54,7 @@ ; printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n"); - while (google_chromeec_get_mkbp_event(&mkbp_event) == 0) + while (google_chromeec_get_mkbp_event(&mkbp_event) >= 0) ; } diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index f47c2f1..08af2f6 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -30,7 +30,7 @@ /* Ensure the digests being saved match the EC's slot size. */ assert(digest_size == EC_VSTORE_SLOT_SIZE); - if (google_chromeec_vstore_write(slot, digest, digest_size)) + if (google_chromeec_vstore_write(slot, digest, digest_size) < 0) return -1; /* Assert the slot is locked on successful write. */ diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c2603..39e59f8 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -42,7 +42,7 @@ .cmd_data_out = &info, }; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return 0; if (locked) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 41307c7..245a70e 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -257,12 +257,14 @@ static void usb_power_cycle(int port) { - if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) + if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK) + < 0) printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); mdelay(10); /* Make sure USB stick is fully depowered. */ - if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) + if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON) + < 0) printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 00bbae6..c379463 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -141,7 +141,7 @@ printk(BIOS_DEBUG, "Platform is resuming.\n"); - if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) { + if (vboot_retrieve_hash(saved_hash, saved_hash_sz) < 0) { printk(BIOS_ERR, "Couldn't retrieve saved hash.\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29 Gerrit-Change-Number: 31626 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: vboot: Turn vboot_logic_executed() into a static inline
by Julius Werner (Code Review) 27 May '20

27 May '20

Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32716 to review the following change. Change subject: vboot: Turn vboot_logic_executed() into a static inline ...................................................................... vboot: Turn vboot_logic_executed() into a static inline This patch moves vboot_logic_executed() (and its dependencies) into a header and turns it into a static inline function. The function is used to guard larger amounts of code in several places, so this should allow us to safe some more space through compile-time elimination (and also makes it easier to avoid undefined reference issues in some cases). Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/misc.h M src/security/vboot/vboot_loader.c 2 files changed, 58 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32716/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index b4fae19..2a0523d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -16,6 +16,8 @@ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ +#include <assert.h> +#include <arch/early_variables.h> #include <security/vboot/vboot_common.h> struct vb2_context; @@ -66,13 +68,63 @@ void vboot_fill_handoff(void); /* - * Source: security/vboot/vboot_loader.c - */ -int vboot_logic_executed(void); - -/* * Source: security/vboot/bootmode.c */ void vboot_save_recovery_reason_vbnv(void); +/* + * The stage loading code is compiled and entered from multiple stages. The + * helper functions below attempt to provide more clarity on when certain + * code should be called. They are implemented inline for better compile-time + * code elimination. + */ + +static inline int verification_should_run(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_VERSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return ENV_ROMSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return ENV_BOOTBLOCK; + else + dead_code(); +} + +static inline int verstage_should_load(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_BOOTBLOCK; + else + return 0; +} + +/* Only for use by functions in this header, do not access directly! */ +extern int vboot_executed; + +static inline int vboot_logic_executed(void) +{ + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) + return car_get_var(vboot_executed); + + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + /* All other stages are "after the bootblock" */ + return !ENV_BOOTBLOCK; + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + /* Post-RAM stages are "after the romstage" */ +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } else { + dead_code(); + } +} + + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3bbb3da..1350307 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -36,55 +36,7 @@ CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -/* The stage loading code is compiled and entered from multiple stages. The - * helper functions below attempt to provide more clarity on when certain - * code should be called. */ - -static int verification_should_run(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - return ENV_ROMSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return ENV_BOOTBLOCK; - else - die("impossible!"); -} - -static int verstage_should_load(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_BOOTBLOCK; - else - return 0; -} - -static int vboot_executed CAR_GLOBAL; - -int vboot_logic_executed(void) -{ - /* If we are in the stage that runs verification, or in the stage that - both loads the verstage and is returned to from it afterwards, we - need to check a global to see if verfication has run. */ - if (verification_should_run() || - (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) - return car_get_var(vboot_executed); - - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - /* All other stages are "after the bootblock" */ - return !ENV_BOOTBLOCK; - } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif - } else { - die("impossible!"); - } -} +int vboot_executed CAR_GLOBAL; static void vboot_prepare(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Gerrit-Change-Number: 32716 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in ...coreboot[master]: src/mainboard: Add dell/inspiron_n5110
by Angel Pons (Code Review) 23 May '20

23 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30996 Change subject: src/mainboard: Add dell/inspiron_n5110 ...................................................................... src/mainboard: Add dell/inspiron_n5110 Run autoport and clean up. It has Nvidia Optimus, a NPCE795 EC, a PCIe xHCI controller and who knows what else. The 4MB flash is shared with the EC, apparently. Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/inspiron_n5110/Kconfig A src/mainboard/dell/inspiron_n5110/Kconfig.name A src/mainboard/dell/inspiron_n5110/Makefile.inc A src/mainboard/dell/inspiron_n5110/acpi/ec.asl A src/mainboard/dell/inspiron_n5110/acpi/platform.asl A src/mainboard/dell/inspiron_n5110/acpi/superio.asl A src/mainboard/dell/inspiron_n5110/acpi_tables.c A src/mainboard/dell/inspiron_n5110/board_info.txt A src/mainboard/dell/inspiron_n5110/devicetree.cb A src/mainboard/dell/inspiron_n5110/dsdt.asl A src/mainboard/dell/inspiron_n5110/gma-mainboard.ads A src/mainboard/dell/inspiron_n5110/gpio.c A src/mainboard/dell/inspiron_n5110/hda_verb.c A src/mainboard/dell/inspiron_n5110/mainboard.c A src/mainboard/dell/inspiron_n5110/romstage.c 17 files changed, 685 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30996/1 diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig b/src/mainboard/dell/inspiron_n5110/Kconfig new file mode 100644 index 0000000..1a12055 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Kconfig @@ -0,0 +1,54 @@ +if BOARD_DELL_INSPIRON_N5110 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select GFX_GMA_INTERNAL_IS_LVDS + select SERIRQ_CONTINUOUS_MODE + select NO_UART_ON_SUPERIO + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + +config MAINBOARD_DIR + string + default dell/inspiron_n5110 + +config MAINBOARD_PART_NUMBER + string + default "Inspiron N5110" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x4b0 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1028 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig.name b/src/mainboard/dell/inspiron_n5110/Kconfig.name new file mode 100644 index 0000000..06334cd --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_INSPIRON_N5110 + bool "Inspiron N5110" diff --git a/src/mainboard/dell/inspiron_n5110/Makefile.inc b/src/mainboard/dell/inspiron_n5110/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/inspiron_n5110/acpi/ec.asl b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl diff --git a/src/mainboard/dell/inspiron_n5110/acpi/platform.asl b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl new file mode 100644 index 0000000..cf5d74f --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/dell/inspiron_n5110/acpi/superio.asl b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl diff --git a/src/mainboard/dell/inspiron_n5110/acpi_tables.c b/src/mainboard/dell/inspiron_n5110/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/inspiron_n5110/board_info.txt b/src/mainboard/dell/inspiron_n5110/board_info.txt new file mode 100644 index 0000000..f48c92b --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/dell/inspiron_n5110/devicetree.cb b/src/mainboard/dell/inspiron_n5110/devicetree.cb new file mode 100644 index 0000000..be4f590 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/devicetree.cb @@ -0,0 +1,73 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x0000035e" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "3000" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x1028 0x04b0 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen2_dec" = "0x0004006d" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 1 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/inspiron_n5110/dsdt.asl b/src/mainboard/dell/inspiron_n5110/dsdt.asl new file mode 100644 index 0000000..1b0cae2 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/inspiron_n5110/gpio.c b/src/mainboard/dell/inspiron_n5110/gpio.c new file mode 100644 index 0000000..7926ee1 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/inspiron_n5110/hda_verb.c b/src/mainboard/dell/inspiron_n5110/hda_verb.c new file mode 100644 index 0000000..a70733b --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76d1, /* Codec Vendor / Device ID: IDT */ + 0x102804b0, /* Subsystem ID */ + + 0x00000007, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x102804b0), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f2), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30160), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/inspiron_n5110/mainboard.c b/src/mainboard/dell/inspiron_n5110/mainboard.c new file mode 100644 index 0000000..02fe3a5 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/inspiron_n5110/romstage.c b/src/mainboard/dell/inspiron_n5110/romstage.c new file mode 100644 index 0000000..fd2f79f --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004006d); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Assumed completely. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9 Gerrit-Change-Number: 30996 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: src/cpu/x86: Check pointer processor_name_start before dereference
by John Zhao (Code Review) 20 May '20

20 May '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33232 Change subject: src/cpu/x86: Check pointer processor_name_start before dereference ...................................................................... src/cpu/x86: Check pointer processor_name_start before dereference Clang Static Analyzer version 8.0.0 detects the left operand of '==' is a garbage value if pointer processor_name_start is NULL. Add sanity check for processor_name_start before dereference. TEST=Built and boot up to kernel. Change-Id: I1f831a8661a4686d306b8217655942934102ea16 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/cpu/x86/name/name.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33232/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index fc360cd..44a1cf0 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -37,6 +37,9 @@ /* Skip leading spaces. */ processor_name_start = (char *)name_as_ints; + if (!processor_name_start) + return; + while (*processor_name_start == ' ') processor_name_start++; -- To view, visit https://review.coreboot.org/c/coreboot/+/33232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f831a8661a4686d306b8217655942934102ea16 Gerrit-Change-Number: 33232 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: payloads/ipxe: Enable HTTPS support
by Felix Singer (Code Review) 01 May '20

01 May '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31086 Change subject: payloads/ipxe: Enable HTTPS support ...................................................................... payloads/ipxe: Enable HTTPS support HTTPS needs a newer iPXE version than 2017.3, because it doesn't work with this release. Tested under master branch. Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31086/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..05b6f4dd 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Gerrit-Change-Number: 31086 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

6 18

Change in ...coreboot[master]: security/lockdown: Write-protect WP_RO
by Patrick Rudolph (Code Review) 27 Apr '20

27 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32705 Change subject: security/lockdown: Write-protect WP_RO ...................................................................... security/lockdown: Write-protect WP_RO Add another choice to boot media protection and write-protect WP_RO in case VBOOT is enabled. Tested on Lenovo T520: The WP_RO region is write-protected. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/bootmedia.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32705/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index bb4d072..1e982d8 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -15,6 +15,18 @@ config BOOTMEDIA_LOCK_NONE bool "Don't lock boot media sections" +config BOOTMEDIA_LOCK_VBOOT_RO + bool "Write-protect WP_RO region in boot media" + depends on VBOOT + help + Select this if you want to write-protect the WP_RO region as specified + in the VBOOT FMAP. You will only be able to write the regions + FW_MAIN_A/FW_MAIN_B, which are not write-protected using the internal + programmer. + The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + config BOOTMEDIA_LOCK_RO bool "Write-protect the whole boot media" help diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c index 8fb4ae9..6fa2de2 100644 --- a/src/security/lockdown/bootmedia.c +++ b/src/security/lockdown/bootmedia.c @@ -17,6 +17,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <bootstate.h> +#include <fmap.h> /* * Enable write protection on the WP_RO region of the bootmedia. @@ -47,8 +48,23 @@ "of whole bootmedia\n"); locked = true; } - } + } else if (CONFIG(BOOTMEDIA_LOCK_VBOOT_RO)) { + struct region_device dev; + if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) { + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); + } else { + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(&dev, wp_prot[i]) < 0) + continue; + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "WP_RO region\n"); + locked = true; + } + } + } if (!locked) printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Gerrit-Change-Number: 32705 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 54

Change in ...coreboot[master]: security: Add common boot media write protection
by Patrick Rudolph (Code Review) 27 Apr '20

27 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32704 Change subject: security: Add common boot media write protection ...................................................................... security: Add common boot media write protection Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Tested on Lenovo T520. The whole flash is protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/Kconfig M src/security/Makefile.inc A src/security/lockdown/Kconfig A src/security/lockdown/Makefile.inc A src/security/lockdown/bootmedia.c M src/soc/intel/common/block/fast_spi/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/finalize.c 8 files changed, 124 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32704/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..99cb054 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/lockdown/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..a74e498 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += lockdown diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig new file mode 100644 index 0000000..bb4d072 --- /dev/null +++ b/src/security/lockdown/Kconfig @@ -0,0 +1,46 @@ + +config SECURITY_BOOTMEDIA_LOCKDOWN + bool + default n + help + Platform support the locking of boot media. This can be for example + SPI controller protected regions or flash status register locking. + +if SECURITY_BOOTMEDIA_LOCKDOWN + +choice + prompt "Boot media protection" + default BOOTMEDIA_LOCK_NONE + +config BOOTMEDIA_LOCK_NONE + bool "Don't lock boot media sections" + +config BOOTMEDIA_LOCK_RO + bool "Write-protect the whole boot media" + help + Select this if you want to write-protect the whole firmware boot + media. The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the flash chip using the + internal programmer any more. + +config BOOTMEDIA_LOCK_NO_ACCESS + bool "Read- and write-protect the whole boot media" + help + Select this if you want to protect the firmware boot media against + all further accesses. On platforms that memory map a part of the + boot media the corresponding region is still readable. + The locking will take place during the chipset lockdown, which is + either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or + has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the boot media using the + internal programmer any more. + +endchoice + +endif diff --git a/src/security/lockdown/Makefile.inc b/src/security/lockdown/Makefile.inc new file mode 100644 index 0000000..c287b9b --- /dev/null +++ b/src/security/lockdown/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SECURITY_BOOTMEDIA_LOCKDOWN) += bootmedia.c diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c new file mode 100644 index 0000000..8fb4ae9 --- /dev/null +++ b/src/security/lockdown/bootmedia.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <bootstate.h> + +/* + * Enable write protection on the WP_RO region of the bootmedia. + */ +static void security_lockdown_bootmedia(void *unused) +{ + static const int wp_prot[] = {MEDIA_WP, CTRLR_WP}; + const struct region_device *rdev; + bool locked = false; + + if (CONFIG(BOOTMEDIA_LOCK_RO)) { + rdev = boot_device_ro(); + + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(rdev, wp_prot[i]) < 0) + continue; + + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "whole bootmedia\n"); + locked = true; + } + } else if (CONFIG(BOOTMEDIA_LOCK_NO_ACCESS)) { + rdev = boot_device_ro(); + if (boot_device_wp_region(rdev, CTRLR_RWP) == 0) { + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled read- and write protection" + "of whole bootmedia\n"); + locked = true; + } + } + + if (!locked) + printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); +} + +/* BS_POST_DEVICE will lock the hardware */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, security_lockdown_bootmedia, + NULL); diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 4bd1f59..ff02844 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI bool + select SECURITY_BOOTMEDIA_LOCKDOWN help Intel Processor common FAST_SPI support diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..39234a8 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select SECURITY_BOOTMEDIA_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n @@ -68,42 +69,3 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON - -if SOUTHBRIDGE_INTEL_COMMON_FINALIZE - -choice - prompt "Flash locking during chipset lockdown" - default LOCK_SPI_FLASH_NONE - -config LOCK_SPI_FLASH_NONE - bool "Don't lock flash sections" - -config LOCK_SPI_FLASH_RO - bool "Write-protect all flash sections" - help - Select this if you want to write-protect the whole firmware flash - chip. The locking will take place during the chipset lockdown, which - is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) - or has to be triggered later (e.g. by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -config LOCK_SPI_FLASH_NO_ACCESS - bool "Write-protect all flash sections and read-protect non-BIOS sections" - help - Select this if you want to protect the firmware flash against all - further accesses (with the exception of the memory mapped BIOS re- - gion which is always readable). The locking will take place during - the chipset lockdown, which is either triggered by coreboot (when - INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. - by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -endchoice - -endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 80c65bb..6f7934a 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,16 +28,6 @@ { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (CONFIG(LOCK_SPI_FLASH_RO) || - CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { - int i; - u32 lockmask = 1UL << 31; - if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) - lockmask |= 1 << 15; - for (i = 0; i < 20; i += 4) - RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; - } - /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Gerrit-Change-Number: 32704 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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