coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31419 Change subject: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size ...................................................................... src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size The default 0xc00 size of pre-CBMEM console is too small to fit whole console log from romstage. Increase the size in order to avoid log truncation when checking console with cbmem utility. The size was adjusted by compiling and running the coreboot on apu2 with SPEW loglevel. Additionally unset the SQUELCH_EARLY_SMP option to get console output between amdinitreset and amdinitearly. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31419/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6e65a6e..3c04b05 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -113,4 +113,16 @@ int default 128 +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x3000 + help + Increase this value if preram cbmem console is getting truncated + +config SQUELCH_EARLY_SMP + bool + default n + help + When selected only the BSP CPU will output to early console. + endif # BOARD_PCENGINES_APU2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 Gerrit-Change-Number: 31419 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: include vb2_sha.h when required
by Joel Kitching (Code Review) 09 May '19

09 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32454 Change subject: vboot: include vb2_sha.h when required ...................................................................... vboot: include vb2_sha.h when required Should include vb2_sha.h header when SHA library functions or constants are required. This replaces NEED_VB2_SHA_LIBRARY. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:1583820 --- M src/commonlib/cbfs.c M src/security/tpm/tspi/tspi.c M src/security/vboot/antirollback.h M util/cbfstool/Makefile.inc M util/cbfstool/cbfs_image.c 5 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32454/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 250a72a..7bb98dd 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,6 +18,7 @@ #include <commonlib/endian.h> #include <commonlib/helpers.h> #include <string.h> +#include <vb2_sha.h> #if !defined(ERROR) #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index e466eb8..4698a4d 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -22,6 +22,7 @@ #include <stdlib.h> #if CONFIG(VBOOT) #include <vb2_api.h> +#include <vb2_sha.h> #include <assert.h> #endif diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 6ea2c13..62d2e20 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -37,6 +37,7 @@ #include <types.h> #include <security/tpm/tspi.h> +#include <vb2_sha.h> struct vb2_context; enum vb2_pcr_digest; diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1787eb1..7928520 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -81,7 +81,6 @@ TOOLCPPFLAGS += -I$(objutil)/cbfstool TOOLCPPFLAGS += -I$(top)/src/commonlib/include TOOLCPPFLAGS += -include $(top)/src/commonlib/include/commonlib/compiler.h -TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include # UEFI header file support. It's not pretty, but that's what we currently diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 6ccc4f9..a7223a2 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -22,6 +22,7 @@ #include <string.h> #include <strings.h> #include <commonlib/endian.h> +#include <vb2_sha.h> #include "common.h" #include "cbfs_image.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Gerrit-Change-Number: 32454 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: communicate display requirements with vb2api_fw_phase1
by Joel Kitching (Code Review) 09 May '19

09 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32324 Change subject: vboot: communicate display requirements with vb2api_fw_phase1 ...................................................................... vboot: communicate display requirements with vb2api_fw_phase1 Input: tell vb2api_fw_phase1 if display unconditionally available Output: vb2api_fw_phase1 tells coreboot if it shall declare display as being available, based on some internal request Move the vboot_set_declares_display call into verstage_main. BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild CQ-DEPEND=CL:1564232 BRANCH=none Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628 Cq-Depend: chromium:1564232 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c M src/security/vboot/vboot_logic.c 2 files changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32324/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 85b1611..ddf0a78 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -76,14 +76,11 @@ vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* Inform vboot if the display was requested by vboot kernel phase - or enabled by dev/rec mode. */ + /* TODO(chromium:948529): Remove these two flags after downstream + vboot code longer reads them. */ if (vboot_wants_oprom() || vb2_sd->recovery_reason || - vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { - vboot_get_working_data()->flags |= VBOOT_FLAG_DISPLAY_REQUESTED; + vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) vb_sd->flags |= VBSD_OPROM_LOADED; - } - /* TODO: Remove when depthcharge no longer reads this flag. */ if (CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) vb_sd->flags |= VBSD_OPROM_MATTERS; diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2a8e619..ef6b82c 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -336,6 +336,10 @@ if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + /* Mainboard/SoC always initializes display. */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + ctx.flags |= VB2_CONTEXT_DISPLAY_REQUESTED; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(&ctx); @@ -360,6 +364,12 @@ vboot_reboot(); } + /* Is vboot declaring that display is available? If so, we should mark + it down, so that the mainboard/SoC knows to initialize display. */ + if (ctx.flags & VB2_CONTEXT_DISPLAY_REQUESTED) + vboot_get_working_data()->flags + |= VBOOT_FLAGS_DISPLAY_REQUESTED; + /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(&ctx); -- To view, visit https://review.coreboot.org/c/coreboot/+/32324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628 Gerrit-Change-Number: 32324 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/acpi: Change EC PTS/WAK dynamic loading
by Lijian Zhao (Code Review) 09 May '19

09 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32371 Change subject: soc/intel/common/acpi: Change EC PTS/WAK dynamic loading ...................................................................... soc/intel/common/acpi: Change EC PTS/WAK dynamic loading Use CondRefOf to replace config optios for EC PTS/WAK acpi method dynamic loading. BUG=N/A TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS method. Both able to build pass. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8 --- M src/mainboard/google/sarien/Kconfig M src/soc/intel/common/Kconfig M src/soc/intel/common/acpi/platform.asl 3 files changed, 11 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32371/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9d658fa..42b3a4f 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -16,7 +16,6 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index b5caf40..c945514 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -51,13 +51,6 @@ bool default n -config SOC_INTEL_COMMON_ACPI_EC_PTS_WAK - bool - default n - help - Set this option to have the platform level _PTS/_WAK methods call - methods provided by the Embedded Controller. - config SOC_INTEL_COMMON_NHLT bool default n diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index bdc0d5c..12a41e7 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -17,6 +17,9 @@ #include <include/console/post_codes.h> +External(\_SB.PCI0.LPCB.EC0.PTS, MethodObj) +External(\_SB.PCI0.LPCB.EC0.WAK, MethodObj) + /* Port 80 POST */ OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) @@ -34,10 +37,10 @@ { Store (POST_OS_ENTER_PTS, DBG0) -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _PTS handler */ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) -#endif + If (CondRefOf(\_SB.PCI0.LPCB.EC0.PTS)) { + /* Call EC _PTS handler */ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + } } /* The _WAK method is called on system wakeup */ @@ -46,10 +49,10 @@ { Store (POST_OS_ENTER_WAKE, DBG0) -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _WAK handler */ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -#endif + If (CondRefOf(\_SB.PCI0.LPCB.EC0.WAK)) { + /* Call EC _WAK handler */ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) + } Return (Package(){0,0}) } -- To view, visit https://review.coreboot.org/c/coreboot/+/32371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8 Gerrit-Change-Number: 32371 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add Kohaku board
by Shelley Chen (Code Review) 08 May '19

08 May '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32161 Change subject: mb/google/hatch: Add Kohaku board ...................................................................... mb/google/hatch: Add Kohaku board Adding Kohaku as a variant of hatch. BUG=b:129706980 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_KOHAKU is built as well. Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32161/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b551065..dd9abe5 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -59,6 +59,7 @@ depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL + default "KOHAKU TEST CB61" if BOARD_GOOGLE_HATCH_WHL config MAINBOARD_DIR string @@ -72,6 +73,7 @@ string default "Hatch" if BOARD_GOOGLE_HATCH default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL + default "Kohaku" if BOARD_GOOGLE_KOHAKU config MAINBOARD_VENDOR string @@ -93,6 +95,7 @@ string default "hatch" if BOARD_GOOGLE_HATCH default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL + default "kohaku" if BOARD_GOOGLE_KOHAKU config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e98bcae..edfa8e7 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -9,3 +9,8 @@ bool "-> Hatch_whl" select BOARD_GOOGLE_BASEBOARD_HATCH select SOC_INTEL_WHISKEYLAKE + +config BOARD_GOOGLE_KOHAKU + bool "-> Kohaku" + select BOARD_GOOGLE_BASEBOARD_HATCH + select SOC_INTEL_COMETLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/32161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0 Gerrit-Change-Number: 32161 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t520: Fix devicetree
by Patrick Rudolph (Code Review) 08 May '19

08 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32317 Change subject: mb/lenovo/t520: Fix devicetree ...................................................................... mb/lenovo/t520: Fix devicetree Disable unused PCI devices. Reduces idle power by around 0.5Watt. Tested on Lenovo T520. Change-Id: I6990dc5810084261b75d2a327b6a103be44fd4cc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32317/1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..b3e1723 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -86,6 +86,8 @@ device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on # dummy @@ -165,6 +167,8 @@ device i2c 5f on end end end # SMBus + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/32317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6990dc5810084261b75d2a327b6a103be44fd4cc Gerrit-Change-Number: 32317 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Add panel config data for display
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31590 Change subject: google/kukui: Add panel config data for display ...................................................................... google/kukui: Add panel config data for display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31590/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 950dca4..bf9bd02 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -15,9 +15,12 @@ #include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <edid.h> +#include <gpio.h> #include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> @@ -42,13 +45,66 @@ setup_usb_host(); } +/* Setup backlight control pins as output pin and power-off by default */ +static void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +static void configure_display(void) +{ + /* board from p0 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); +} + +static const struct edid kukui_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +struct lcm_init_table lcm_init_cmd[] = { + {INIT_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON}}, + {DELAY_CMD, 120, {}}, +}; + + static void display_startup(void) { + int ret = 0; + u32 mipi_dsi_flags; struct edid edid; + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } mtk_ddp_mode_set(&edid); @@ -62,6 +118,8 @@ mtcmos_display_power_on(); mtcmos_protect_display_bus(); + configure_backlight(); + configure_display(); display_startup(); } else { printk(BIOS_INFO, "Skipping display init.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Gerrit-Change-Number: 31590 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: mediaek/mt8183: add panel driver for kukui p2
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32097 Change subject: WIP: mediaek/mt8183: add panel driver for kukui p2 ...................................................................... WIP: mediaek/mt8183: add panel driver for kukui p2 BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/dsi.c 2 files changed, 222 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32097/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index bf9bd02..541485a 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boardid.h> #include <bootmode.h> #include <console/console.h> #include <delay.h> @@ -55,11 +56,72 @@ static void configure_display(void) { - /* board from p0 */ - gpio_output(GPIO(LCM_RST), 0); - udelay(100); - gpio_output(GPIO(LCM_RST), 1); - mdelay(20); + + printk(BIOS_ERR, "board_id() = %d\n", board_id()); + + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + printk(BIOS_ERR, "board from p2\n"); + + gpio_output(GPIO(LCM_RST), 0); + gpio_output(GPIO(BPI_BUS3), 0); + gpio_output(GPIO(MISC_BSI_CK_3), 0); + gpio_output(GPIO(PERIPHERAL_EN9), 0); + gpio_output(GPIO(SIM2_SRST), 0); + gpio_output(GPIO(SIM2_SIO), 0); + gpio_output(GPIO(BPI_OLAT1), 0); + gpio_output(GPIO(SIM2_SCLK), 0); + gpio_set_pull(GPIO(LCM_RST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_BUS3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(MISC_BSI_CK_3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(PERIPHERAL_EN9), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SRST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SIO), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_OLAT1), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SCLK), GPIO_PULL_ENABLE, GPIO_PULL_UP); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + + gpio_output(GPIO(MISC_BSI_CK_3), 1); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + gpio_output(GPIO(BPI_OLAT1), 1); + gpio_output(GPIO(SIM2_SCLK), 1); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + gpio_output(GPIO(BPI_BUS3), 1); + mdelay(20); + mdelay(20); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox350] = 0x%x\n", read32((void *)GPIO_BASE + 0x350)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox10] = 0x%x\n", read32((void *)GPIO_BASE + 0x10)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox110] = 0x%x\n", read32((void *)GPIO_BASE + 0x110)); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox390] = 0x%x\n", read32((void *)GPIO_BASE + 0x390)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox20] = 0x%x\n", read32((void *)GPIO_BASE + 0x20)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox120] = 0x%x\n", read32((void *)GPIO_BASE + 0x120)); + } } static const struct edid kukui_innolux_edid = { @@ -84,6 +146,76 @@ {DELAY_CMD, 120, {}}, }; +static const struct edid kukui_p097pfg_ssd2858_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1536x2048@60Hz", + .pixel_clock = 229000, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1536, .hbl = 160, .hso = 80, .hspw = 26, .hborder = 0, + .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 196, + }, +}; + +struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = { + /* SSD2858 config */ + {INIT_CMD, 2, {0xff, 0x00}}, + /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2}}, MULT=0x49 + * 27 Mhz => 985.5 Mhz */ + {INIT_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49}}, + /* MTXDIV=1, SYSDIV=3 (=> 4) */ + {INIT_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03}}, + /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1 + * MRXEE=1 */ + {INIT_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f}}, + {INIT_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d}}, + {INIT_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00}}, + +// {INIT_CMD, 1, {0x11}}, +// {DELAY_CMD, 120, {}}, + + {INIT_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x04, 0x45}}, + {INIT_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00}}, + {INIT_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04}}, + /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */ + {INIT_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49}}, + {INIT_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00}}, + /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */ + {INIT_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08}}, + {INIT_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06}}, + /* DSI0 enable (default: probably not needed) */ + {INIT_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f}}, + /* DSI1 enable */ + {INIT_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f}}, + + /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */ + {INIT_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18}}, + /* VACT= 0x800 (2048}}, VFP= 0x14, HFP=0x50 */ + {INIT_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50}}, + /* HACT=0x300 (768) */ + {INIT_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00}}, + {INIT_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00}}, + + /* Take panel out of sleep. */ + {INIT_CMD, 2, {0xff, 0x01}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, + {INIT_CMD, 2, {0xff, 0x00}}, + + //{INIT_CMD, 6, {0x60, 0x14, 0x41, 0x00, 0x81, 0x02}}, + //{INIT_CMD, 6, {0x60, 0x14, 0xc1, 0x00, 0x81, 0x0A}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, +}; static void display_startup(void) { @@ -91,16 +223,30 @@ u32 mipi_dsi_flags; struct edid edid; - edid = kukui_innolux_edid; - mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM; + if (board_id() < 2) { + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + } else { + edid = kukui_p097pfg_ssd2858_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + } edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, - false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (board_id() < 2) + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + else { + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_p097pfg_ssd2858_init_cmd, sizeof(lcm_p097pfg_ssd2858_init_cmd) / sizeof(struct lcm_init_table)); + printk(BIOS_ERR, "mtk_dsi_init from p2\n"); + } + if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index f96d847..316d92d 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <boardid.h> #include <console/console.h> #include <delay.h> #include <soc/addressmap.h> @@ -97,6 +98,11 @@ printk(BIOS_ERR, "data_rate: %u bps\n", data_rate); + if (board_id() == 2) + data_rate = 1420000000; + + printk(BIOS_ERR, "board_id() == 2 data_rate: %u bps\n", data_rate); + if (data_rate >= 2000000000) { txdiv = 1; txdiv0 = 0; @@ -169,26 +175,28 @@ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | phy_timing->clk_hs_exit << 16; - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + if (board_id() < 2) { + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + } else { + dsi_write32(&dsi->dsi_phy_timecon0, 0x0e1c070d); + dsi_write32(&dsi->dsi_phy_timecon1, 0x1a411334); + dsi_write32(&dsi->dsi_phy_timecon2, 0x11420100); + dsi_write32(&dsi->dsi_phy_timecon3, 0x001a180a); + } } static void mtk_dsi_reset(void) { - dsi_setbits_le32(&dsi->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 0); } static void mtk_dsi_clk_hs_mode_enable(void) { - dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); + dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -312,7 +320,7 @@ edid->mode.hborder) * bpp - 10; else hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; + edid->mode.hborder) * bpp - 8; hsync_active_byte = edid->mode.hspw * bpp - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; @@ -348,8 +356,8 @@ static void mtk_dsi_start(void) { - dsi_write32(&dsi->dsi_start, 0); - dsi_write32(&dsi->dsi_start, 1); + dsi_clrbits_le32(&dsi->dsi_start, 1); + dsi_setbits_le32(&dsi->dsi_start, 1); } static void mtk_dsi_cmdq(u8 *data, u8 len) @@ -359,6 +367,15 @@ u8 cmdq_size; u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0; + + while(read32(&dsi->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "mtk_dsi_cmdq wait dsi no busy\n"); + mdelay(20); + } + + printk(BIOS_ERR, "mtk_dsi_cmdq dsi no busy\n"); + dsi_write32(&dsi->dsi_intsta, 0); + switch (len) { case 0: return; @@ -393,14 +410,17 @@ reg_val = (type << 8) | config; } - for (i = 0; i < len; i++) - dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)), + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + ((cmdq_off + i) & (0xfffffffc)), (0xff << (((i + cmdq_off) & 3) * 8)), tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - dsi_write32(&dsi->dsi_intsta, 0); mtk_dsi_start(); stopwatch_init_usecs_expire(&sw, 400); @@ -414,7 +434,12 @@ if (!(intsta_0 & CMD_DONE_INT_FLAG)) printk(BIOS_ERR, "dsi DONE INT Timeout\n"); - dsi_write32(&dsi->dsi_start, 0); + for (i = 0x200; i < 0x210; i = i + 4) + printk(BIOS_ERR, "dump_dsi_reg : reg[0x%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x60] = 0x%x\n", read32((void *)DSI_BASE + 0x60)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x00] = 0x%x\n", read32((void *)DSI_BASE)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x14] = 0x%x\n", read32((void *)DSI_BASE + 0x14)); } static void push_table(struct lcm_init_table *init_cmd, u32 count) @@ -426,7 +451,17 @@ switch (cmd) { case DELAY_CMD: - mdelay(init_cmd[i].cmd); + if (init_cmd[i].cmd > 20) { + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + } else { + mdelay(20); + } + printk(BIOS_ERR, "delay : init_cmd[%d].len = 0x%x\n", i, init_cmd[i].len); break; case END_OF_TABLE: @@ -434,6 +469,7 @@ case INIT_CMD: default: + printk(BIOS_ERR, "init_cmd : init_cmd[%d].data[0] = 0x%x\n", i, init_cmd[i].data[0]); mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len); break; } @@ -443,7 +479,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, const struct edid *edid, struct lcm_init_table *init_cmd, u32 count) { - int data_rate; + int data_rate, i; struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); @@ -453,18 +489,23 @@ if (data_rate < 0) return -1; - mtk_dsi_reset(); dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_reset(); mtk_dsi_phy_timconfig(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, edid); mtk_dsi_clk_hs_mode_enable(); - mtk_dsi_set_mode(0); push_table(init_cmd, count); mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); + dsi_write32((void *)DSI_BASE + 0x178, 0x00ff0000); + dsi_write32((void *)DSI_BASE + 0x17c, 0x00200040); + + for (i = 0; i < 0x208; i = i + 4) { + printk(BIOS_ERR, "dump_dsi_reg : reg[ox%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + } + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Gerrit-Change-Number: 32097 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t520: Add SMBIOS type 9 fields
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32309 Change subject: mb/lenovo/t520: Add SMBIOS type 9 fields ...................................................................... mb/lenovo/t520: Add SMBIOS type 9 fields Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32309/1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..88495fb 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -78,9 +78,17 @@ device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on + slot_designation "Below keyboard" + slot_type "21" + slot_data_width "8" + end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + slot_designation "Right side" + slot_type "7" + slot_data_width "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 -- To view, visit https://review.coreboot.org/c/coreboot/+/32309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2 Gerrit-Change-Number: 32309 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: [WIP]smbios: Walk over PCI devicetree to fill type 9
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32308 Change subject: [WIP]smbios: Walk over PCI devicetree to fill type 9 ...................................................................... [WIP]smbios: Walk over PCI devicetree to fill type 9 Use the devicetree values for type 9 slots. Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32308/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 10feb15..c565462 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -996,6 +996,19 @@ dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } + if (dev->path.type == DEVICE_PATH_PCI) { + if (dev->smbios_slot_type || + dev->smbios_slot_data_width || + dev->smbios_slot_designation) { + len += smbios_write_type9(current, handle, + dev->smbios_slot_designation, + dev->smbios_slot_type, + 1, + 0, + dev->bus->secondary, + dev->path.pci.devfn); + } + } } return len; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Gerrit-Change-Number: 32308 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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