coreboot-gerrit April 2019

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Change in ...coreboot[master]: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31512 Change subject: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS ...................................................................... AGESA f12 f14 vendorcofe: Clean up extra CFLAGS Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc 2 files changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31512/1 diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index dbea9c3..9bc3c26 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index bf1051c..da79a39 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### -- To view, visit https://review.coreboot.org/c/coreboot/+/31512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Gerrit-Change-Number: 31512 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: AGESA: Move heap_status_name() implementation
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31511 Change subject: AGESA: Move heap_status_name() implementation ...................................................................... AGESA: Move heap_status_name() implementation Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h M src/vendorcode/amd/agesa/common/Makefile.inc A src/vendorcode/amd/agesa/common/debug_util.c A src/vendorcode/amd/agesa/common/debug_util.h M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc 10 files changed, 34 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31511/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 3231d4f..b80c220 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -21,8 +21,6 @@ #include <AGESA.h> #include <AMD.h> -#include <heapManager.h> - static const char undefined[] = "undefined"; /* Match order of enum AGESA_STRUCT_NAME. */ @@ -34,11 +32,6 @@ "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; -/* heapManager.h */ -static const char *HeapStatusStr[] = { - "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" -}; - /* This function has to match with enumeration of AGESA_STRUCT_NAME defined * inside AMD.h header file. Unfortunately those are different across * different vendorcode subtrees. @@ -64,15 +57,6 @@ return AgesaFunctionNameStr[index]; } -const char *heap_status_name(int status) -{ - if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) - return undefined; - - int index = status - HEAP_DO_NOT_EXIST_YET; - return HeapStatusStr[index]; -} - /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 15ea211..672bca1 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,6 +27,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> +#include <debug_util.h> #include <AMD.h> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 43b205a..c7d654d 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -24,7 +24,6 @@ /* eventlog */ const char *agesa_struct_name(int state); -const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 78dd4fc..2479694 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesa-entry.c ramstage-y += agesa-entry.c +libagesa-y += debug_util.c libagesa-y += amdlib.c # Do not optimise performance-critical low-level IO for size with -Os, diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000..29d0841 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include <AGESA.h> +#include <AMD.h> +#include <heapManager.h> + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000..a8d9a33 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index f925ccb..dbea9c3 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -46,7 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ad2d2dc..bf1051c 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 57350d9..1c5dc18 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 3115c4d..c423cf2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h -- To view, visit https://review.coreboot.org/c/coreboot/+/31511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Gerrit-Change-Number: 31511 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/google/sarien: Enable UCSI device
by Duncan Laurie (Code Review) 25 May '19

25 May '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32358 Change subject: mb/google/sarien: Enable UCSI device ...................................................................... mb/google/sarien: Enable UCSI device Enable the UCSI driver in kconfig and add the device to the mainboard devicetree with the specified path for the UCSI device that is provided by the Wilco EC driver. This was tested on a Sarien device with the linux kernel: > cat /sys/class/typec/port0/usb_typec_revision 1.1 > cat /sys/class/typec/port0/port_type [dual] source sink Change-Id: I0fe33a8b63e04de883579a80aeb896b880da147a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32358/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9d658fa..6131149 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -7,6 +7,7 @@ select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI + select DRIVERS_USB_UCSI select EC_GOOGLE_WILCO select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9ecbf00..042d4f5 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -358,6 +358,10 @@ chip ec/google/wilco device pnp 0c09.0 on end end + chip drivers/usb/ucsi + register "path" = ""\\_SB.PCI0.LPCB.EC0.UCSI"" + device pnp 0ca0.0 on end + end end # LPC/eSPI device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 625655b..7b9f83e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -391,6 +391,10 @@ chip ec/google/wilco device pnp 0c09.0 on end end + chip drivers/usb/ucsi + register "path" = ""\\_SB.PCI0.LPCB.EC0.UCSI"" + device pnp 0ca0.0 on end + end end # LPC/eSPI device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/32358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe33a8b63e04de883579a80aeb896b880da147a Gerrit-Change-Number: 32358 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: AGESA binaryPI: Sync STRUCT_NAME definitions
by Kyösti Mälkki (Code Review) 23 May '19

23 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31510 Change subject: AGESA binaryPI: Sync STRUCT_NAME definitions ...................................................................... AGESA binaryPI: Sync STRUCT_NAME definitions While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/vendorcode/amd/agesa/f12/AMD.h M src/vendorcode/amd/agesa/f14/AMD.h M src/vendorcode/amd/agesa/f15tn/AMD.h M src/vendorcode/amd/agesa/f16kb/AMD.h M src/vendorcode/amd/pi/00630F01/AMD.h M src/vendorcode/amd/pi/00660F01/AMD.h M src/vendorcode/amd/pi/00730F01/AMD.h 8 files changed, 31 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31510/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index cc65652..3231d4f 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -29,8 +29,9 @@ static const char *AgesaFunctionNameStr[] = { "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", + "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; /* heapManager.h */ diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h index 179c3f5..31c0b34 100644 --- a/src/vendorcode/amd/agesa/f12/AMD.h +++ b/src/vendorcode/amd/agesa/f12/AMD.h @@ -148,7 +148,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h index 9d443be..c1cfaa1 100644 --- a/src/vendorcode/amd/agesa/f14/AMD.h +++ b/src/vendorcode/amd/agesa/f14/AMD.h @@ -147,7 +147,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f15tn/AMD.h b/src/vendorcode/amd/agesa/f15tn/AMD.h index 31d38db..27326ec 100644 --- a/src/vendorcode/amd/agesa/f15tn/AMD.h +++ b/src/vendorcode/amd/agesa/f15tn/AMD.h @@ -144,7 +144,10 @@ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f16kb/AMD.h b/src/vendorcode/amd/agesa/f16kb/AMD.h index bfce993..83d538f 100644 --- a/src/vendorcode/amd/agesa/f16kb/AMD.h +++ b/src/vendorcode/amd/agesa/f16kb/AMD.h @@ -143,7 +143,9 @@ AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE ///< AmdGet2DDataEye general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h index 68f7c32..f70b128 100644 --- a/src/vendorcode/amd/pi/00630F01/AMD.h +++ b/src/vendorcode/amd/pi/00630F01/AMD.h @@ -149,6 +149,8 @@ AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index aa68204..54abf80 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -126,6 +126,11 @@ AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH; +/* When AMD rolled out CarrizoPI, they made a bad choice of removing + * an entry from the middle of the enumeration list. + */ +#define AMD_S3_SAVE_REMOVED + /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS @@ -140,6 +145,10 @@ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle +#if 0 + /* This was removed, shifting everything else up.*/ + AMD_S3_SAVE = 0x0002C000, +#endif AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h index 1b6fdb2..13fc29a 100644 --- a/src/vendorcode/amd/pi/00730F01/AMD.h +++ b/src/vendorcode/amd/pi/00730F01/AMD.h @@ -148,6 +148,9 @@ AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE = 0x00035000, /* reserved */ + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, -- To view, visit https://review.coreboot.org/c/coreboot/+/31510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Gerrit-Change-Number: 31510 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in ...coreboot[master]: lib/bootblock: Sanitize CMOS after bootblock_*_early_init()
by Thomas Heijligen (Code Review) 23 May '19

23 May '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31349 to review the following change. Change subject: lib/bootblock: Sanitize CMOS after bootblock_*_early_init() ...................................................................... lib/bootblock: Sanitize CMOS after bootblock_*_early_init() CMOS isn't used that early, but the chipset initialization may be required to access it. In one instance, Intel Apollo Lake, the sanitize_cmos() function seems to hang if called before bootblock_soc_early_init(). The missing step is fast_spi_early_init(). But even without, one might expect sanitize_cmos() to return eventually (it didn't within about 20min). Change-Id: I6e1a029e4be7e109be43a3dad944bd7e05ea1f02 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/lib/bootblock.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31349/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index f2ada52..6b9ecbf 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -41,12 +41,12 @@ timestamps[i].entry_stamp); } - sanitize_cmos(); - cmos_post_init(); - bootblock_soc_early_init(); bootblock_mainboard_early_init(); + sanitize_cmos(); + cmos_post_init(); + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e1a029e4be7e109be43a3dad944bd7e05ea1f02 Gerrit-Change-Number: 31349 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

8 9

Change in ...coreboot[master]: mb/up/squared: Add mainboard
by Felix Singer (Code Review) 22 May '19

22 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31378 Change subject: mb/up/squared: Add mainboard ...................................................................... mb/up/squared: Add mainboard Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A src/mainboard/up/Kconfig A src/mainboard/up/Kconfig.name A src/mainboard/up/squared/Kconfig A src/mainboard/up/squared/Kconfig.name A src/mainboard/up/squared/acpi_tables.c A src/mainboard/up/squared/devicetree.cb A src/mainboard/up/squared/dsdt.asl 7 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31378/1 diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig new file mode 100644 index 0000000..84277de --- /dev/null +++ b/src/mainboard/up/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_UP + +choice + prompt "Mainboard model" + +source "src/mainboard/up/*/Kconfig.name" + +endchoice + +source "src/mainboard/up/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Up" + +endif diff --git a/src/mainboard/up/Kconfig.name b/src/mainboard/up/Kconfig.name new file mode 100644 index 0000000..56be3e8 --- /dev/null +++ b/src/mainboard/up/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UP + bool "Up" diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig new file mode 100644 index 0000000..7271753 --- /dev/null +++ b/src/mainboard/up/squared/Kconfig @@ -0,0 +1,53 @@ +if BOARD_UP_SQUARED + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + +config MAINBOARD_DIR + string + default "up/squared" + +config MAINBOARD_VENDOR + string + default "Up" + +config MAINBOARD_PART_NUMBER + string + default "Squared" + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config VGA_BIOS_ID + string + default "8086,5a85" + +config PXE_ROM_ID + string + default "10ec,8168" + +config MAX_CPUS + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config UART_FOR_CONSOLE + default 2 + +endif diff --git a/src/mainboard/up/squared/Kconfig.name b/src/mainboard/up/squared/Kconfig.name new file mode 100644 index 0000000..4d6a59b --- /dev/null +++ b/src/mainboard/up/squared/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UP_SQUARED + bool "Squared" diff --git a/src/mainboard/up/squared/acpi_tables.c b/src/mainboard/up/squared/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/up/squared/acpi_tables.c diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb new file mode 100644 index 0000000..5d91e38 --- /dev/null +++ b/src/mainboard/up/squared/devicetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/apollolake + + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 off end # - Gen + device pci 03.0 off end # - Iunit + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - TXE + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.1 on end # - PCIe-A 1 + device pci 13.2 on end # - PCIe-A 2 + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 1 + device pci 14.1 on end # - PCIe-B 2 + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - HSUART 0 + device pci 18.1 on end # - HSUART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl new file mode 100644 index 0000000..48b24b9 --- /dev/null +++ b/src/mainboard/up/squared/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Gerrit-Change-Number: 31378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Dump ME f/w version and status information.
by Tim Wawrzynczak (Code Review) 22 May '19

22 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32527 Change subject: soc/intel/cannonlake: Dump ME f/w version and status information. ...................................................................... soc/intel/cannonlake: Dump ME f/w version and status information. At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints what appears to be correct information on Kled (hatch_whl). Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/me.c 2 files changed, 309 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32527/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 7ad0c7c..1328944 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c new file mode 100644 index 0000000..59ba879 --- /dev/null +++ b/src/soc/intel/cannonlake/me.c @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <bootstate.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/pci.h> +#include <intelblocks/cse.h> +#include <soc/pci_devs.h> +#include <stdint.h> +#include <stdlib.h> + +/* Miscellaneous constants */ +enum +{ + MKHI_GEN_GROUP_ID = 0xFF, + MKHI_GET_FW_VERSION = 0x02, + ME_OPMODE_NORMAL = 0x00, + ME_WSTATE_NORMAL = 0x05, + BIOS_HOST_ADD = 0x00, + HECI_MKHI_ADD = 0x07, +}; + +/* HFSTS register offsets in PCI config space */ +enum +{ + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + +/* Host Firmware Status Register 1 */ +union hfsts1 +{ + uint32_t raw; + struct { + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t fw_upd_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reset_count : 4; + uint32_t boot_options : 1; + uint32_t rsvd0 : 1; + uint32_t bist_state : 1; + uint32_t bist_reset_req : 1; + uint32_t power_source : 2; + uint32_t reserved1 : 1; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union hfsts2 +{ + uint32_t raw; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 3 */ +union hfsts3 +{ + uint32_t raw; +}; + +/* Host Firmware Status Register 4 */ +union hfsts4 +{ + uint32_t raw; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test: 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union hfsts5 +{ + uint32_t raw; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union hfsts6 +{ + uint32_t raw; + struct { + uint32_t force_boot_guard_acm: 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy: 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + +/* + * From reading the documentation, this should work for both WHL and CML + * platforms + */ +static void print_me_version(void *unused) +{ + (void)unused; + + struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; + } __packed; + + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + union hfsts1 hfsts1; + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || + (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) + goto fail; + + heci_reset(); + + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, + HECI_MKHI_ADD)) + goto fail; + + if (!heci_receive(&resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); + +static void dump_me_status(void *unused) +{ + + union hfsts1 hfsts1; + union hfsts2 hfsts2; + union hfsts3 hfsts3; + union hfsts4 hfsts4; + union hfsts5 hfsts5; + union hfsts6 hfsts6; + + (void)unused; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); + hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); + hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.raw); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.raw); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.raw); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.raw); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.raw); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.raw); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.fw_upd_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, dump_me_status, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/32527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Gerrit-Change-Number: 32527 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

10 45

Change in ...coreboot[master]: soc/amd/common: Identify AGESA call pattern
by Kyösti Mälkki (Code Review) 22 May '19

22 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31488 Change subject: soc/amd/common: Identify AGESA call pattern ...................................................................... soc/amd/common: Identify AGESA call pattern The entry to AGESA always follows pattern: amd_create_struct() amd_dispatch() amd_release_struct() Separate the create/release_struct calls from the more relevant entry point details. Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 46 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31488/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 1c6c0aa..821535d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -66,10 +66,9 @@ return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); } -static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, +static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func, void *buf, size_t len) { - AMD_CONFIG_PARAMS *StdHeader; AGESA_STATUS status; /* Should clone entire StdHeader here. */ @@ -78,8 +77,8 @@ /* If we provide the buffer, API expects it to have StdHeader already filled. */ - if (buf != NULL && len >= sizeof(*StdHeader)) { - memcpy(buf, &aip->StdHeader, sizeof(*StdHeader)); + if (buf != NULL && len >= sizeof(aip->StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(aip->StdHeader)); aip->AllocationMethod = ByHost; aip->NewStructPtr = buf; aip->NewStructSize = len; @@ -102,9 +101,7 @@ if (!aip->NewStructPtr) die("No AGESA structure created"); - StdHeader = aip->NewStructPtr; - StdHeader->Func = aip->AgesaFunctionName; - return StdHeader; + return status; } static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) @@ -112,14 +109,9 @@ return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); } -static AGESA_STATUS amd_init_reset(void) +static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams) { AGESA_STATUS status; - AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RESET_PARAMS *ResetParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESET, &_ResetParams, sizeof(AMD_RESET_PARAMS)); SetFchResetParams(&ResetParams->FchInterface); @@ -127,17 +119,12 @@ status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - amd_release_struct(&AmdParamStruct); return status; } -static AGESA_STATUS amd_init_early(void) +static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_EARLY_PARAMS *EarlyParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_EARLY, NULL, 0); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); @@ -146,8 +133,6 @@ status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -184,13 +169,9 @@ uma_size / MiB, uma_start); } -static AGESA_STATUS amd_init_post(void) +static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_POST_PARAMS *PostParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_POST, NULL, 0); PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -230,18 +211,12 @@ print_init_post_settings(PostParams); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_env(void) +static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_ENV_PARAMS *EnvParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_ENV, NULL, 0); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); @@ -250,8 +225,6 @@ status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -281,17 +254,13 @@ } } -static AGESA_STATUS amd_init_mid(void) +static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_MID, NULL, 0); - SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); @@ -299,22 +268,12 @@ status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_late(void) +static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* - * NOTE: if not call amdcreatestruct, the initializer - * (AmdInitLateInitializer) would not be called. - */ - AMD_LATE_PARAMS *LateParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_LATE, NULL, 0); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -343,17 +302,12 @@ AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - amd_release_struct(&AmdParamStruct); return Status; } -static AGESA_STATUS amd_init_rtb(void) +static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RTB_PARAMS *RtbParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RTB, NULL, 0); timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); @@ -365,20 +319,14 @@ RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_init_resume(void) +static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESUME, NULL, 0); - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; @@ -386,23 +334,16 @@ status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_s3late_restore(void) +static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = amd_create_struct(&AmdParamStruct, - AMD_S3LATE_RESTORE, &_S3LateParams, sizeof(AMD_S3LATE_PARAMS)); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -410,21 +351,14 @@ Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_s3final_restore(void) +static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = amd_create_struct(&AmdParamStruct, - AMD_S3FINAL_RESTORE, &_S3FinalParams, sizeof(AMD_S3FINAL_PARAMS)); - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -432,22 +366,22 @@ Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_RESET: - return amd_init_reset(); + return amd_init_reset(Params); case AMD_INIT_EARLY: - return amd_init_early(); + return amd_init_early(Params); case AMD_INIT_POST: - return amd_init_post(); + return amd_init_post(Params); case AMD_INIT_RESUME: - return amd_init_resume(); + return amd_init_resume(Params); default: return AGESA_UNSUPPORTED; } @@ -455,22 +389,25 @@ static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_ENV: - return amd_init_env(); + return amd_init_env(Params); case AMD_INIT_MID: - return amd_init_mid(); + return amd_init_mid(Params); case AMD_INIT_LATE: - return amd_init_late(); + return amd_init_late(Params); case AMD_INIT_RTB: - return amd_init_rtb(); + return amd_init_rtb(Params); case AMD_S3LATE_RESTORE: - return amd_s3late_restore(); + return amd_s3late_restore(Params); case AMD_S3FINAL_RESTORE: - return amd_s3final_restore(); + return amd_s3final_restore(Params); default: return AGESA_UNSUPPORTED; } + } AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) @@ -478,7 +415,23 @@ AGESA_STATUS status = AGESA_UNSUPPORTED; AMD_CONFIG_PARAMS template = {}; AMD_CONFIG_PARAMS *StdHeader = &template; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; + union { + AMD_RESET_PARAMS ResetParams; + AMD_S3LATE_PARAMS S3LateParams; + AMD_S3FINAL_PARAMS S3FinalParams; + } sp; + if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || + (func == AMD_S3FINAL_RESTORE)) { + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); + } else { + amd_create_struct(aip, func, NULL, 0); + } + + StdHeader = aip->NewStructPtr; StdHeader->Func = func; if (ENV_ROMSTAGE) @@ -486,5 +439,6 @@ if (ENV_RAMSTAGE) status = ramstage_dispatch(StdHeader); + amd_release_struct(aip); return status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1 Gerrit-Change-Number: 31488 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: [WIP]soc/fsp1.1: Implement postcar stage
by Arthur Heymans (Code Review) 21 May '19

21 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30686 Change subject: [WIP]soc/fsp1.1: Implement postcar stage ...................................................................... [WIP]soc/fsp1.1: Implement postcar stage TODO cleanup, test Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/romstage.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/skylake/romstage/car_stage.S 7 files changed, 86 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30686/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 69fa8df..53a993c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,6 +18,8 @@ bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select POSTCAR_STAGE + select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package? diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4..62dc663 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c @@ -45,6 +44,9 @@ cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc +postcar-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += after_raminit.S +postcar-y += stage_cache.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cdc8e93..05c4425 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,151 +20,10 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -/* - * This is the common entry point after DRAM has been initialized. - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* chipset_teardown_car() is expected to disable cache-as-ram. */ - call chipset_teardown_car - -#else -.extern fih_car +.text +.global chipset_teardown_car +chipset_teardown_car: post_code(POST_FSP_TEMP_RAM_EXIT) - - /* Calculate TempRamExit entry into FSP */ - movl fih_car, %ebp - mov 0x40(%ebp), %eax - add 0x1c(%ebp), %eax - - /* Build the call frame */ - pushl $0 - - /* Call TempRamExit */ - call *%eax - add $4, %esp - cmp $0, %eax - jz 1f - /* - * Failures for post code BC - failed in TempRamExit - * - * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. - */ - movb $0xBC, %ah - jmp .Lhlt -1: -#endif - /* Display the MTRRs */ - call display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - push %esp - call soc_set_mtrrs - - /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ - movl %eax, %esp -#else - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - call soc_enable_mtrrs -#else - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call after_cache_as_ram + pop %ebx + jmp *%ebx diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 934ae67..2a4e47c 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -140,11 +140,6 @@ /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main -/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after RAM init. */ -#if !ENV_VERSTAGE -#include "after_raminit.S" -#endif movb $0x69, %ah jmp .Lhlt diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index c1bcd84..d362b44 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -30,6 +30,7 @@ #include <ec/google/chromeec/ec_commands.h> #include <elog.h> #include <fsp/romstage.h> +#include <fsp/memmap.h> #include <mrc_cache.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -39,9 +40,77 @@ #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + size_t alignment; + uint32_t aligned_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + postcar_frame_add_mtrr(&pcf, aligned_ram, aligned_ram + alignment, MTRR_TYPE_WRBACK); + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + uintptr_t smm_base; + size_t smm_size; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, alignment, MTRR_TYPE_WRBACK); +#endif + + run_postcar_phase(&pcf); +} + asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { - void *top_of_stack; struct pei_data pei_data; struct romstage_params params = { .pei_data = &pei_data, @@ -78,11 +147,9 @@ soc_after_ram_init(&params); post_code(0x38); - top_of_stack = setup_stack_and_mtrrs(); + platform_enter_postcar(); - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - return top_of_stack; + return NULL; } void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index fabbc2b..3296331 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -16,6 +16,9 @@ romstage-y += pmutil.c romstage-y += tsc_freq.c +postcar-y += memmap.c +postcar-y += iosf.c + ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 9482456..1c5857b 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -20,9 +20,8 @@ .global car_stage_entry car_stage_entry: call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S" - + /* we don't return here */ movb $0x69, %ah jmp .Lhlt -- To view, visit https://review.coreboot.org/c/coreboot/+/30686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Gerrit-Change-Number: 30686 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

9 29

Change in ...coreboot[master]: soc/amd/common: Refactor AmdCreateStruct() use
by Kyösti Mälkki (Code Review) 21 May '19

21 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31486 Change subject: soc/amd/common: Refactor AmdCreateStruct() use ...................................................................... soc/amd/common: Refactor AmdCreateStruct() use AmdCreateStruct() and AmdReleaseStruct() are equally bad when it comes to lack of correct function declarations for definitions found in vendorcode binaryPI/AGESA.c. Replace these with calls that go through the common module_dispatch() functions. Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 70 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31486/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index f09fc5d..1c6c0aa 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -66,41 +66,60 @@ return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); } -static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) +static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, + AGESA_STRUCT_NAME func, void *buf, size_t len) { AMD_CONFIG_PARAMS *StdHeader; + AGESA_STATUS status; /* Should clone entire StdHeader here. */ - interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = &GetBiosCallout; - AGESA_STATUS status = AmdCreateStruct(interface_struct); + /* If we provide the buffer, API expects it to have + StdHeader already filled. */ + if (buf != NULL && len >= sizeof(*StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(*StdHeader)); + aip->AllocationMethod = ByHost; + aip->NewStructPtr = buf; + aip->NewStructSize = len; + } else { + if (ENV_ROMSTAGE) + aip->AllocationMethod = PreMemHeap; + if (ENV_RAMSTAGE) + aip->AllocationMethod = PostMemDram; + } + + aip->AgesaFunctionName = func; + status = module_dispatch(AMD_CREATE_STRUCT, &aip->StdHeader); if (status != AGESA_SUCCESS) { printk(BIOS_ERR, "Error: AmdCreateStruct() for 0x%x returned 0x%x. " "Proper system initialization may not be possible.\n", - interface_struct->AgesaFunctionName, status); + aip->AgesaFunctionName, status); } - if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ + if (!aip->NewStructPtr) die("No AGESA structure created"); - StdHeader = interface_struct->NewStructPtr; - StdHeader->Func = interface_struct->AgesaFunctionName; + StdHeader = aip->NewStructPtr; + StdHeader->Func = aip->AgesaFunctionName; return StdHeader; } +static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) +{ + return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); +} + static AGESA_STATUS amd_init_reset(void) { AGESA_STATUS status; AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESET, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_RESET_PARAMS), - .NewStructPtr = &_ResetParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS *ResetParams = create_struct(&AmdParamStruct); + AMD_RESET_PARAMS *ResetParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RESET, &_ResetParams, sizeof(AMD_RESET_PARAMS)); SetFchResetParams(&ResetParams->FchInterface); @@ -108,19 +127,17 @@ status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } static AGESA_STATUS amd_init_early(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_EARLY, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct); + AMD_EARLY_PARAMS *EarlyParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_EARLY, NULL, 0); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); @@ -129,7 +146,7 @@ status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -170,12 +187,10 @@ static AGESA_STATUS amd_init_post(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_POST, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct); + AMD_POST_PARAMS *PostParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_POST, NULL, 0); PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -215,7 +230,7 @@ print_init_post_settings(PostParams); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -223,12 +238,10 @@ static AGESA_STATUS amd_init_env(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_ENV, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParams = create_struct(&AmdParamStruct); + AMD_ENV_PARAMS *EnvParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_ENV, NULL, 0); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); @@ -237,7 +250,7 @@ status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -271,15 +284,13 @@ static AGESA_STATUS amd_init_mid(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_MID, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = create_struct(&AmdParamStruct); + AMD_MID_PARAMS *MidParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_MID, NULL, 0); SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); @@ -288,7 +299,7 @@ status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -296,16 +307,14 @@ static AGESA_STATUS amd_init_late(void) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_LATE, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; /* * NOTE: if not call amdcreatestruct, the initializer * (AmdInitLateInitializer) would not be called. */ - AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); + AMD_LATE_PARAMS *LateParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_LATE, NULL, 0); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -334,19 +343,17 @@ AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RTB, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); + AMD_RTB_PARAMS *RtbParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RTB, NULL, 0); timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); @@ -358,7 +365,7 @@ RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } @@ -366,13 +373,11 @@ static AGESA_STATUS amd_init_resume(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESUME, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = create_struct(&AmdParamStruct); + AMD_RESUME_PARAMS *InitResumeParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RESUME, NULL, 0); get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; @@ -381,7 +386,7 @@ status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -390,17 +395,13 @@ { AGESA_STATUS Status; AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3LATE_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3LATE_PARAMS), - .NewStructPtr = &_S3LateParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = create_struct(&AmdParamStruct); + AMD_S3LATE_PARAMS *S3LateParams = amd_create_struct(&AmdParamStruct, + AMD_S3LATE_RESTORE, &_S3LateParams, sizeof(AMD_S3LATE_PARAMS)); get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -409,7 +410,7 @@ Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } @@ -418,15 +419,11 @@ { AGESA_STATUS Status; AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3FINAL_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3FINAL_PARAMS), - .NewStructPtr = &_S3FinalParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = create_struct(&AmdParamStruct); + AMD_S3FINAL_PARAMS *S3FinalParams = amd_create_struct(&AmdParamStruct, + AMD_S3FINAL_RESTORE, &_S3FinalParams, sizeof(AMD_S3FINAL_PARAMS)); get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -435,7 +432,7 @@ Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index e17cedc..da89ce8 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -45,30 +45,3 @@ CONST UINT32 ModuleSignature = MODULE_SIGNATURE; CONST CHAR8 ModuleIdentifier[8] = AGESA_ID; -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e Gerrit-Change-Number: 31486 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019