coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/intel/sandybridge: Move boot_count_increment()
by Patrick Rudolph (Code Review) 13 May '19

13 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32067 Change subject: nb/intel/sandybridge: Move boot_count_increment() ...................................................................... nb/intel/sandybridge: Move boot_count_increment() Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/romstage.c 2 files changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32067/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065..34aec38 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <elog.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include "sandybridge.h" @@ -45,22 +44,7 @@ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 8ddc156..96d98ea 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <elog.h> static void early_pch_reset_pmcon(void) { @@ -80,6 +81,9 @@ s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/32067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Gerrit-Change-Number: 32067 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Choose better default settings for HSW
by Nico Huber (Code Review) 12 May '19

12 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31465 Change subject: drivers/intel/gma: Choose better default settings for HSW ...................................................................... drivers/intel/gma: Choose better default settings for HSW When libgfxinit was added, there were no Haswell boards in the tree with discrete CPU/PCH. There are now, and we have a Kconfig to distingush them. So use that instead of mainboard overrides. TEST=Built config for asrock/h81m-hds and checked that GFX_GMA_CPU_VARIANT is still set to `Normal`. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig 2 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31465/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2dbed01..fd2422d 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -105,7 +105,7 @@ default "ULT" if ((SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEY_LAKE) \ && !SOC_INTEL_CANNONLAKE_PCH_H) \ || ((SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE) && !SKYLAKE_SOC_PCH_H) \ - || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL + || SOC_INTEL_BROADWELL || (NORTHBRIDGE_INTEL_HASWELL && INTEL_LYNXPOINT_LP) default "Normal" config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 55f1637..f2ba55c 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -40,14 +40,6 @@ hex default 0x200000 -# -# The override of GFX_GMA_CPU_VARIANT should be removed once the patches -# for dynamic CPU detection are merged in libgfxinit. -# -config GFX_GMA_CPU_VARIANT - string - default "Normal" - config MAINBOARD_DIR string default asrock/h81m-hds -- To view, visit https://review.coreboot.org/c/coreboot/+/31465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Gerrit-Change-Number: 31465 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: soc/intel/cnl: Enable VT-d
by John Zhao (Code Review) 11 May '19

11 May '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32432 Change subject: soc/intel/cnl: Enable VT-d ...................................................................... soc/intel/cnl: Enable VT-d By default VT-d is disabled by fsp. Enabling VT-d by coreboot through upd VtdDisable. Set bit2 DMA_CTRL_PLATFORM_OPT_IN_FLAG to report any platform initiated DMA is restricted to only reserved memory regions (reported in RMRR structures) when transferring control to system software. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32432/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 43d91d3..2ee7f7e 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -358,7 +358,13 @@ return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + /* Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG. Platform firmware is + * recommended to set this field to report any platform initiated DMA + * is restricted to only reserved memory regions (reported in RMRR + * structures) when transferring control to system software. + */ + acpi_create_dmar(dmar, DMAR_INTR_REMAP | (1 << 2), soc_fill_dmar); + current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 2ad2c93..9fc90cf 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -103,6 +103,7 @@ assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg, config); @@ -114,6 +115,9 @@ /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + /* Configure VT-d */ + tconfig->VtdDisable = config->VtdDisable; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Gerrit-Change-Number: 32432 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Fix s5 touchscreen power leakage
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32367 Change subject: mb/google/sarien: Fix s5 touchscreen power leakage ...................................................................... mb/google/sarien: Fix s5 touchscreen power leakage Leakage power is observed from 3V_TSP_S0_FUSE during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry. BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32367/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..09ffd91 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,6 +39,8 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> } } diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c Gerrit-Change-Number: 32367 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/nami: Add VBT blobs and include them in cbfs
by Arthur Heymans (Code Review) 10 May '19

10 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30427 Change subject: mb/google/nami: Add VBT blobs and include them in cbfs ...................................................................... mb/google/nami: Add VBT blobs and include them in cbfs Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc R src/mainboard/google/poppy/variants/nami/akali-data.vbt A src/mainboard/google/poppy/variants/nami/data.vbt A src/mainboard/google/poppy/variants/nami/patheon-data.vbt A src/mainboard/google/poppy/variants/nami/vayne-data.vbt 5 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30427/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 7f86bb7..8f4ef0c 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -41,3 +41,15 @@ cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, akali-data.vbt, akali-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, vayne-data.vbt, vayne-vbt.bin) +$(call add_vbt_to_cbfs, data.vbt, vbt.bin) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000..8406362 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/patheon-data.vbt b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Gerrit-Change-Number: 30427 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0); /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2); /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Gerrit-Change-Number: 31027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/smbus: Init SMBus
by Michał Żygowski (Code Review) 10 May '19

10 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32062 Change subject: soc/intel/braswell/smbus: Init SMBus ...................................................................... soc/intel/braswell/smbus: Init SMBus Using Intel southbridge common implementation to retrieve SPD from DIMMs causes FSP memory init to hang. Initialize SMBus as in Intel SoC common before issuing any transactions to let FSP properly initialize memory. Also make Intel common southbridge smbus API compatible with SPD library. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 --- M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/include/soc/smbus.h M src/soc/intel/braswell/romstage/romstage.c A src/soc/intel/braswell/smbus.c 4 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32062/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index a538f7d..554af41 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c @@ -38,6 +39,7 @@ ramstage-y += sata.c ramstage-y += scc.c ramstage-y += sd.c +ramstage-y += smbus.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h new file mode 100644 index 0000000..f5075e1 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +#include <soc/pci_devs.h> + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)) +#else + +#include <device/pci_type.h> +#define PCH_DEV_SMBUS PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC) +#endif + +#define HOSTC 0x40 +#define HST_EN (1 << 0) + +void smbus_common_init(void); + +#endif /* _SOC_SMBUS_H_ */ diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ca1eb40..6a0226e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -40,6 +40,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/smbus.h> #include <soc/smm.h> #include <soc/spi.h> #include <build.h> @@ -194,6 +195,7 @@ spi_init(); lpc_init(); + smbus_common_init(); } /* SOC initialization after RAM is enabled */ diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c new file mode 100644 index 0000000..454c3f6 --- /dev/null +++ b/src/soc/intel/braswell/smbus.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/early_smbus.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <southbridge/intel/common/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBus I/O base address */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_BASE_ADDRESS), + /* Set SMBus enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); +} + +void smbus_common_init(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 Gerrit-Change-Number: 32062 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarein: Add arcada touchscreen stop gpio
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32178 Change subject: mb/google/sarein: Add arcada touchscreen stop gpio ...................................................................... mb/google/sarein: Add arcada touchscreen stop gpio Describe GPP_B21 pin as touchscreen stop gpio, which will be clear during s0ix and get set again when exit from s0ix. TEST=Check GPP_B21 pin stay low during s0ix on arcada platofrm. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ie87f374d3bca76b8a4b53676c95f2da08bb3a887 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32178/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bf3736..611140a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -303,6 +303,7 @@ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "5" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87f374d3bca76b8a4b53676c95f2da08bb3a887 Gerrit-Change-Number: 32178 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable options for wakeup
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30447 Change subject: soc/intel/cannonlake: Enable options for wakeup ...................................................................... soc/intel/cannonlake: Enable options for wakeup Cannonlake FSP silicon init have dedicated wake up capability settings for several IP, expose the selection into coreboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..e5a3ae1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -302,6 +302,13 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Wake Up Capability */ + uint8_t codec_wake_sx; + uint8_t pcie_wake_deepsx; + uint8_t wlan_wake_sx; + uint8_t wlan_wake_deepsx; + uint8_t glan_wake_deepsx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..9a24242 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -225,6 +225,14 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Wakeup Capability */ + params->PchHdaCodecSxWakeCapability = config->codec_wake_sx; + params->PchPmWoWlanEnable = config->wlan_wake_sx; + params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx; + params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx; + params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx; + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 Gerrit-Change-Number: 30447 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable LTR for PCIe NVMe root port
by Duncan Laurie (Code Review) 09 May '19

09 May '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32456 Change subject: mb/google/sarien: Enable LTR for PCIe NVMe root port ...................................................................... mb/google/sarien: Enable LTR for PCIe NVMe root port Enable LTR for NVMe so it can use ASPM L1.2. BUG=b:127593309 TEST=build and boot on sarien and check L1 substate with lspci before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32456/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 426bdae..77bd82a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -196,6 +196,7 @@ # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 27c0913..96146ba 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -197,6 +197,7 @@ # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" -- To view, visit https://review.coreboot.org/c/coreboot/+/32456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Gerrit-Change-Number: 32456 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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