coreboot-gerrit April 2019

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Change in ...coreboot[master]: device: ignore NONE devices behind bridge
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32441 Change subject: device: ignore NONE devices behind bridge ...................................................................... device: ignore NONE devices behind bridge Ignore NONE devices in dev_is_active_bridge that are commonly used to indicate hotplug capable ports. Tested on Lenovo T520: The empty ExpressCard Slot is no longer marked as active bridge. Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/device_util.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32441/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911..47df305 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -628,7 +628,7 @@ /* * Returns true if the device is an enabled bridge that has at least - * one enabled device on its secondary bus. + * one enabled device on its secondary bus that is not of type NONE. */ bool dev_is_active_bridge(struct device *dev) { @@ -643,6 +643,9 @@ for (link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_NONE) + continue; + if (child->enabled) return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a Gerrit-Change-Number: 32441 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: [WIP]sconfig: Add SMBIOS type 9 entries
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32307 Change subject: [WIP]sconfig: Add SMBIOS type 9 entries ...................................................................... [WIP]sconfig: Add SMBIOS type 9 entries Add the new fields: * slot_type that corresponds to SMBIOS type 9 'Slot Type' * slot_data_width that corresponds to SMBIOS type 9 'Slot Data Bus Width' Runtime code will be able to iterate over the PCI tree and fill in 'Bus Number', 'Device/Function', 'Slot Data Bus Width', 'Slot Type' and 'Current Usage'. Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device/device.h M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.y 5 files changed, 127 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32307/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d56..32c41a4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -141,6 +141,11 @@ #if !DEVTREE_EARLY struct chip_operations *chip_ops; const char *name; +#if CONFIG(GENERATE_SMBIOS_TABLES) + u8 smbios_slot_type; + u8 smbios_slot_data_width; + const char* smbios_slot_designation; +#endif #endif DEVTREE_CONST void *chip_info; }; diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e..22dfa59 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -622,6 +622,43 @@ } } +void add_slot_type(struct bus *bus, char *val) +{ + + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_type' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_type = val; +} + +void add_slot_data_width(struct bus *bus, char *val) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_data_width' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_data_width = val; +} + +void add_slot_designation(struct bus *bus, char *val) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_designation' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_designation = val; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -831,7 +868,26 @@ fprintf(fil, "\t.chip_info = &%s_info_%d,\n", chip_ins->chip->name_underscore, chip_ins->id); if (next) - fprintf(fil, "\t.next=&%s\n", next->name); + fprintf(fil, "\t.next=&%s,\n", next->name); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation) { + fprintf(fil, "#if !DEVTREE_EARLY\n"); + fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); + } + /* SMBIOS types start at 1, if zero it hasn't been set */ + if (ptr->smbios_slot_type) + fprintf(fil, "\t.smbios_slot_type = %s,\n", + ptr->smbios_slot_type); + if (ptr->smbios_slot_data_width) + fprintf(fil, "\t.smbios_slot_data_width = %s,\n", + ptr->smbios_slot_data_width); + if (ptr->smbios_slot_designation) + fprintf(fil, "\t.smbios_slot_designation = %s,\n", + ptr->smbios_slot_designation); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width) { + fprintf(fil, "#endif\n"); + fprintf(fil, "#endif\n"); + } fprintf(fil, "};\n"); emit_resources(fil, ptr); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697..6abb90f 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -141,6 +141,15 @@ struct bus *bus; /* Pointer to last bus under this device. */ struct bus *last_bus; + + /* SMBIOS slot type */ + char *smbios_slot_type; + + /* SMBIOS slot data width */ + char *smbios_slot_data_width; + + /* SMBIOS slot description for reference designation */ + char *smbios_slot_designation; }; extern struct bus *root_parent; @@ -158,6 +167,12 @@ void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin, int irqpin); +void add_slot_type(struct bus *bus, char *val); + +void add_slot_data_width(struct bus *bus, char *val); + +void add_slot_designation(struct bus *bus, char *val); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca5..491eab9 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -21,40 +21,43 @@ %} %option nodebug %% -[ \t]+ {} -#.*\n {linenum++;} -\r?\n {linenum++;} -chip {return(CHIP);} -device {return(DEVICE);} -register {return(REGISTER);} -on {yylval.number=1; return(BOOL);} -off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} -pci {yylval.number=PCI; return(BUS);} -ioapic {yylval.number=IOAPIC; return(BUS);} -pnp {yylval.number=PNP; return(BUS);} -i2c {yylval.number=I2C; return(BUS);} -lapic {yylval.number=APIC; return(BUS);} -cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} -cpu {yylval.number=CPU; return(BUS);} -domain {yylval.number=DOMAIN; return(BUS);} -generic {yylval.number=GENERIC; return(BUS);} -mmio {yylval.number=MMIO; return(BUS);} -spi {yylval.number=SPI; return(BUS);} -usb {yylval.number=USB; return(BUS);} -irq {yylval.number=IRQ; return(RESOURCE);} -drq {yylval.number=DRQ; return(RESOURCE);} -io {yylval.number=IO; return(RESOURCE);} -ioapic_irq {return(IOAPIC_IRQ);} -inherit {return(INHERIT);} -subsystemid {return(SUBSYSTEMID);} -end {return(END);} -= {return(EQUALS);} -0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} -\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +[ \t]+ {} +#.*\n {linenum++;} +\r?\n {linenum++;} +chip {return(CHIP);} +device {return(DEVICE);} +register {return(REGISTER);} +on {yylval.number=1; return(BOOL);} +off {yylval.number=0; return(BOOL);} +hidden {yylval.number=3; return(HIDDEN);} +pci {yylval.number=PCI; return(BUS);} +ioapic {yylval.number=IOAPIC; return(BUS);} +pnp {yylval.number=PNP; return(BUS);} +i2c {yylval.number=I2C; return(BUS);} +lapic {yylval.number=APIC; return(BUS);} +cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} +cpu {yylval.number=CPU; return(BUS);} +domain {yylval.number=DOMAIN; return(BUS);} +generic {yylval.number=GENERIC; return(BUS);} +mmio {yylval.number=MMIO; return(BUS);} +spi {yylval.number=SPI; return(BUS);} +usb {yylval.number=USB; return(BUS);} +irq {yylval.number=IRQ; return(RESOURCE);} +drq {yylval.number=DRQ; return(RESOURCE);} +io {yylval.number=IO; return(RESOURCE);} +ioapic_irq {return(IOAPIC_IRQ);} +inherit {return(INHERIT);} +subsystemid {return(SUBSYSTEMID);} +end {return(END);} +slot_type {return(SLOT_TYPE);} +slot_data_width {return(SLOT_DATA_WIDTH);} +slot_designation {return(SLOT_DESIGNATION);} += {return(EQUALS);} +0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} %% diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab..cbb8be5 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,13 +31,13 @@ int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESIGNATION SLOT_TYPE SLOT_DATA_WIDTH IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren slot_type | devicechildren slot_data_width | devicechildren slot_designation | /* empty */ ; chip: CHIP STRING /* == path */ { $<chip_instance>$ = new_chip_instance($<string>2); @@ -72,4 +72,13 @@ ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER { add_ioapic_info(cur_parent, strtol($<string>2, NULL, 16), $<string>3, strtol($<string>4, NULL, 16)); }; + +slot_designation: SLOT_DESIGNATION STRING + { add_slot_designation(cur_parent, $<string>2); }; + +slot_type: SLOT_TYPE STRING + { add_slot_type(cur_parent, $<string>2); }; + +slot_data_width: SLOT_DATA_WIDTH STRING + { add_slot_data_width(cur_parent, $<string>2); }; %% -- To view, visit https://review.coreboot.org/c/coreboot/+/32307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Gerrit-Change-Number: 32307 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

8 13

Change in ...coreboot[master]: google/kukui: Enable boot sound support
by Jiaxin Yu (Code Review) 07 May '19

07 May '19

Jiaxin Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32459 Change subject: google/kukui: Enable boot sound support ...................................................................... google/kukui: Enable boot sound support Config enable gpio for speaker amp max98357a. BUG=b:117254418 TEST=Build pass and verified on kukui p1 board BRANCH=None Change-Id: I97655702dff402245326d2eff71fae0e336df9f5 Signed-off-by: Jiaxin Yu <jiaxin.yu(a)mediatek.com> --- M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/kukui/gpio.h M src/mainboard/google/kukui/mainboard.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/32459/1 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 44e75e2..ad2edaa 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -27,6 +27,7 @@ gpio_input_pullup(EC_IRQ); gpio_input_pullup(CR50_IRQ); gpio_output(GPIO_RESET, 0); + gpio_output(EN_SPK_AMP, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -38,6 +39,7 @@ {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {EN_SPK_AMP.id, ACTIVE_HIGH, -1, "SPK enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 92d238e..0a98997 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -23,6 +23,7 @@ #define EC_IN_RW GPIO(PERIPHERAL_EN14) #define CR50_IRQ GPIO(PERIPHERAL_EN3) #define GPIO_RESET GPIO(PERIPHERAL_EN8) +#define EN_SPK_AMP GPIO(PERIPHERAL_EN12) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..40b8a49 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,10 +38,22 @@ setup_usb_host(); } +static void configure_audio(void) +{ + /* Audio PWR*/ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(CAM_RST0), PAD_CAM_RST0_FUNC_I2S2_LRCK); + gpio_set_mode(GPIO(CAM_PDN1), PAD_CAM_PDN1_FUNC_I2S2_BCK); + gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); + gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); +} static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + configure_audio(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/32459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97655702dff402245326d2eff71fae0e336df9f5 Gerrit-Change-Number: 32459 Gerrit-PatchSet: 1 Gerrit-Owner: Jiaxin Yu <jiaxin.yu(a)mediatek.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: mb/google/sarien: Turn off camera power when s0ix
by EricR Lai (Code Review) 06 May '19

06 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32519 Change subject: mb/google/sarien: Turn off camera power when s0ix ...................................................................... mb/google/sarien: Turn off camera power when s0ix Turn off camera power when s0ix for power saving. ACPI _ON/_OFF is not taken by UVC driver, so invoke s0ix method from LPIT. BUG=b:129177593 TEST= measure camera power comsumption is 0mV under s0ix Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl M src/soc/intel/cannonlake/acpi/lpit.asl 4 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32519/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..58e0704 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,6 +40,8 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + \_SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + \_SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + \_SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + \_SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 8515806..00115a5 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -62,12 +62,14 @@ */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + \_SB.MS0X(1) } /* * Function 6. */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + \_SB.MS0X(0) } } Return(Buffer(One) {0x00}) -- To view, visit https://review.coreboot.org/c/coreboot/+/32519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed Gerrit-Change-Number: 32519 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 23

Change in ...coreboot[master]: WIP: Power resource stub
by Tim Wawrzynczak (Code Review) 06 May '19

06 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32188 Change subject: WIP: Power resource stub ...................................................................... WIP: Power resource stub Change-Id: I253a11e24a086792e151c3e47335586d43c3fce0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/device/device_util.c A src/drivers/generic/power_resource/Kconfig A src/drivers/generic/power_resource/Makefile.inc A src/drivers/generic/power_resource/chip.h A src/drivers/generic/power_resource/power_resource.c M src/drivers/i2c/generic/chip.h M src/drivers/i2c/generic/generic.c M src/include/device/device.h M src/include/device/path.h M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.y 14 files changed, 256 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32188/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911..f6474ef 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -232,6 +232,8 @@ snprintf(buffer, sizeof(buffer), "MMIO: %08x", dev->path.mmio.addr); break; + case DEVICE_PATH_POWER_RES: + snprintf(buffer, sizeof(buffer), "POWER_RES"); default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); diff --git a/src/drivers/generic/power_resource/Kconfig b/src/drivers/generic/power_resource/Kconfig new file mode 100644 index 0000000..f0d4769 --- /dev/null +++ b/src/drivers/generic/power_resource/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_GENERIC_POWER_RESOURCE + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/generic/power_resource/Makefile.inc b/src/drivers/generic/power_resource/Makefile.inc new file mode 100644 index 0000000..e076252 --- /dev/null +++ b/src/drivers/generic/power_resource/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += power_resource.c diff --git a/src/drivers/generic/power_resource/chip.h b/src/drivers/generic/power_resource/chip.h new file mode 100644 index 0000000..49ce49f --- /dev/null +++ b/src/drivers/generic/power_resource/chip.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GENERIC_POWER_RESOURCE_CHIP_H__ +#define __GENERIC_POWER_RESOURCE_CHIP_H__ + +#include <arch/acpi_device.h> + +struct drivers_generic_power_resource_config { + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + /* GPIO used to stop operation of device. */ + struct acpi_gpio stop_gpio; + /* Delay to be inserted after disabling stop. */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. */ + unsigned int stop_off_delay_ms; +}; + +#if CONFIG(HAVE_ACPI_TABLES) + +/* + * + */ +void power_resource_generic_fill_ssdt(struct device *dev); + +#endif /* #if CONFIG(HAVE_ACPI_TABLES) */ + +#endif /* __GENERIC_POWER_RESOURCE_CHIP_H__ */ diff --git a/src/drivers/generic/power_resource/power_resource.c b/src/drivers/generic/power_resource/power_resource.c new file mode 100644 index 0000000..13f922e --- /dev/null +++ b/src/drivers/generic/power_resource/power_resource.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/path.h> +#include <console/console.h> +#include "chip.h" + +static struct device_operations power_resource_dev_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .scan_bus = &scan_generic_bus, + .acpi_fill_ssdt_generator = &power_resource_generic_fill_ssdt +}; + +static void power_resource_dev_enable(struct device *dev) +{ + printk(BIOS_WARNING, "@@ in power_resource_dev_enable\n"); + dev->ops = &power_resource_dev_ops; +} + +struct chip_operations drivers_generic_power_resource_ops = { + CHIP_NAME("Power resource") + .enable_dev = power_resource_dev_enable +}; + +#if CONFIG(HAVE_ACPI_TABLES) + +static void fill_ssdt(struct device *dev, + struct drivers_generic_power_resource_config *config) +{ + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + &config->stop_gpio, + config->stop_delay_ms, + config->stop_off_delay_ms + }; + + acpi_device_add_power_res(&power_res_params); +} + +void power_resource_generic_fill_ssdt(struct device *dev) +{ + printk(BIOS_WARNING, "@@ in power_resource fill ssdt\n"); + fill_ssdt(dev, dev->chip_info); +} + +#endif /* CONFIG(HAVE_ACPI_TABLES) */ diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 9e2abb9..ec83365 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -50,28 +50,6 @@ /* Disable reset and enable GPIO export in _CRS */ bool disable_gpio_export_in_crs; - /* Does the device have a power resource? */ - bool has_power_resource; - - /* GPIO used to take device out of reset or to put it into reset. */ - struct acpi_gpio reset_gpio; - /* Delay to be inserted after device is taken out of reset. */ - unsigned int reset_delay_ms; - /* Delay to be inserted after device is put into reset. */ - unsigned int reset_off_delay_ms; - /* GPIO used to enable device. */ - struct acpi_gpio enable_gpio; - /* Delay to be inserted after device is enabled. */ - unsigned int enable_delay_ms; - /* Delay to be inserted after device is disabled. */ - unsigned int enable_off_delay_ms; - /* GPIO used to stop operation of device. */ - struct acpi_gpio stop_gpio; - /* Delay to be inserted after disabling stop. */ - unsigned int stop_delay_ms; - /* Delay to be inserted after enabling stop. */ - unsigned int stop_off_delay_ms; - /* Generic properties for exporting device-specific data to the OS */ struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST]; int property_count; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 598f211..161086e 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -23,19 +23,24 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include <drivers/generic/power_resource/chip.h> #if CONFIG(HAVE_ACPI_TABLES) -static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) +static bool i2c_generic_add_gpios_to_crs(struct drivers_generic_power_resource_config *pr_config, + struct drivers_i2c_generic_config *cfg) { /* * Return false if: * 1. Request to explicitly disable export of GPIOs in CRS, or * 2. Both reset and enable GPIOs are not provided. */ + if (!pr_config) + return false; + if (cfg->disable_gpio_export_in_crs || - ((cfg->reset_gpio.pin_count == 0) && - (cfg->enable_gpio.pin_count == 0))) + ((pr_config->reset_gpio.pin_count == 0) && + (pr_config->enable_gpio.pin_count == 0))) return false; return true; @@ -70,6 +75,10 @@ int curr_index = 0; int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1; const char *path = acpi_device_path(dev); + struct device *pr_dev; + struct drivers_generic_power_resource_config *pr_config; + struct acpi_gpio *reset_gpio; + struct acpi_gpio *enable_gpio; if (!dev->enabled || !scope) return; @@ -79,6 +88,20 @@ return; } + /* Check for an associated power resource device */ + if (dev->link_list && dev->link_list->children && + dev->link_list->children->path.type == DEVICE_PATH_POWER_RES) { + pr_dev = dev->link_list->children; + pr_config = pr_dev->chip_info; + reset_gpio = &pr_config->reset_gpio; + enable_gpio = &pr_config->enable_gpio; + } else { + pr_dev = NULL; + pr_config = NULL; + reset_gpio = NULL; + enable_gpio = NULL; + } + /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); @@ -101,10 +124,10 @@ else acpi_device_write_interrupt(&config->irq); - if (i2c_generic_add_gpios_to_crs(config) == true) { - reset_gpio_index = i2c_generic_write_gpio(&config->reset_gpio, + if (pr_config && i2c_generic_add_gpios_to_crs(pr_config, config) == true) { + reset_gpio_index = i2c_generic_write_gpio(reset_gpio, &curr_index); - enable_gpio_index = i2c_generic_write_gpio(&config->enable_gpio, + enable_gpio_index = i2c_generic_write_gpio(enable_gpio, &curr_index); } acpigen_write_resourcetemplate_footer(); @@ -120,8 +143,15 @@ (reset_gpio_index != -1) || (enable_gpio_index != -1) || (irq_gpio_index != -1)) { dsd = acpi_dp_new_table("_DSD"); + + /* + TODO: tdw + remove this + */ if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + /* end remove */ + if (irq_gpio_index != -1) acpi_dp_add_gpio(dsd, "irq-gpios", path, irq_gpio_index, 0, @@ -130,11 +160,11 @@ if (reset_gpio_index != -1) acpi_dp_add_gpio(dsd, "reset-gpios", path, reset_gpio_index, 0, - config->reset_gpio.polarity); + reset_gpio->polarity); if (enable_gpio_index != -1) acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, - config->enable_gpio.polarity); + enable_gpio->polarity); /* Add generic property list */ acpi_dp_add_property_list(dsd, config->property_list, config->property_count); @@ -142,20 +172,8 @@ } /* Power Resource */ - if (config->has_power_resource) { - const struct acpi_power_res_params power_res_params = { - &config->reset_gpio, - config->reset_delay_ms, - config->reset_off_delay_ms, - &config->enable_gpio, - config->enable_delay_ms, - config->enable_off_delay_ms, - &config->stop_gpio, - config->stop_delay_ms, - config->stop_off_delay_ms - }; - acpi_device_add_power_res(&power_res_params); - } + if (pr_dev) + power_resource_generic_fill_ssdt(pr_dev); /* Callback if any. */ if (callback) diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d56..6a24365 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -126,6 +126,7 @@ unsigned int on_mainboard : 1; unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ + unsigned int probed : 1; /* set if device's presence should be probed */ struct pci_irq_info pci_irq_info[4]; u8 command; diff --git a/src/include/device/path.h b/src/include/device/path.h index 6736bed..46180d7 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -19,6 +19,7 @@ DEVICE_PATH_SPI, DEVICE_PATH_USB, DEVICE_PATH_MMIO, + DEVICE_PATH_POWER_RES /* * When adding path types to this table, please also update the @@ -42,6 +43,7 @@ "DEVICE_PATH_SPI", \ "DEVICE_PATH_USB", \ "DEVICE_PATH_MMIO", \ + "DEVICE_PATH_POWER_RES", \ } struct domain_path { diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2f1120a..2562cfb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -185,11 +185,75 @@ register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device i2c 49 on #probed + chip drivers/generic/power_resource + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device power_resource 0 on end + end + end + end + end # I2C #1 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e..c66e66e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -511,8 +511,17 @@ sprintf(name, "_dev%d", new_d->id); new_d->name = name; - new_d->enabled = status & 0x01; - new_d->hidden = (status >> 1) & 0x01; + /* probed? */ + if (status == 2) { + new_d->probed = 1; + new_d->enabled = 0; + new_d->hidden = 0; + } else { + new_d->enabled = status & 0x01; + new_d->hidden = (status >> 1) & 0x01; + new_d->probed = 0; + } + new_d->chip_instance = chip_instance; chip_instance->ref_count++; @@ -566,6 +575,9 @@ case MMIO: new_d->path = ".type=DEVICE_PATH_MMIO,{.mmio={ .addr = 0x%x }}"; break; + + case POWER_RESOURCE: + new_d->path = ".type=DEVICE_PATH_POWER_RES,"; } return new_d; @@ -789,6 +801,7 @@ fprintf(fil, "},\n"); fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); fprintf(fil, "\t.hidden = %d,\n", ptr->hidden); + fprintf(fil, "\t.probed = %d,\n", ptr->probed); fprintf(fil, "\t.on_mainboard = 1,\n"); if (ptr->subsystem_vendor > 0) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697..5aae51ad 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -102,9 +102,10 @@ /* Monotonically increasing ID for the device. */ int id; - /* Indicates device status (enabled / hidden or not). */ + /* Indicates device status (enabled / hidden / probed or not). */ int enabled; int hidden; + int probed; /* Subsystem IDs for the device. */ int subsystem_vendor; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca5..32ecd57 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -29,11 +29,13 @@ register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} +probed {yylval.number=2; return(PROBED);} hidden {yylval.number=3; return(HIDDEN);} pci {yylval.number=PCI; return(BUS);} ioapic {yylval.number=IOAPIC; return(BUS);} pnp {yylval.number=PNP; return(BUS);} i2c {yylval.number=I2C; return(BUS);} +power_resource {yylval.number=POWER_RESOURCE; return(BUS);} lapic {yylval.number=APIC; return(BUS);} cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} cpu {yylval.number=CPU; return(BUS);} diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab..ce0f111 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,7 +31,7 @@ int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN PROBED BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO POWER_RESOURCE %% devtree: { cur_parent = root_parent; } chip; @@ -56,7 +56,7 @@ cur_parent = $<dev>5->parent; }; -status: BOOL | HIDDEN; +status: BOOL | HIDDEN | PROBED; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ { add_resource(cur_parent, $<number>1, strtol($<string>2, NULL, 0), strtol($<string>4, NULL, 0)); } ; -- To view, visit https://review.coreboot.org/c/coreboot/+/32188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I253a11e24a086792e151c3e47335586d43c3fce0 Gerrit-Change-Number: 32188 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: google/kukui: Raising the CPU frequency
by Tristan Hsieh (Code Review) 06 May '19

06 May '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32466 Change subject: google/kukui: Raising the CPU frequency ...................................................................... google/kukui: Raising the CPU frequency Run CPU at the highest freqency (1989MHz) to speed up the boot time. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32466/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 81ae9c5..baaca43 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -17,6 +17,7 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> +#include <soc/pll.h> #include <soc/rtc.h> #include "early_init.h" @@ -28,6 +29,7 @@ mainboard_early_init(); mt6358_init(); + mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac Gerrit-Change-Number: 32466 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

6 19

Change in ...coreboot[master]: vboot: remove use of GoogleBinaryBlockHeader
by Joel Kitching (Code Review) 06 May '19

06 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32455 Change subject: vboot: remove use of GoogleBinaryBlockHeader ...................................................................... vboot: remove use of GoogleBinaryBlockHeader Remove use of deprecated GoogleBinaryBlockHeader struct, and replace with vb2_gbb_header. BUG=b:124141368, chromium:954774 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/gbb.c M src/security/vboot/gbb.h M src/security/vboot/vboot_common.c 3 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32455/1 diff --git a/src/security/vboot/gbb.c b/src/security/vboot/gbb.c index 8f57c79..5293033 100644 --- a/src/security/vboot/gbb.c +++ b/src/security/vboot/gbb.c @@ -13,17 +13,19 @@ * GNU General Public License for more details. */ +#define NEED_VB20_INTERNALS /* Peeking into vb2_gbb_header */ + #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> -#include <gbb_header.h> #include <security/vboot/gbb.h> #include <string.h> +#include <vb2_api.h> #define GBB_FMAP_REGION_NAME "GBB" /* Copy of GBB header read from boot media. */ -static GoogleBinaryBlockHeader gbb_header; +static struct vb2_gbb_header gbb_header; /* * Read "GBB" region from SPI flash to obtain GBB header and validate @@ -45,13 +47,14 @@ return 1; if (rdev_readat(&gbb_rdev, &gbb_header, 0, - sizeof(GoogleBinaryBlockHeader)) != - sizeof(GoogleBinaryBlockHeader)) { + sizeof(struct vb2_gbb_header)) != + sizeof(struct vb2_gbb_header)) { printk(BIOS_ERR, "%s: Failure to read GBB header!\n", __func__); return 1; } - if (memcmp(gbb_header.signature, GBB_SIGNATURE, GBB_SIGNATURE_SIZE)) { + if (memcmp(gbb_header.signature, VB2_GBB_SIGNATURE, + VB2_GBB_SIGNATURE_SIZE)) { printk(BIOS_ERR, "%s: Signature check failed!\n", __func__); return 1; } diff --git a/src/security/vboot/gbb.h b/src/security/vboot/gbb.h index 550548d..389242a 100644 --- a/src/security/vboot/gbb.h +++ b/src/security/vboot/gbb.h @@ -18,7 +18,7 @@ #include <stdint.h> -/* In order to use GBB_FLAG_* macros from vboot, include gbb_header.h. */ +/* In order to use VB2_GBB_FLAG_* macros from vboot, include vb2_api.h. */ /* * Read flags field from GBB header. diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 5e95c62..b434f8d 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -18,12 +18,12 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <fmap.h> -#include <gbb_header.h> #include <reset.h> #include <stddef.h> #include <security/vboot/gbb.h> #include <security/vboot/vboot_common.h> #include <security/vboot/vbnv.h> +#include <vb2_api.h> int vboot_named_region_device(const char *name, struct region_device *rdev) { @@ -42,7 +42,7 @@ if (!vboot_developer_mode_enabled()) return 0; /* Enable if GBB flag is set */ - if (gbb_is_flag_set(GBB_FLAG_ENABLE_UDC)) + if (gbb_is_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) return 1; /* Enable if VBNV flag is set */ if (vbnv_udc_enable_flag()) -- To view, visit https://review.coreboot.org/c/coreboot/+/32455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2 Gerrit-Change-Number: 32455 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Update vboot submodule to upstream master
by Martin Roth (Code Review) 06 May '19

06 May '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32344 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 304aa429: 2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags) to commit id dccea9ae: 2019-04-15 02:06:22 -0700 - (vboot: add magic and version to vb2_shared_data) This brings in 37 new commits. Change-Id: Ia91fadf4f50d9b7ce14143aaa0a1e2e1c5cbef07 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32344/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 304aa42..dccea9a 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca +Subproject commit dccea9ae88059c8cb7dff76d2682835184fc8338 -- To view, visit https://review.coreboot.org/c/coreboot/+/32344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia91fadf4f50d9b7ce14143aaa0a1e2e1c5cbef07 Gerrit-Change-Number: 32344 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: util/inteltool: Add Sunrise Point LP (Skylake) IDs
by Felix Singer (Code Review) 06 May '19

06 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31506 Change subject: util/inteltool: Add Sunrise Point LP (Skylake) IDs ...................................................................... util/inteltool: Add Sunrise Point LP (Skylake) IDs Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31506/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..bdcee02 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -224,11 +224,19 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point Mobile Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1, "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2, + "Sunrise Point-LP U Base" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1, "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2, + "Sunrise Point-LP U Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1, + "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2, "Sunrise Point-LP Y Premium" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, "Sunrise Point-LP U iHDCP 2.2 Base" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..9fbe9b5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -144,10 +144,14 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2 0x9d58 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2 0x9d56 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b -- To view, visit https://review.coreboot.org/c/coreboot/+/31506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Gerrit-Change-Number: 31506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: Documentation: Add MSI MS-7707
by Bluemax (Code Review) 06 May '19

06 May '19

Bluemax has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32236 Change subject: Documentation: Add MSI MS-7707 ...................................................................... Documentation: Add MSI MS-7707 Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Signed-off-by: Bluemax <1403092+BlueMax(a)users.noreply.github.com> --- A Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg A Documentation/mainboard/medion/ms_7707/logs/cbmem.log A Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt A Documentation/mainboard/medion/ms_7707/logs/superiotool.log A Documentation/mainboard/medion/ms_7707/ms-7707.md 5 files changed, 1,084 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32236/1 diff --git a/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg b/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg new file mode 100644 index 0000000..d747774 --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg Binary files differ diff --git a/Documentation/mainboard/medion/ms_7707/logs/cbmem.log b/Documentation/mainboard/medion/ms_7707/logs/cbmem.log new file mode 100644 index 0000000..9921fe5 --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/cbmem.log @@ -0,0 +1,751 @@ +*** Pre-CBMEM romstage console overflowed, log truncated! *** + : 24T +Selected tWR : 10T +Selected tFAW : 20T +Selected tRRD : 4T +Selected tRTP : 5T +Selected tWTR : 5T +Selected tRFC : 107T +Done dimm mapping +Update PCI-E configuration space: +PCI(0, 0, 0)[a0] = 0 +PCI(0, 0, 0)[a4] = 1 +PCI(0, 0, 0)[bc] = 8a800000 +PCI(0, 0, 0)[a8] = 75000000 +PCI(0, 0, 0)[ac] = 1 +PCI(0, 0, 0)[b8] = 80000000 +PCI(0, 0, 0)[b0] = 80800000 +PCI(0, 0, 0)[b4] = 80800000 +PCI(0, 0, 0)[7c] = 7f +PCI(0, 0, 0)[70] = ff800000 +PCI(0, 0, 0)[74] = 0 +PCI(0, 0, 0)[78] = ff800c00 +Done memory map +Done io registers +Done jedec reset +Done MRS commands +t123: 1912, 9120, 500 +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : Bring up +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : 0x4e +ME: FWS2: 0x104e0006 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x3 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x0 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x0 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0x4e +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +Waited long enough, or CPU was not replaced, continue... +PASSED! Tell ME that DRAM is ready +ME: FWS2: 0x102c0006 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x3 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x0 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x0 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0x2c +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +ME: Requested BIOS Action: Continue to boot +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : Bring up +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : 0x2c +memcfg DDR3 ref clock 133 MHz +memcfg DDR3 clock 1330 MHz +memcfg channel assignment: A: 0, B 1, C 2 +memcfg channel[0] config (00600008): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 2048 MB width x8 single rank, selected + DIMMB 0 MB width x8 single rank +memcfg channel[1] config (00600008): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 2048 MB width x8 single rank, selected + DIMMB 0 MB width x8 single rank +CBMEM: +IMD: root @ 7ffff000 254 entries. +IMD: root @ 7fffec00 62 entries. +External stage cache: +IMD: root @ 803ff000 254 entries. +IMD: root @ 803fec00 62 entries. +CBMEM entry for DIMM info: 0x7fffea40 +MTRR Range: Start=ffc00000 End=0 (Size 400000) +MTRR Range: Start=0 End=1000000 (Size 1000000) +MTRR Range: Start=7f800000 End=80000000 (Size 800000) +MTRR Range: Start=80000000 End=80800000 (Size 800000) +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/postcar' +CBFS: Found @ offset 2ef00 size 3c28 +Decompressing stage fallback/postcar @ 0x7ffcefc0 (32016 bytes) +Loading module at 7ffcf000 with entry 7ffcf000. filesize: 0x3a10 memsize: 0x7cd0 +Processing 111 relocs. Offset value of 0x7dfcf000 + + +coreboot-4.9-1212-g3eebb16c05-dirty Wed Apr 3 16:57:19 UTC 2019 postcar starting (log level: 7)... +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 19c00 size 14d90 +Decompressing stage fallback/ramstage @ 0x7ff8bfc0 (270072 bytes) +Loading module at 7ff8c000 with entry 7ff8c000. filesize: 0x2c590 memsize: 0x41eb8 +Processing 3092 relocs. Offset value of 0x7f18c000 + + +coreboot-4.9-1212-g3eebb16c05-dirty Wed Apr 3 16:57:19 UTC 2019 ramstage starting (log level: 7)... +Normal boot. +BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0 +Enumerating buses... +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/0100] enabled +PCI: 00:01.0 [8086/0101] enabled +PCI: 00:16.0 [8086/1c3a] enabled +PCI: 00:16.1: Disabling device +PCI: 00:16.1 [8086/1c3b] disabled No operations +PCI: 00:16.2: Disabling device +PCI: 00:16.2 [8086/1c3c] disabled No operations +PCI: 00:16.3: Disabling device +PCI: 00:16.3 [8086/1c3d] disabled No operations +PCI: 00:19.0 [8086/1503] enabled +PCI: 00:1a.0 [8086/1c2d] enabled +PCI: 00:1b.0 [8086/1c20] enabled +PCH: PCIe Root Port coalescing is enabled +PCI: 00:1c.0 [8086/1c10] enabled +PCI: 00:1c.1: Disabling device +PCI: 00:1c.2: Disabling device +PCI: 00:1c.3: Disabling device +PCI: 00:1c.4: Disabling device +PCI: 00:1c.4: check set enabled +PCI: 00:1c.4 [8086/1c18] disabled +PCI: 00:1c.5: Disabling device +PCI: 00:1c.5 [8086/1c1a] disabled +PCH: Remap PCIe function 6 to 1 +PCI: 00:1c.6 [8086/1c1c] enabled +PCI: 00:1c.7: Disabling device +PCH: PCIe map 1c.1 -> 1c.6 +PCH: PCIe map 1c.6 -> 1c.1 +PCI: 00:1d.0 [8086/1c26] enabled +PCI: 00:1e.0: Disabling device +PCI: 00:1e.0 [8086/244e] disabled No operations +PCI: 00:1f.0 [8086/1c46] enabled +PCI: 00:1f.2 [8086/1c00] enabled +PCI: 00:1f.3 [8086/1c22] enabled +PCI: 00:1f.5: Disabling device +PCI: 00:1f.5 [8086/1c08] disabled No operations +PCI: 00:1f.6: Disabling device +PCI: 00:1f.6 [8086/1c24] disabled No operations +PCI: Leftover static devices: +PCI: 00:02.0 +PCI: 00:1c.6 +PCI: 00:1c.2 +PCI: 00:1c.3 +PCI: 00:1c.7 +PCI: Check your devicetree.cb. +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [10de/0614] enabled +Enabling Common Clock Configuration +ASPM: Enabled L0s and L1 +Failed to enable LTR for dev = PCI: 01:00.0 +scan_bus: scanning of bus PCI: 00:01.0 took 127 usecs +PCI: pci_scan_bus for bus 02 +scan_bus: scanning of bus PCI: 00:1c.0 took 41 usecs +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [1033/0194] enabled +Enabling Common Clock Configuration +ASPM: Enabled L0s and L1 +scan_bus: scanning of bus PCI: 00:1c.1 took 219 usecs +PNP: 004e.1 disabled +PNP: 004e.4 enabled +PNP: 004e.5 enabled +PNP: 004e.6 enabled +PNP: 004e.7 enabled +PNP: 004e.8 disabled +PNP: 004e.a enabled +scan_bus: scanning of bus PCI: 00:1f.0 took 111 usecs +scan_bus: scanning of bus PCI: 00:1f.3 took 1 usecs +scan_bus: scanning of bus DOMAIN: 0000 took 735 usecs +scan_bus: scanning of bus Root Device took 738 usecs +done +FMAP: Found "FLASH" version 1.1 at 210000. +FMAP: base = ffc00000 size = 400000 #areas = 4 +FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes) +MRC: Checking cached data update for 'RW_MRC_CACHE'. +Manufacturer: ef +SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 +MRC: no data in 'RW_MRC_CACHE' +MRC: cache data 'RW_MRC_CACHE' needs update. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 755 exit 7946 +found VGA at PCI: 01:00.0 +Setting up VGA for PCI: 01:00.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +Done reading resources. +skipping PNP: 004e.6@c1 fixed resource, size=0! +skipping PNP: 004e.6@c5 fixed resource, size=0! +skipping PNP: 004e.6@ce fixed resource, size=0! +skipping PNP: 004e.6@cf fixed resource, size=0! +skipping PNP: 004e.6@d0 fixed resource, size=0! +skipping PNP: 004e.6@d1 fixed resource, size=0! +skipping PNP: 004e.6@d3 fixed resource, size=0! +skipping PNP: 004e.6@e1 fixed resource, size=0! +skipping PNP: 004e.6@f1 fixed resource, size=0! +skipping PNP: 004e.7@f6 fixed resource, size=0! +skipping PNP: 004e.7@30 fixed resource, size=0! +skipping PNP: 004e.7@f0 fixed resource, size=0! +skipping PNP: 004e.a@30 fixed resource, size=0! +skipping PNP: 004e.a@e0 fixed resource, size=0! +skipping PNP: 004e.a@f4 fixed resource, size=0! +skipping PNP: 004e.a@f8 fixed resource, size=0! +skipping PNP: 004e.a@f9 fixed resource, size=0! +skipping PNP: 004e.a@fa fixed resource, size=0! +Setting resources... +TOUUD 0x175000000 TOLUD 0x8a800000 TOM 0x100000000 +MEBASE 0xff800000 +IGD decoded, subtracting 160M UMA and 0M GTT +TSEG base 0x80000000 size 8M +Available memory below 4GB: 2048M +Available memory above 4GB: 1872M +PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem +PCI: 00:01.0 20 <- [0x00e0000000 - 0x00e30fffff] size 0x03100000 gran 0x14 bus 01 mem +PCI: 01:00.0 10 <- [0x00e2000000 - 0x00e2ffffff] size 0x01000000 gran 0x18 mem +PCI: 01:00.0 14 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 01:00.0 1c <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x19 mem64 +PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 01:00.0 30 <- [0x00e3000000 - 0x00e301ffff] size 0x00020000 gran 0x11 romem +PCI: 00:16.0 10 <- [0x00e3229000 - 0x00e322900f] size 0x00000010 gran 0x04 mem64 +PCI: 00:19.0 10 <- [0x00e3200000 - 0x00e321ffff] size 0x00020000 gran 0x11 mem +PCI: 00:19.0 14 <- [0x00e3224000 - 0x00e3224fff] size 0x00001000 gran 0x0c mem +PCI: 00:19.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io +PCI: 00:1a.0 10 <- [0x00e3226000 - 0x00e32263ff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00e3220000 - 0x00e3223fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.1 20 <- [0x00e3100000 - 0x00e31fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 03:00.0 10 <- [0x00e3100000 - 0x00e3101fff] size 0x00002000 gran 0x0d mem64 +PCI: 00:1d.0 10 <- [0x00e3227000 - 0x00e32273ff] size 0x00000400 gran 0x0a mem +PNP: 004e.4 60 <- [0x0000000295 - 0x000000029c] size 0x00000008 gran 0x03 io +PNP: 004e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq +PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 004e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +PNP: 004e.6 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq +PNP: 004e.6 c1 <- [0x000000003f - 0x000000003e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 c5 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 ce <- [0x00000000e0 - 0x00000000df] size 0x00000000 gran 0x00 irq +PNP: 004e.6 cf <- [0x0000000040 - 0x000000003f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d0 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d1 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d3 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 e1 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 f1 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq +PNP: 004e.7 60 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io +PNP: 004e.7 f6 <- [0x0000000a00 - 0x00000009ff] size 0x00000000 gran 0x00 io +PNP: 004e.7 30 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PNP: 004e.7 f0 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 irq +PNP: 004e.a 30 <- [0x0000000001 - 0x0000000000] size 0x00000000 gran 0x00 irq +PNP: 004e.a e0 <- [0x0000000010 - 0x000000000f] size 0x00000000 gran 0x00 irq +PNP: 004e.a f4 <- [0x0000000004 - 0x0000000003] size 0x00000000 gran 0x00 irq +PNP: 004e.a f8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PNP: 004e.a f9 <- [0x0000000009 - 0x0000000008] size 0x00000000 gran 0x00 irq +PNP: 004e.a fa <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PCI: 00:1f.2 10 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000002050 - 0x0000002053] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x0000002054 - 0x0000002057] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00e3225000 - 0x00e32257ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00e3228000 - 0x00e32280ff] size 0x00000100 gran 0x08 mem64 +Done setting resources. +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 1040 exit 0 +Enabling resources... +PCI: 00:00.0 subsystem <- 1462/7707 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 bridge ctrl <- 000b +PCI: 00:01.0 subsystem <- 1462/7707 +PCI: 00:01.0 cmd <- 07 +PCI: 00:16.0 subsystem <- 1462/7707 +PCI: 00:16.0 cmd <- 02 +PCI: 00:19.0 subsystem <- 1462/7707 +PCI: 00:19.0 cmd <- 103 +PCI: 00:1a.0 subsystem <- 1462/7707 +PCI: 00:1a.0 cmd <- 102 +PCI: 00:1b.0 subsystem <- 1462/7707 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 1462/7707 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 1462/7707 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1d.0 subsystem <- 1462/7707 +PCI: 00:1d.0 cmd <- 102 +pch_decode_init +PCI: 00:1f.0 subsystem <- 1462/7707 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 1462/7707 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 1462/7707 +PCI: 00:1f.3 cmd <- 103 +PCI: 01:00.0 cmd <- 03 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 0 usecs +CPU_CLUSTER: 0 init ... +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 +0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +0x0000000100000000 - 0x0000000175000000 size 0x75000000 type 6 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 4/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 +MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 +MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU has 4 cores, 4 threads enabled. +Setting up SMI for CPU +Will perform SMM setup. +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 13380 size 6800 +microcode: sig=0x206a7 pf=0x2 revision=0x2e +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 +Processing 16 relocs. Offset value of 0x00030000 +Attempting to start 3 APs +Waiting for 10ms after sending INIT. +Waiting for 1st SIPI to complete...done. +Waiting for 2nd SIPI to complete...done. +AP: slot 1 apic_id 2. +AP: slot 2 apic_id 4. +AP: slot 3 apic_id 6. +Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 +Processing 13 relocs. Offset value of 0x00038000 +SMM Module: stub loaded at 00038000. Will call 7ffa3c4d(00000000) +Installing SMM handler to 0x80000000 +Loading module at 80010000 with entry 80010112. filesize: 0x1048 memsize: 0x5068 +Processing 40 relocs. Offset value of 0x80010000 +Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 +Processing 13 relocs. Offset value of 0x80008000 +SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd +SMM Module: placing jmp sequence at 80007800 rel16 0x07fd +SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd +SMM Module: stub loaded at 80008000. Will call 80010112(00000000) +Initializing Southbridge SMI... + +New SMBASE 0x80000000 +In relocation handler: cpu 0 +New SMBASE=0x80000000 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffffc00 +In relocation handler: cpu 1 +New SMBASE=0x7ffffc00 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffff400 +In relocation handler: cpu 3 +New SMBASE=0x7ffff400 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffff800 +In relocation handler: cpu 2 +New SMBASE=0x7ffff800 IEDBASE=0x80400000 +microcode: Update skipped, already up-to-date +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +microcode: Update skipped, already up-to-date +microcode: updated to revision 0x2e date=2018-04-10 +microcode: updated to revision 0x2e date=2018-04-10 +Initializing CPU #0 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: platform id 1 +CPU: cpuid(1) 0x206a7 +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +Setting up local APIC... apic_id: 0x00 done. +VMX status: enabled +IA32_FEATURE_CONTROL status: locked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +Turbo is available but hidden +Turbo has been enabled +CPU #0 initialized +Initializing CPU #3 +Initializing CPU #2 +Initializing CPU #1 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +Enabling cache +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: platform id 1 +CPU: platform id 1 +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: cpuid(1) 0x206a7 +CPU: platform id 1 +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +CPU: cpuid(1) 0x206a7 +CPU: cpuid(1) 0x206a7 +Setting up local APIC...CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported + apic_id: 0x04 done. +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +Setting up local APIC...Setting up local APIC...VMX status: enabled + apic_id: 0x02 done. +IA32_FEATURE_CONTROL status: locked +VMX status: enabled + apic_id: 0x06 done. +IA32_FEATURE_CONTROL status: locked +VMX status: enabled +IA32_FEATURE_CONTROL status: locked +model_x06ax: energy policy set to 6 +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +CPU #2 initialized +CPU #1 initialized +model_x06ax: frequency set to 2800 +CPU #3 initialized +bsp_do_flight_plan done after 16 msecs. +Initializing southbridge SMI... +SMI_STS: +GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO1 +ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 +TCO_STS: +Locking SMM. +CPU_CLUSTER: 0 init finished in 29496 usecs +PCI: 00:00.0 init ... +Disabling PEG12. +Disabling PEG11. +Disabling IGD. +Disabling Device 4. +Disabling PEG60. +Disabling Device 7. +Set BIOS_RESET_CPL +CPU TDP: 95 Watts +PCI: 00:00.0 init finished in 1010 usecs +PCI: 00:01.0 init ... +PCI: 00:01.0 init finished in 1 usecs +PCI: 00:16.0 init ... +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : M0 with UMA +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : uKernel Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : Unknown 0x02 +ME: BIOS path: Normal +ME: Extend SHA-256: 286a9a97f425b427f5c26060982dffbd791397de171c1f63d77a81466114685d +ME: Firmware Version 7.0.1197.4 (code) 7.0.1197.4 (recovery) +ME Capability: Full Network manageability : disabled +ME Capability: Regular Network manageability : disabled +ME Capability: Manageability : disabled +ME Capability: Small business technology : disabled +ME Capability: Level III manageability : disabled +ME Capability: IntelR Anti-Theft (AT) : disabled +ME Capability: IntelR Capability Licensing Service (CLS) : enabled +ME Capability: IntelR Power Sharing Technology (MPC) : enabled +ME Capability: ICC Over Clocking : enabled +ME Capability: Protected Audio Video Path (PAVP) : disabled +ME Capability: IPV6 : disabled +ME Capability: KVM Remote Control (KVM) : disabled +ME Capability: Outbreak Containment Heuristic (OCH) : disabled +ME Capability: Virtual LAN (VLAN) : disabled +ME Capability: TLS : disabled +ME Capability: Wireless LAN (WLAN) : disabled +PCI: 00:16.0 init finished in 176416 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 0 usecs +PCI: 00:1a.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1a.0 init finished in 12 usecs +PCI: 00:1b.0 init ... +Azalia: base = e3220000 +Azalia: codec_mask = 09 +Azalia: Initializing codec #3 + codec not valid. +Azalia: Initializing codec #0 + codec not ready. +PCI: 00:1b.0 init finished in 6438 usecs +PCI: 00:1c.0 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.0 init finished in 9 usecs +PCI: 00:1c.1 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.1 init finished in 8 usecs +PCI: 00:1d.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1d.0 init finished in 12 usecs +PCI: 00:1f.0 init ... +pch: lpc_init +PCH: detected P67, device id: 0x1c46, rev id 0x5 +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +Set power on after power failure. +NMI sources disabled. +CougarPoint PM init +RTC: failed = 0x0 +RTC Init +Disabling ACPI via APMC: +done. +pch_spi_init +PCI: 00:1f.0 init finished in 236 usecs +PCI: 00:1f.2 init ... +SATA: Initializing... +SATA: Controller in AHCI mode. +ABAR: e3225000 +PCI: 00:1f.2 init finished in 72 usecs +PCI: 00:1f.3 init ... +PCI: 00:1f.3 init finished in 7 usecs +PCI: 01:00.0 init ... +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000000 +Copying VGA ROM Image from e3000000 to 0xc0000, 0xf200 bytes +Calling Option ROM... +Unsupported software interrupt #0x15 eax 0x5f14 +... Option ROM returned. +VBE: Getting information about VESA mode 4115 +VBE: resolution: 800x600@32 +VBE: framebuffer: e1000000 +VBE: Setting VESA mode 4115 +VGA Option ROM was run +PCI: 01:00.0 init finished in 4530635 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 0 usecs +PNP: 004e.4 init ... +PNP: 004e.4 init finished in 69 usecs +PNP: 004e.5 init ... +PNP: 004e.5 init finished in 1 usecs +PNP: 004e.6 init ... +PNP: 004e.6 init finished in 1 usecs +PNP: 004e.7 init ... +PNP: 004e.7 init finished in 1 usecs +PNP: 004e.a init ... +PNP: 004e.a init finished in 1 usecs +Devices initialized +BS: BS_DEV_INIT times (us): entry 6 run 4744434 exit 0 +Finalize devices... +PCI: 00:1f.0 final +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 13170 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset 32b80 size 2526 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at 7ff4f000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +Generating ACPI PIRQ entries +Found 1 CPU(s) with 4 core(s) each. +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000001 +Incorrect expansion ROM header signature 78aa +PCI: 01:00.0: Missing PCI Option ROM +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = 7ff53080 +ACPI: * HPET +ACPI: added table 5/32, length now 56 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000001 +Incorrect expansion ROM header signature 78aa +ACPI: done. +ACPI tables: 16576 bytes. +smbios_write_tables: 7ff4d000 +Create SMBIOS type 17 +SMBIOS tables: 558 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fe7 +Writing coreboot table at 0x7ff73000 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000fffff: RESERVED + 3. 0000000000100000-000000001fffffff: RAM + 4. 0000000020000000-00000000201fffff: RESERVED + 5. 0000000020200000-000000003fffffff: RAM + 6. 0000000040000000-00000000401fffff: RESERVED + 7. 0000000040200000-000000007ff4cfff: RAM + 8. 000000007ff4d000-000000007ff8bfff: CONFIGURATION TABLES + 9. 000000007ff8c000-000000007ffcdfff: RAMSTAGE +10. 000000007ffce000-000000007fffffff: CONFIGURATION TABLES +11. 0000000080000000-000000008a7fffff: RESERVED +12. 00000000f0000000-00000000f3ffffff: RESERVED +13. 0000000100000000-0000000174ffffff: RAM +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +Wrote coreboot table at: 7ff73000, 0x38c bytes, checksum 1f06 +coreboot table: 932 bytes. +IMD ROOT 0. 7ffff000 00001000 +IMD SMALL 1. 7fffe000 00001000 +CONSOLE 2. 7ffde000 00020000 +TIME STAMP 3. 7ffdd000 00000910 +MRC DATA 4. 7ffdc000 000005d4 +ROMSTG STCK 5. 7ffd7000 00005000 +AFTER CAR 6. 7ffce000 00009000 +RAMSTAGE 7. 7ff8b000 00043000 +SMM BACKUP 8. 7ff7b000 00010000 +COREBOOT 9. 7ff73000 00008000 +ACPI 10. 7ff4f000 00024000 +ACPI GNVS 11. 7ff4e000 00001000 +SMBIOS 12. 7ff4d000 00000800 +IMD small region: + IMD ROOT 0. 7fffec00 00000400 + MEM INFO 1. 7fffea40 000001a9 + ROMSTAGE 2. 7fffea20 00000004 + COREBOOTFWD 3. 7fffe9e0 00000028 +BS: BS_WRITE_TABLES times (us): entry 0 run 3842 exit 0 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 35100 size af0b1 +Checking segment from ROM address 0xffe45338 +Checking segment from ROM address 0xffe45354 +Loading segment from ROM address 0xffe45338 + code (compression=1) + New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xffe45370 filesize 0xaf079 +Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000af079 +using LZMA +Loading segment from ROM address 0xffe45354 + Entry Point 0x008008f0 +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 269229 exit 0 +PCH: watchdog disabled +Jumping to boot code at 008008f0(7ff73000) + diff --git a/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt b/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt new file mode 100644 index 0000000..2bb51dd --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt @@ -0,0 +1,9 @@ + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- 08 -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- 32 -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: 50 -- 52 -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- diff --git a/Documentation/mainboard/medion/ms_7707/logs/superiotool.log b/Documentation/mainboard/medion/ms_7707/logs/superiotool.log new file mode 100644 index 0000000..0540f1f --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/superiotool.log @@ -0,0 +1,290 @@ +superiotool r4.9-1191-geb789f0b79 +Found Fintek F71808A (vid=0x3419, id=0x0110) at 0x4e +Register dump: +idx val def +0x02: 0x00 (0x00) +0x07: 0x0a (0x00) +0x20: 0x10 (0x10) +0x21: 0x01 (0x01) +0x23: 0x19 (0x19) +0x24: 0x34 (0x34) +0x25: 0x00 (0x00) +0x26: 0x00 (0x00) +0x27: 0x10 (MM) +0x28: 0x00 (0x00) +0x29: 0xc0 (0xc0) +0x2a: 0x20 (0x21) +0x2b: 0x4f (0x2f) +0x2c: 0x90 (0x5c) +0x2d: 0x2f (0x27) + +LDN 0x01 (COM1) +idx val def +0x30: 0x00 (0x01) +0x60: 0x03 (0x03) +0x61: 0xf8 (0xf8) +0x70: 0x04 (0x04) +0xf0: 0x00 (0x00) + +LDN 0x04 (Hardware monitor) +idx val def +0x30: 0x01 (0x01) +0x60: 0x02 (0x02) +0x61: 0x95 (0x95) +0x70: 0x00 (0x00) + +LDN 0x05 (Keyboard) +idx val def +0x30: 0x01 (0x01) +0x60: 0x00 (0x00) +0x61: 0x60 (0x60) +0x70: 0x01 (0x01) +0x72: 0x0c (0x0c) +0xfe: 0x01 (0x01) +0xff: 0x29 (0x29) + +LDN 0x06 (GPIO) +idx val def +0x70: 0x00 (0x00) +0xc0: 0x00 (0x00) +0xc1: 0x3f (0x3f) +0xc2: 0x13 (NA) +0xc3: 0x00 (0x00) +0xc4: 0x00 (0x00) +0xc5: 0x1f (0x00) +0xc6: 0x03 (0x00) +0xcb: 0x00 (0x00) +0xcc: 0x00 (0x00) +0xcd: 0x00 (0x00) +0xce: 0xe0 (0xe0) +0xcf: 0x40 (0x40) +0xd0: 0x20 (0x00) +0xd1: 0x20 (0x00) +0xd2: 0xdb (NA) +0xd3: 0x20 (0x00) +0xd4: 0x00 (0x00) +0xd5: 0x00 (0x00) +0xd6: 0x18 (0x00) +0xd7: 0x00 (0x00) +0xd8: 0x00 (0x00) +0xe0: 0x00 (0x00) +0xe1: 0x1f (0x1f) +0xe2: 0x17 (NA) +0xe3: 0x00 (0x00) +0xf0: 0x00 (0x00) +0xf1: 0xff (0xff) +0xf2: 0xe7 (NA) +0xf3: 0x00 (0x00) + +LDN 0x07 (WDT) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0xf0: 0x03 (0x03) +0xf2: 0xff (NA) +0xf3: 0xff (NA) +0xf4: 0xff (NA) +0xf5: 0x00 (0x00) +0xf6: 0x0a (0x0a) +0xf7: 0x00 (0x00) + +LDN 0x08 (CIR) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x70: 0x00 (0x00) +0xf0: 0x00 (NA) +0xf1: 0x00 (NA) +0xf8: 0x00 (0x00) +0xf9: 0x00 (0x00) +0xfa: 0x80 (0x80) +0xfb: 0x3b (0x3b) +0xfc: 0x00 (0x00) +0xfd: 0x00 (0x00) +0xfe: 0x00 (0x00) + +LDN 0x0a (PME, ACPI, and EUP Power Saving) +idx val def +0x30: 0x01 (0x00) +0xe0: 0x10 (0x10) +0xe1: 0xcc (0xcc) +0xe2: 0x0c (0x0c) +0xe3: 0x13 (0x13) +0xe4: 0x09 (0x09) +0xe5: 0xc7 (0xc7) +0xe6: 0x09 (0x09) +0xe7: 0x63 (0x63) +0xe8: 0x00 (0x00) +0xe9: 0x0f (0x0f) +0xec: 0x00 (0x00) +0xed: 0xc0 (0x00) +0xee: 0x00 (0x00) +0xf0: 0x00 (0x00) +0xf1: 0x20 (NA) +0xf2: 0x00 (0x00) +0xf3: 0x02 (NA) +0xf4: 0x04 (0x06) +0xf5: 0x3c (0x3c) +0xf6: 0x1f (0x1f) +0xf7: 0x00 (0x00) +0xf8: 0x00 (0x00) +0xf9: 0x09 (0x00) +0xfa: 0x00 (0x00) +0xfd: 0xff (NA) + +Hardware monitor (0x0295) +Register dump: +idx val def +0x01: 0x03 (0x03) +0x02: 0x00 (0x00) +0x03: 0x01 (0x01) +0x08: 0x4c (0x4c) +0x0a: 0x00 (0x00) +0x0b: 0x00 (0x00) +0x0c: 0x55 (0x55) +0x0d: 0x00 (0x00) +0x0f: 0x20 (0x20) +0x20: 0xca (NA) +0x21: 0x81 (NA) +0x22: 0xff (NA) +0x23: 0xff (NA) +0x24: 0xff (RR) +0x25: 0xff (RR) +0x26: 0xff (RR) +0x27: 0xc9 (NA) +0x28: 0xda (NA) +0x29: 0xff (RR) +0x2a: 0xff (RR) +0x2b: 0xff (RR) +0x2c: 0xff (RR) +0x2d: 0x80 (NA) +0x2e: 0x8a (NA) +0x2f: 0x7f (NA) +0x40: 0x44 (0x44) +0x41: 0x00 (0x00) +0x42: 0x00 (NA) +0x43: 0x00 (0x00) +0x44: 0x00 (0x00) +0x45: 0x00 (0x00) +0x46: 0x00 (0x00) +0x47: 0x00 (0x00) +0x48: 0x00 (0x00) +0x49: 0x00 (0x00) +0x4a: 0x00 (0x00) +0x4b: 0x00 (0x00) +0x4c: 0x00 (0x00) +0x4d: 0x00 (0x00) +0x4e: 0x00 (0x00) +0x4f: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x64: 0x00 (0x00) +0x66: 0x02 (0x02) +0x6b: 0x06 (0x06) +0x6c: 0x40 (0x40) +0x6d: 0x04 (0x04) +0x6f: 0x00 (0x00) +0x7f: 0x00 (0x00) +0x70: 0xff (RR) +0x71: 0xff (RR) +0x72: 0x19 (NA) +0x73: 0xff (RR) +0x74: 0x22 (NA) +0x75: 0xff (RR) +0x76: 0xff (RR) +0x77: 0xff (RR) +0x78: 0xff (NA) +0x79: 0xff (NA) +0x7a: 0x00 (NA) +0x7b: 0x00 (NA) +0x7c: 0x00 (NA) +0x7d: 0x00 (RR) +0x7e: 0x00 (RR) +0x80: 0xff (RR) +0x81: 0xff (RR) +0x82: 0x64 (NA) +0x83: 0x55 (NA) +0x84: 0x64 (NA) +0x85: 0x55 (NA) +0x86: 0xff (RR) +0x87: 0xff (RR) +0x88: 0xff (RR) +0x89: 0xff (RR) +0x8a: 0xff (RR) +0x8b: 0xff (RR) +0x8c: 0xff (RR) +0x8d: 0xff (RR) +0x90: 0x00 (0x00) +0x91: 0x06 (NA) +0x92: 0x06 (NA) +0x93: 0x00 (0x00) +0x94: 0x2a (0x2e) +0x95: 0xff (0xff) +0x96: 0x05 (0x05) +0x98: 0x44 (0x44) +0x9b: 0x05 (0x05) +0x9c: 0x55 (0x55) +0x9e: 0x66 (0x66) +0x9f: 0x00 (0x00) +0xa0: 0x05 (0x03) +0xa1: 0x7d (0xff) +0xa2: 0x00 (0x00) +0xa3: 0x80 (0x83) +0xa4: 0x03 (0x03) +0xa5: 0xff (0xff) +0xa6: 0x3c (0x3c) +0xa7: 0x32 (0x32) +0xa8: 0x28 (0x28) +0xa9: 0x1e (0x1e) +0xaa: 0xff (0xff) +0xab: 0xd9 (0xd9) +0xac: 0xb2 (0xb2) +0xad: 0x99 (0x99) +0xae: 0x80 (0x80) +0xaf: 0x1d (0x1d) +0xb0: 0x0f (0x0c) +0xb1: 0xff (0x25) +0xb2: 0x00 (0x00) +0xb3: 0x8a (0x80) +0xb4: 0x03 (0x03) +0xb5: 0xff (0xff) +0xb6: 0x3c (0x3c) +0xb7: 0x32 (0x32) +0xb8: 0x28 (0x28) +0xb9: 0x1e (0x1e) +0xba: 0xff (0xff) +0xbb: 0xd9 (0xd9) +0xbc: 0xb2 (0xb2) +0xbd: 0x99 (0x99) +0xbe: 0x80 (0x80) +0xbf: 0x1e (0x1e) +0xc0: 0x0f (0x0f) +0xc1: 0xff (0xff) +0xc2: 0xff (RR) +0xc3: 0x7f (0x7f) +0xc4: 0xff (RR) +0xc5: 0xff (RR) +0xc6: 0xff (RR) +0xc7: 0xff (RR) +0xc8: 0xff (RR) +0xc9: 0xff (RR) +0xca: 0xff (RR) +0xcb: 0xff (RR) +0xcc: 0xff (RR) +0xcd: 0xff (RR) +0xce: 0xff (RR) +0xcf: 0x00 (0x00) +0xe0: 0x00 (NA) +0xe1: 0x00 (NA) +0xe2: 0x00 (NA) +0xe3: 0x00 (NA) +0xe4: 0x00 (NA) +0xec: 0x00 (0x00) +0xed: 0x01 (0x01) +0xee: 0x01 (0x01) +0xef: 0x00 (0x00) + diff --git a/Documentation/mainboard/medion/ms_7707/ms-7707.md b/Documentation/mainboard/medion/ms_7707/ms-7707.md new file mode 100644 index 0000000..3b79dca --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/ms-7707.md @@ -0,0 +1,34 @@ +# MSI MS-7707 V1.1 + +## Specifications + +MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) +SandyBridge Intel P67 (BD82x6x) +Winbond 25Q32BV (4MB) +Fintek F71808A +Intel 82579V Gigabit +NEC uPD720200 USB 3.0 Host Controller +IME 7.0.4.1197 + +## Working +- Tested on Arch Linux 5.0.5 +- PCIe gfx adapter +- PS/2 Keyboard +- USB3.0 +- coreboot 4.9 (TianoCore) +- S0/S5 states +- H/W FAN control (proper HWM function not checked though) + +## Known issues + +- S0/S5 states work properly as long as the board gets powered. After power cut the system is dead. Needs battery removal and CMOSCLR to revive. SuperIO is supposed to be in an unknown state as current coreboot SuperIO initialization isn't able to set all registers (see cbmem.log - skipping PNP: 004e.a@e0 fixed resource, size=0!). + +## Resources + +- [BIOS ROM] +- [Fintek F71808A datasheet] +- [Winbond 25Q32BV datasheet] + +[BIOS ROM]: https://www.medion.com/de/servicebackend/_lightbox/treiber_details.php?did=… +[Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html -- To view, visit https://review.coreboot.org/c/coreboot/+/32236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Gerrit-Change-Number: 32236 Gerrit-PatchSet: 1 Gerrit-Owner: Bluemax Gerrit-MessageType: newchange

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coreboot-gerrit April 2019