April 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs

by Kyösti Mälkki (Code Review)

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31361 to review the following change. Change subject: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs ...................................................................... [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise CAR_GLOBALs may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all. Does not fix family14. Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/gcccar.inc M src/vendorcode/amd/agesa/f14/gcccar.inc M src/vendorcode/amd/agesa/f15tn/gcccar.inc M src/vendorcode/amd/agesa/f16kb/gcccar.inc 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1 diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02a..e96c7f7 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1767,6 +1767,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d97..26745c9 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1131,6 +1131,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/31361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Gerrit-Change-Number: 31361 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 month, 4 weeks

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Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE

by Krystian Hebel (Code Review)

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363 Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE ...................................................................... /mainboard/pcengines/apu2: implement POSTCAR_STAGE As in [1], POSTCAR_STAGE will be required since October 2019. [1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/... Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf --- M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc M src/mainboard/pcengines/apu2/OemCustomize.c A src/mainboard/pcengines/apu2/postcar.c M src/mainboard/pcengines/apu2/romstage.c A src/mainboard/pcengines/apu2/state_machine.c 7 files changed, 213 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1 diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a..0178018 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -16,6 +16,7 @@ #include <AGESA.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> #include <stdlib.h> @@ -23,7 +24,6 @@ #include "imc.h" #include "hudson.h" -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -34,8 +34,7 @@ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -56,75 +55,66 @@ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams) { - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + printk(BIOS_DEBUG, "Done\n"); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) +{ + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; + FchParams->Azalia.AzaliaEnable = AzDisable; - /* Fan Control */ - oem_fan_control(FchParams); + /* Fan Control */ + oem_fan_control(FchParams); - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; - /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(BOARD_PCENGINES_APU2)) { - // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = FALSE; - } else { - // Enable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = TRUE; - } + if (CONFIG(BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } - // Enable EHCI 1 (port 4 to 7) - // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. - FchParams->Usb.Ehci2Enable = TRUE; + // Enable EHCI 1 (port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; - /* sata configuration */ - FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP - FchParams->Sata.SataDevSlpPort1 = 0; + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; } printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b..28f9eb8 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e..7824996 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,10 +14,14 @@ # GNU General Public License for more details. # +romstage-y += state_machine.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +postcar-y += postcar.c + +ramstage-y += state_machine.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 700f4c7..7ef7e00 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -14,7 +14,7 @@ */ #include <AGESA.h> -#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -76,25 +76,7 @@ .DdiLinkList = NULL, }; -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c new file mode 100644 index 0000000..b57ea94 --- /dev/null +++ b/src/mainboard/pcengines/apu2/postcar.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> + +void late_car_teardown(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index bd3c421..a6fe713 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -40,9 +40,11 @@ static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + pci_devfn_t dev; + u32 data; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -57,51 +59,32 @@ hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - pci_devfn_t dev; - u32 data; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + post_code(0x30); + early_lpc_init(); - post_code(0x30); - early_lpc_init(); + hudson_clk_output_48Mhz(); + post_code(0x31); - hudson_clk_output_48Mhz(); - post_code(0x31); + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + console_init(); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); @@ -112,27 +95,17 @@ val |= (1 << 30); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - - timestamp_add_now(TS_BEFORE_INITRAM); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); - - timestamp_add_now(TS_AFTER_INITRAM); } -void agesa_postcar(struct sysinfo *cb) -{ - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); +//~ void agesa_postcar(struct sysinfo *cb) +//~ { + //~ //PspMboxBiosCmdDramInfo(); + //~ post_code(0x41); + //~ AGESAWRAPPER(amdinitenv); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -} + //~ outb(0xEA, 0xCD6); + //~ outb(0x1, 0xcd7); +//~ } static void early_lpc_init(void) { diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c new file mode 100644 index 0000000..4a10df9 --- /dev/null +++ b/src/mainboard/pcengines/apu2/state_machine.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> +#include <binaryPI/FieldAccessors.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} + +AGESA_STATUS +AmdGetValue ( + IN CONST AGESA_FIELD_NAME name, + IN OUT VOID** value, + IN UINT32 size + ) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Gerrit-Change-Number: 32363 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

1 month, 4 weeks

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Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER

by Krystian Hebel (Code Review)

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421 Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER ...................................................................... nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI wrapper to use new interface for dispatcher. Tested only on 00730F01 (apu2) - no other platforms available. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/state_machine.c 5 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..c64a7ba 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1006,3 +1009,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..08dfd84 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -991,3 +994,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c..f69f226 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,6 +40,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1242,3 +1244,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..349761b 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += agesawrapper.c ramstage-y += agesawrapper.c +else +romstage-y += state_machine.c +ramstage-y += state_machine.c endif romstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c new file mode 100644 index 0000000..f42e97f --- /dev/null +++ b/src/northbridge/amd/pi/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2019 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Gerrit-Change-Number: 32421 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

2 months

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Change in ...coreboot[master]: nb/intel/i945: Correct mask for CxDRT1

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31144 Change subject: nb/intel/i945: Correct mask for CxDRT1 ...................................................................... nb/intel/i945: Correct mask for CxDRT1 [27:24] and [31:30] are reserved, so we shouldn't change them. Tested on i945G-M4 board. Change-Id: I0cac9160c756405838706edb0461575241faae35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31144/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..2a62ca3 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1475,7 +1475,7 @@ /* Calculate DRT1 */ - temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; /* DRAM RASB Precharge */ temp_drt |= (sysinfo->trp - 2) << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cac9160c756405838706edb0461575241faae35 Gerrit-Change-Number: 31144 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 months

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Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069 Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code ...................................................................... nb/intel/sandybridge: Fill common MRC settings in northbridge code Fill northbridge and southbridge BARs in raminit code. Allows to drop duplicated code from mainboard directories. Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7a..c544a74 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -275,6 +275,24 @@ u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -286,6 +304,7 @@ enable_usb_bar(); mainboard_fill_pei_data(&pei_data); + northbridge_fill_pei_data(&pei_data); post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Gerrit-Change-Number: 32069 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 months

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Change in ...coreboot[master]: ec/quanta/it8518: Use ACPI EC code

by James (Code Review)

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31382 Change subject: ec/quanta/it8518: Use ACPI EC code ...................................................................... ec/quanta/it8518: Use ACPI EC code ec/quanta/it8518 implements its own code for reading and writing the EC. As a result, it cannot be used with ec/acpi. ec/quanta/it8518 contains definitions that are useful for mb/thinkpad/x131e, however, x131e uses ec/acpi. This replaces functions and definitions in ec/quanta/it8518 with their equivalents in ec/acpi. TODO: test on google/stout Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/ec/quanta/it8518/Kconfig M src/ec/quanta/it8518/ec.c M src/ec/quanta/it8518/ec.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c 8 files changed, 17 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31382/1 diff --git a/src/ec/quanta/it8518/Kconfig b/src/ec/quanta/it8518/Kconfig index 24ac36f..caaccd5 100644 --- a/src/ec/quanta/it8518/Kconfig +++ b/src/ec/quanta/it8518/Kconfig @@ -1,4 +1,5 @@ config EC_QUANTA_IT8518 + select EC_ACPI bool help Interface to QUANTA IT8518 Embedded Controller. diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index e293f7c..a27e7b9 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -19,6 +19,7 @@ #include <delay.h> #include <device/device.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdlib.h> @@ -93,48 +94,16 @@ * These functions are for accessing the IT8518 device RAM space via 0x66/0x68 */ -u8 ec_read_ob(void) -{ - if (!output_buffer_full(EC_SC)) return 0; - return inb(EC_DATA); -} - -void ec_write_cmd(u8 cmd) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(cmd, EC_SC); -} - -void ec_write_ib(u8 data) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(data, EC_DATA); -} - -u8 ec_read(u16 addr) -{ - ec_write_cmd(RD_EC); - ec_write_ib(addr); - return ec_read_ob(); -} - -void ec_write(u16 addr, u8 data) -{ - ec_write_cmd(WR_EC); - ec_write_ib(addr); - ec_write_ib(data); -} - #ifndef __PRE_RAM__ u8 ec_it8518_get_event(void) { u8 cmd = 0; u8 status = inb(EC_SC); - if (status & SCI_EVT) { - ec_write_cmd(QR_EC); - cmd = ec_read_ob(); - } else if (status & SMI_EVT) { + if (status & EC_SCI_EVT) { + send_ec_command(QR_EC); + cmd = recv_ec_data(); + } else if (status & EC_SMI_EVT) { ec_kbc_write_cmd(EC_KBD_SMI_EVENT); cmd = ec_kbc_read_ob(); } diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 6fca3b9..27f9137 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -43,17 +43,6 @@ void ec_kbc_write_cmd(u8 cmd); void ec_kbc_write_ib(u8 data); -// 62h/66h Command Interface -#define EC_DATA 0x62 -#define EC_SC 0x66 // Status & Control Register -#define SMI_EVT (1 << 6) // 1: SMI event was triggered -#define SCI_EVT (1 << 5) // 1: SCI event was triggered - -// EC Commands (defined in ec_function_spec v3.12) -#define RD_EC 0x80 -#define WR_EC 0x81 -#define QR_EC 0x84 - #define EC_CMD_EXIT_BOOT_BLOCK 0x85 #define EC_CMD_NOTIFY_ACPI_ENTER 0x86 #define EC_CMD_NOTIFY_ACPI_EXIT 0x87 @@ -63,13 +52,13 @@ #define EC_PERIPH_CNTL_3 0x0D #define EC_USB_S3_EN 0x26 #define EC_PERIPH_STAT_3 0x35 +#define EC_MBAT_STATUS 0x38 #define EC_THERM_0 0x78 #define EC_WAKE_SRC_ENABLE 0xBF #define EC_FW_VER 0xE8 // 2 Bytes #define EC_IF_MIN_VER 0xEB #define EC_STATUS_REG 0xEC #define EC_IF_MAJ_VER 0xEF -#define EC_MBAT_STATUS 0x0138 // EC 0.83b added status bits: @@ -81,12 +70,6 @@ // EC 0.86a added enable bit: #define EC_LID_WAKE_ENABLE 0x4 -u8 ec_read_ob(void); -void ec_write_cmd(u8 cmd); -void ec_write_ib(u8 data); - -u8 ec_read(u16 addr); -void ec_write(u16 addr, u8 data); u8 ec_it8518_get_event(void); void ec_it8518_enable_wake_events(void); diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 5301d30..f7f54c1 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -24,6 +24,7 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 229f919..11cdc2a 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index b63083f..63cc67b 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -29,13 +29,14 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { /* Stout EC needs to be put back in ACPI mode */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); } diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 6a51645..27eae19 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,6 +24,7 @@ #include <cpu/intel/model_206ax/model_206ax.h> /* Include EC functions */ +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -96,13 +97,13 @@ /* * TODO(kimarie) Clear all pending events and enable SCI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); break; case APMC_ACPI_DIS: /* * TODO(kimarie) Clear all pending events and enable SMI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_EXIT); + send_ec_command(EC_CMD_NOTIFY_ACPI_EXIT); break; } return 0; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d212951..66eb953 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,6 +29,7 @@ #include <southbridge/intel/common/gpio.h> #include <halt.h> #include <bootmode.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" #include "onboard.h" @@ -121,12 +122,12 @@ * Tell EC to exit RO mode */ printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); - ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); + send_ec_command(EC_CMD_EXIT_BOOT_BLOCK); die("wait for ec to reset"); } } else { printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); - ec_write_cmd(EC_CMD_WARM_RESET); + send_ec_command(EC_CMD_WARM_RESET); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Gerrit-Change-Number: 31382 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

2 months

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Change in ...coreboot[master]: mb/lenovo/x131e: function key support

by James (Code Review)

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31067 Change subject: mb/lenovo/x131e: function key support ...................................................................... mb/lenovo/x131e: function key support Enables function keys for X131e. The IT8518e EC of this board uses some different ACPI methods compared to the regular Lenovo H8. Add an option to use the alternative set of methods. Change-Id: Ib3a01f37a8b54889b55e92c501c9350e6c68bd57 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x131e/Makefile.inc M src/mainboard/lenovo/x131e/devicetree.cb A src/mainboard/lenovo/x131e/ec.h M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x131e/romstage.c A src/mainboard/lenovo/x131e/smihandler.c 9 files changed, 146 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31067/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f9b0b14..3dab615 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -28,6 +28,12 @@ Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot. +config H8_ALT_EC_QUERY + bool "Alternate ACPI EC query methods" + default n + help + Use alternative EC query methods for X131e + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..7c96504 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -140,7 +140,11 @@ /* Sleep Button pressed */ Method(_Q13, 0, NotSerialized) { +#ifndef CONFIG_H8_ALT_EC_QUERY Notify(^SLPB, 0x80) +#else + ^HKEY.RHK(0x04) +#endif } /* Brightness up GPE */ @@ -217,9 +221,20 @@ Method (_Q17, 0, NotSerialized) { +#ifndef CONFIG_H8_ALT_EC_QUERY ^HKEY.RHK (0x08) +#else + BRIGHTNESS_DOWN() +#endif } +#ifdef CONFIG_H8_ALT_EC_QUERY + Method (_Q18, 0, NotSerialized) + { + BRIGHTNESS_UP() + } +#endif + Method (_Q66, 0, NotSerialized) { ^HKEY.RHK (0x0A) diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 946b945..ee7a83f 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -8,6 +8,7 @@ select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_H8 + select H8_ALT_EC_QUERY select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00cce..2dab950 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 3d0148f..0a73010 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -47,7 +47,8 @@ chip southbridge/intel/bd82x6x # GPI routing - register "alt_gp_smi_en" = "0x0000" + register "alt_gp_smi_en" = "0x0002" + register "gpi1_routing" = "1" register "gpi6_routing" = "2" register "gpi13_routing" = "2" @@ -115,22 +116,10 @@ register "beepmask1" = "0x87" register "has_power_management_beeps" = "0" - register "event0_enable" = "0xff" - register "event1_enable" = "0xff" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xff" - register "event5_enable" = "0xff" - register "event6_enable" = "0xff" - register "event7_enable" = "0xff" - register "event8_enable" = "0xff" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0xff" - register "eventf_enable" = "0xff" + register "event2_enable" = "0xc8" # sleep, monitor, brightness down + register "event3_enable" = "0x01" # brightness up + register "eventc_enable" = "0x30" # airplane, camera + register "eventd_enable" = "0x04" # mic register "has_bdc_detection" = "0" diff --git a/src/mainboard/lenovo/x131e/ec.h b/src/mainboard/lenovo/x131e/ec.h new file mode 100644 index 0000000..4a731dc --- /dev/null +++ b/src/mainboard/lenovo/x131e/ec.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X131E_EC_H +#define X131E_EC_H + +#define GPE_EC_SCI 6 +#define GPE_EC_WAKE 13 + +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 + +#endif // X131E_EC_H diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..9e6a7dd 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -13,9 +13,17 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> +#include "ec.h" + +void mainboard_suspend_resume(void) +{ + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); +} static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..30df36f 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -26,11 +26,6 @@ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x131e/smihandler.c b/src/mainboard/lenovo/x131e/smihandler.c new file mode 100644 index 0000000..a634359 --- /dev/null +++ b/src/mainboard/lenovo/x131e/smihandler.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> +#include "ec.h" + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = ec_status(); + if (!(status & EC_SCI_EVT)) + return; + + u8 event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + send_ec_command(EC_CMD_NOTIFY_ACPI_EXIT); + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(EC_SC, EC_DATA); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } + + //outb(0xe9, 0x64); // EC_KBD_CMD_MUTE + //ec_set_bit(0xbf, 4); // EC_WAKE_SRC_ENABLE, EC_LID_WAKE_ENABLE +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a01f37a8b54889b55e92c501c9350e6c68bd57 Gerrit-Change-Number: 31067 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

2 months

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Change in ...coreboot[master]: payloads/ipxe: Enable HTTPS support

by Felix Singer (Code Review)

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31086 Change subject: payloads/ipxe: Enable HTTPS support ...................................................................... payloads/ipxe: Enable HTTPS support HTTPS needs a newer iPXE version than 2017.3, because it doesn't work with this release. Tested under master branch. Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31086/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..05b6f4dd 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Gerrit-Change-Number: 31086 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

2 months, 1 week

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Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 months, 1 week

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Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704 Change subject: device/hypertransport: Drop dev_find_slot() debugging ...................................................................... device/hypertransport: Drop dev_find_slot() debugging Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device.c M src/device/device_const.c M src/include/device/device.h 3 files changed, 5 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1 diff --git a/src/device/device.c b/src/device/device.c index 20a4077..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,7 +1253,4 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); - - if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index 480ac76..cdae33d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -177,15 +177,6 @@ * Work around the devicetree topology being manipulated on-the-fly * on systems with HyperTransport Support. */ - -static int ht_tree_needs_fixing, ht_tree_fixup_failed; - -void ht_report_devtree_sanity(void) -{ - printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", - ht_tree_needs_fixing, ht_tree_fixup_failed); -} - static const struct bus *ht_bus_reloc(const struct bus *parent, pci_devfn_t devfn) { @@ -222,34 +213,20 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; + const struct bus *root; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - dev = pcidev_path_behind(pci_domain->link_list, devfn); + root = pci_domain->link_list; /* Static devicetree with HyperTransport has whacky topology. */ - if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - return dev; + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + root = ht_bus_reloc(root, devfn); - DEVTREE_CONST struct device *dev_fixup, *dev_old_method; - - const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); - dev_fixup = pcidev_path_behind(root, devfn); - dev_old_method = dev_find_slot(0, devfn); - - if (ENV_RAMSTAGE) { - if (dev != dev_old_method) - ht_tree_needs_fixing++; - - if (dev_fixup != dev_old_method) - ht_tree_fixup_failed++; - } - - return dev_old_method; + return pcidev_path_behind(root, devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 40a0f58..540b7e3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,7 +227,6 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); -void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Gerrit-Change-Number: 30704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 months, 1 week

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coreboot-gerrit April 2019