April 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Use absolute jump address

by Nitheesh Sekar (Code Review)

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32388 Change subject: TEMP: NOT FOR REVIEW: Use absolute jump address ...................................................................... TEMP: NOT FOR REVIEW: Use absolute jump address When the qcs405 soc jumps from qc_sec to bootblock, the pc is at 0x0 address mapped to actual SRAM address(0x8c30000). The mapping happens in a hardware block 'boot-remapper' only for a maximum of 128K possible. If the bootflow continues from the 0x0 address, bootblock references variable beyond 128K crashing the boot. So change the PC to start execting from the absolute address instead. Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32388/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..7dc8b0f 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -23,7 +23,9 @@ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu + ldr x15, =arm64_init_cpu + blr x15 - bl main + ldr x15, =main + blr x15 ENDPROC(_start) -- To view, visit https://review.coreboot.org/c/coreboot/+/32388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Gerrit-Change-Number: 32388 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: google/mistrtal: Add board ID API.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31426 Change subject: google/mistrtal: Add board ID API. ...................................................................... google/mistrtal: Add board ID API. BUG=None TEST=Verified GPIO assignment and board ID values. BRANCH=None Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/boardid.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31426/1 diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index e9013af..ae418f2 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += chromeos.c bootblock-y += bootblock.c +verstage-y += boardid.c verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += verstage.c @@ -10,7 +11,9 @@ romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c new file mode 100644 index 0000000..f20960c --- /dev/null +++ b/src/mainboard/google/mistral/boardid.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> + +/* + * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106 + * and 107. + */ + +static uint32_t board_id_val = UNDEFINED_STRAPPING_ID; + +static uint32_t get_board_id(void) +{ + uint32_t bid; + const gpio_t pins[] = {[2] = GPIO(107), [1] = GPIO(106), [0] = GPIO(105)}; + + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint32_t board_id(void) +{ + if (board_id_val == UNDEFINED_STRAPPING_ID) + board_id_val = get_board_id(); + + return board_id_val; +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/31426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Gerrit-Change-Number: 31426 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: google/mistrtal: Setup required Chromeos GPIOs.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31459 Change subject: google/mistrtal: Setup required Chromeos GPIOs. ...................................................................... google/mistrtal: Setup required Chromeos GPIOs. Setup Flash write protect, recovery and h1 interrupt gpios to requires state at boot. BUG=None TEST=Verified GPIO state and its functionalities. BRANCH=None Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/bootblock.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31459/1 diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 6718d52..c72856d 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -15,8 +15,9 @@ #include <bootblock_common.h> #include <timestamp.h> +#include "board.h" void bootblock_mainboard_init(void) { - + setup_chromeos_gpios(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Gerrit-Change-Number: 31459 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31826 Change subject: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button ...................................................................... TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31826/1 diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h index 2e23ce3..51e4bf2 100644 --- a/src/mainboard/google/mistral/board.h +++ b/src/mainboard/google/mistral/board.h @@ -19,7 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> - +#define GPIO_DEV_STATE GPIO(45) #define GPIO_H1_AP_INT GPIO(53) #define GPIO_WP_STATE GPIO(54) #define GPIO_REC_STATE GPIO(77) diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 838691b..9b69a4f 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -24,11 +24,14 @@ { gpio_input(GPIO_WP_STATE); gpio_input(GPIO_REC_STATE); + gpio_input(GPIO_DEV_STATE); } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { + {GPIO_DEV_STATE.addr, ACTIVE_HIGH, + gpio_get(GPIO_DEV_STATE), "developer"}, {GPIO_REC_STATE.addr, ACTIVE_LOW, gpio_get(GPIO_REC_STATE), "recovery"}, {GPIO_WP_STATE.addr, ACTIVE_LOW, -- To view, visit https://review.coreboot.org/c/coreboot/+/31826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Gerrit-Change-Number: 31826 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: mb/google/mistral: Ignore REC switch if TPM isn't ready

by Patrick Georgi (Code Review)

Hello SANTHOSH JANARDHANA HASSAN, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32272 to review the following change. Change subject: mb/google/mistral: Ignore REC switch if TPM isn't ready ...................................................................... mb/google/mistral: Ignore REC switch if TPM isn't ready The recovery button's state is cached in the TPM, but on first boot Cr50 isn't ready yet for this task, which leads to a reboot further down the road (to get TPM up). To not confuse matters further, only act on the recovery button if the TPM is in fact able to cache the state. BUG=b:129878075 BRANCH=none TEST=recovery button is only read on second boot Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32272/1 diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 9b69a4f..e0306b16 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -72,6 +72,9 @@ gpio_t rec_sw; static enum switch_state saved_state = not_probed; + if (is_tpm_detected() == 0) + return saved_state; + if (saved_state != not_probed) return saved_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/32272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Gerrit-Change-Number: 32272 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW qcs405: Enable bl31

by Name of user not set (Code Review)

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31899 Change subject: TEMP: NOT FOR REVIEW qcs405: Enable bl31 ...................................................................... TEMP: NOT FOR REVIEW qcs405: Enable bl31 Keeping it seperate to include bl31.elf till we can build bl31 from repo Change-Id: Icca865369358e54a042b2dce02072c05761194b2 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/soc.c 3 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/31899/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..bf2f01b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -157,6 +157,8 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware @@ -235,6 +237,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif # CONFIG_SOC_QUALCOMM_QCS405 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 8c57f4a..b6ad8c2 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -107,4 +107,15 @@ @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin endif +################################################################################ +BL31_FILE := $(QCS405_BLOB)/bl31.elf +bl31_file := $(shell ls $(BL31_FILE)) +ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) + BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 + $(BL31_CBFS)-file := $(BL31_FILE) + $(BL31_CBFS)-type := payload + $(BL31_CBFS)-compression := none + cbfs-files-y += $(BL31_CBFS) +endif +################################################################################ endif diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index ea52eb8..e22a3d8 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -23,7 +23,7 @@ void bootmem_platform_add_ranges(void) { - bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); + bootmem_add_range((uintptr_t)_dram_reserved, REGION_SIZE(dram_reserved), BM_MEM_BL31); } static void soc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icca865369358e54a042b2dce02072c05761194b2 Gerrit-Change-Number: 31899 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM

by Name of user not set (Code Review)

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31898 Change subject: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM ...................................................................... TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM This patch adds support to select the board id based on the TPM availability. Change-Id: Ifa7b17085364bb631f43a133839773033721062d Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/drivers/spi/tpm/tis.c M src/drivers/spi/tpm/tpm.c M src/mainboard/google/mistral/boardid.c M src/security/tpm/tis.h M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h 6 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31898/1 diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 40bf27d..9d0f664 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -4,6 +4,8 @@ * found in the LICENSE file. */ +#include <symbols.h> +#include <soc/symbols.h> #include <arch/early_variables.h> #include <console/console.h> #include <string.h> @@ -93,3 +95,13 @@ return 0; } + +unsigned int is_tpm_detected(void) +{ + if (0 == (*_tpm_detection)) + return 0; + else if (1 == (*_tpm_detection)) + return 1; + else + return 0; +} diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index aad7610..b2484aa0 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -15,6 +15,8 @@ * Specification Revision 00.43". */ +#include <symbols.h> +#include <soc/symbols.h> #include <arch/early_variables.h> #include <assert.h> #include <commonlib/endian.h> @@ -457,10 +459,13 @@ } if (!retries) { + *_tpm_detection = 0; printk(BIOS_ERR, "\n%s: Failed to connect to the TPM\n", __func__); return -1; } + else + *_tpm_detection = 1; printk(BIOS_INFO, " done!\n"); diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c index b86f84e..66309c0 100644 --- a/src/mainboard/google/mistral/boardid.c +++ b/src/mainboard/google/mistral/boardid.c @@ -17,6 +17,7 @@ #include <gpio.h> #include <console/console.h> #include <stdlib.h> +#include <security/tpm/tis.h> /* * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106 @@ -32,8 +33,22 @@ [1] = GPIO(106), [0] = GPIO(105)}; - bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); - printk(BIOS_INFO, "Board ID %d\n", bid); + if (0 == is_tpm_detected()) { + bid = 25; /* Assign 25 for EVB boards */ + printk(BIOS_DEBUG, "EVB Board ID: %d\n", bid); + } else { + bid = 0; /* Assign 0 for Proto boards */ + + /* The board id assigned for Proto boards is 0. + * Since gpios are not wired in the initial phase, + * we will get 0 whihch is a coincidence. + * To make sure it starts working, after gpios are + * wired, reassign the value read from gpios to id. + */ + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_DEBUG, "Proto Board ID: %d\n", bid); + } return bid; } diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index c410838..dd2f348 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -97,4 +97,14 @@ */ int tis_plat_irq_status(void); +/* + * This function is_tpm_detected() sets tpm_detection value to be 1 upon TPM detection. + * The value is writted to the specific region of SRAM which will retain + * the TPM Detection information between various stages of the bootloader. + * + * Returns 0 if TPM is not detected + * Returns 1 if TPM is detected + */ +unsigned int is_tpm_detected(void); + #endif /* TIS_H_ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index c23f651..585abf5 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -39,6 +39,7 @@ TIMESTAMP(0x8C50000, 1K) PRERAM_CBMEM_CONSOLE(0x8C50400, 32K) PRERAM_CBFS_CACHE(0x8C58400, 70K) + REGION(tpm_detection, 0x8CFD000, 0x8, 0x10) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 45e6988..ce6e7cb 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -23,4 +23,8 @@ DECLARE_REGION(bsram); DECLARE_REGION(dram_reserved); +extern u8 _tpm_detection[]; +extern u8 _etpm_detection[]; +#define _tpm_detection_size (_etpm_detection - _tpm_detection) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/31898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa7b17085364bb631f43a133839773033721062d Gerrit-Change-Number: 31898 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: google/mistral: Support triggering Recovery/FDR.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31173 Change subject: google/mistral: Support triggering Recovery/FDR. ...................................................................... google/mistral: Support triggering Recovery/FDR. Implement triggering factory data reset and recovery mechanism based on Recovery/FDR switch(GPIO77) value. Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/mistral/verstage.c 4 files changed, 142 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31173/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index 5e97bb6..f28a382 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -23,6 +23,7 @@ select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY + select VBOOT_WIPEOUT_SUPPORTED config MAINBOARD_DIR string diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h new file mode 100644 index 0000000..2e23ce3 --- /dev/null +++ b/src/mainboard/google/mistral/board.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H + +#include <gpio.h> +#include <soc/gpio.h> + + +#define GPIO_H1_AP_INT GPIO(53) +#define GPIO_WP_STATE GPIO(54) +#define GPIO_REC_STATE GPIO(77) + +void setup_chromeos_gpios(void); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H */ diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index ba0b1da..0405c4e 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -14,11 +14,18 @@ */ #include <boot/coreboot_tables.h> -#include <gpio.h> #include <security/tpm/tis.h> -#include <soc/gpio.h> +#include <bootmode.h> +#include <timer.h> +#include <console/console.h> +#include "board.h" -#define GPIO_H1_AP_INT GPIO(53) +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input(GPIO_WP_STATE); + gpio_input(GPIO_REC_STATE); +} void fill_lb_gpios(struct lb_gpios *gpios) { @@ -27,9 +34,109 @@ {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, }; +#endif + struct lb_gpio chromeos_gpios[] = { + {GPIO_REC_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_REC_STATE), "recovery"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_WP_STATE), "write protect"}, + {-1, ACTIVE_LOW, 1, "power"}, + {-1, ACTIVE_LOW, 0, "lid"}, + }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -#endif +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +/* + * The recovery switch: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static enum switch_state get_rec_sw_state(void) +{ + struct stopwatch sw; + int sampled_value; + gpio_t rec_sw; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + rec_sw = GPIO_REC_STATE; + sampled_value = !gpio_get(rec_sw); + + if (!sampled_value) { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + //display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + //display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + //display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_rec_sw_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_rec_sw_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP_STATE); } #if 0 diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c index 7ea21c7..a63f61e 100644 --- a/src/mainboard/google/mistral/verstage.c +++ b/src/mainboard/google/mistral/verstage.c @@ -15,18 +15,10 @@ */ #include <console/console.h> -#include <gpio.h> #include <security/vboot/vboot_common.h> #include <spi-generic.h> #include <soc/clock.h> -#include <soc/gpio.h> - -#define GPIO_H1_AP_INT GPIO(53) - -static void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_H1_AP_INT); -} +#include "board.h" void verstage_mainboard_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Gerrit-Change-Number: 31173 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: google/mistral: add CR50

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30716 Change subject: google/mistral: add CR50 ...................................................................... google/mistral: add CR50 Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30716/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index b614a37..eddc1a3 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -14,6 +14,8 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MISSING_BOARD_RESET + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 config VBOOT select VBOOT_VBNV_FLASH @@ -29,6 +31,10 @@ string default "Google" +config DRIVER_TPM_SPI_BUS + hex + default 0x4 + ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -- To view, visit https://review.coreboot.org/c/coreboot/+/30716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Gerrit-Change-Number: 30716 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...coreboot[master]: google/mistral: Enable additional GBB flags in vboot.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31171 Change subject: google/mistral: Enable additional GBB flags in vboot. ...................................................................... google/mistral: Enable additional GBB flags in vboot. Enable GBB_FLAG_FORCE_MANUAL_RECOVERY and GBB_FLAG_DEV_SCREEN_SHORT_DELAY as additional default flags. Change-Id: If1e7effb2d74b861f196ce861a3c8779ce89b3b2 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31171/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index c369472..5e97bb6 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -20,7 +20,9 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 Gerrit-Change-Number: 31171 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

4 months, 3 weeks

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coreboot-gerrit April 2019