coreboot-gerrit March 2019

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Name of user not set (Code Review) 15 Mar '19

15 Mar '19

Hello mturney mturney, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29948 to look at the new patch set (#12). Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... soc/qualcomm/qcs405: Support for new SoC Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/soc/qualcomm/qcs405/Kconfig A src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/cbmem.c A src/soc/qualcomm/qcs405/include/soc/gpio.h A src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/soc.c A src/soc/qualcomm/qcs405/spi.c A src/soc/qualcomm/qcs405/timer.c 9 files changed, 284 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29948/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: device/pci_ops: Have only default PCI bus ops available
by Nico Huber (Code Review) 15 Mar '19

15 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31753 ) Change subject: device/pci_ops: Have only default PCI bus ops available ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Gerrit-Change-Number: 31753 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 14 Mar 2019 14:34:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/root_device: Scan bridges on LPC bus too
by Nico Huber (Code Review) 15 Mar '19

15 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device/root_device: Scan bridges on LPC bus too ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29474/5/src/device/root_device.c File src/device/root_device.c: https://review.coreboot.org/#/c/29474/5/src/device/root_device.c@66 PS5, Line 66: void scan_lpc_bus(struct device *bus) > Looks very much like scan_usb_bus() and root_dev_scan_bus(). Yep (the former sneaked into a rebase). I'll try to consolidate this. https://review.coreboot.org/#/c/29474/5/src/device/root_device.c@105 PS5, Line 105: link->secondary = ++bus_max; > This is weird, each path type (PCI/SMBus/LPC/xx) should have separate enumeration for the bus number […] Theoretically, yes. But does it matter in practice? I could implement something (based on the path type of the first child?). Same concerns about changing current, steady numbers, though. I'll have a closer look at the devicetrees currently in our tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 14 Mar 2019 13:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Fix PCI IO config accessor
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31847 ) Change subject: arch/x86: Fix PCI IO config accessor ...................................................................... arch/x86: Fix PCI IO config accessor In case PCI_IO_CFG_EXT=n parameter 'reg' was not properly truncated to 8 bits and it would overflow to dev.fn part of the register. A similar thing could happen with 'dev' but that value originates from PCI_DEV() macro unlike 'reg'. Change-Id: Id2888e07fc0f2b182b4633a747c1786e5c560678 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31847 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/pci_io_cfg.h 1 file changed, 15 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 6c88b3c..1e6934a 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -21,19 +21,22 @@ static __always_inline uint32_t pci_io_encode_addr(pci_devfn_t dev, uint16_t reg) { - if (CONFIG(PCI_IO_CFG_EXT)) { - // seg == 0 - return dev >> 4 | (reg & 0xff) | ((reg & 0xf00) << 16); - } else { - return dev >> 4 | reg; - } + uint32_t addr = 1 << 31; + + addr |= dev >> 4; + addr |= reg & 0xfc; + + if (CONFIG(PCI_IO_CFG_EXT)) + addr |= (reg & 0xf00) << 16; + + return addr; } static __always_inline uint8_t pci_io_read_config8(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); return inb(0xCFC + (reg & 3)); } @@ -41,7 +44,7 @@ uint16_t pci_io_read_config16(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); return inw(0xCFC + (reg & 2)); } @@ -49,7 +52,7 @@ uint32_t pci_io_read_config32(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); return inl(0xCFC); } @@ -57,7 +60,7 @@ void pci_io_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); outb(value, 0xCFC + (reg & 3)); } @@ -65,7 +68,7 @@ void pci_io_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); outw(value, 0xCFC + (reg & 2)); } @@ -73,7 +76,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(0x80000000 | (addr & ~3), 0xCF8); + outl(addr, 0xCF8); outl(value, 0xCFC); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2888e07fc0f2b182b4633a747c1786e5c560678 Gerrit-Change-Number: 31847 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/arcada: Update USB2 port6 AFE setting
by Lijian Zhao (Code Review) 14 Mar '19

14 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31632 Change subject: mb/google/arcada: Update USB2 port6 AFE setting ...................................................................... mb/google/arcada: Update USB2 port6 AFE setting Accoriding to 574354, we need to tune each port to pass eye diagram other than just use recommanded setting as they are base guidence only. Bug=b:124407280 TEST=Build and boot up on sarien board. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I587695809b368edd33852c4241de097ca31e9d66 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31632/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 244ba7a..cded5ff 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -125,7 +125,14 @@ register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth -- To view, visit https://review.coreboot.org/c/coreboot/+/31632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I587695809b368edd33852c4241de097ca31e9d66 Gerrit-Change-Number: 31632 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Define GPP_C13 as EC_SYNC_IRQ
by Philip Chen (Code Review) 14 Mar '19

14 Mar '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31814 Change subject: mb/google/hatch: Define GPP_C13 as EC_SYNC_IRQ ...................................................................... mb/google/hatch: Define GPP_C13 as EC_SYNC_IRQ BUG=b:125933998 BRANCH=None TEST=None Signed-off-by: Philip Chen <philipchen(a)google.com> Change-Id: I1dd38ca5aed1e0ddecb4738910cbfa92de33d315 --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31814/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index 75d583e..df05e88 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -78,6 +78,9 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index 0cdec46..5d6311b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -35,4 +35,7 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI +/* EC sync irq is GPP_C13_IRQ */ +#define EC_SYNC_IRQ GPP_C13_IRQ + #endif /* BASEBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd38ca5aed1e0ddecb4738910cbfa92de33d315 Gerrit-Change-Number: 31814 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: copy data structures to cbmem for downstream use
by Joel Kitching (Code Review) 14 Mar '19

14 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31329 Change subject: vboot: copy data structures to cbmem for downstream use ...................................................................... vboot: copy data structures to cbmem for downstream use For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot verification occurs before cbmem is brought online. In order to make vboot data structures available downstream, copy vb2_working_data from SRAM into cbmem when cbmem comes online. BUG=b:124141368, b:124192753 TEST=Build locally TEST=util/lint/checkpatch.pl --ignore GERRIT_CHANGE_ID -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I62c11268a83927bc00ae9bd93b1b31363b38e8cf Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/common.c 1 file changed, 32 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31329/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 747644a..8b73697 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -40,47 +40,32 @@ uint32_t buffer_size; }; -static const size_t vb_work_buf_size = 16 * KiB; +static struct vb2_working_data *vb2_wd = NULL; static struct vb2_working_data * const vboot_get_working_data(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - /* cbmem_add() does a cbmem_find() first. */ - return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); - else - return (struct vb2_working_data *)_vboot2_work; + if (vb2_wd == NULL) { +#if ENV_POSTCAR || ENV_RAMSTAGE + /* cbmem_find is linked from romstage onward */ + vb2_wd = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); +#else + /* _vboot2_work is accessible until end of romstage */ + vb2_wd = (struct vb2_working_data *)_vboot2_work; +#endif + } + assert(vb2_wd != NULL); + return vb2_wd; } static size_t vb2_working_data_size(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - return vb_work_buf_size; - else - return _vboot2_work_size; + /* _vboot2_work_size is accessible until end of romstage */ + return _vboot2_work_size; } static struct selected_region *vb2_selected_region(void) { - struct selected_region *sel_reg = NULL; - - /* Ramstage and postcar always uses cbmem as a source of truth. */ - if (ENV_RAMSTAGE || ENV_POSTCAR) - sel_reg = cbmem_find(CBMEM_ID_VBOOT_SEL_REG); - else if (ENV_ROMSTAGE) { - /* Try cbmem first. Fall back on working data if not found. */ - sel_reg = cbmem_find(CBMEM_ID_VBOOT_SEL_REG); - - if (sel_reg == NULL) { - struct vb2_working_data *wd = vboot_get_working_data(); - sel_reg = &wd->selected_region; - } - } else { - /* Stages such as bootblock and verstage use working data. */ - struct vb2_working_data *wd = vboot_get_working_data(); - sel_reg = &wd->selected_region; - } - - return sel_reg; + return &vboot_get_working_data()->selected_region; } void vb2_init_work_context(struct vb2_context *ctx) @@ -104,7 +89,6 @@ memset(ctx, 0, sizeof(*ctx)); ctx->workbuf = (void *)vb2_get_shared_data(); ctx->workbuf_size = wd->buffer_size; - } struct vb2_shared_data *vb2_get_shared_data(void) @@ -148,33 +132,30 @@ return reg->size > 0; } -void vb2_store_selected_region(void) +void vb2_store_working_data(void) { - const struct vb2_working_data *wd; - struct selected_region *sel_reg; + struct vb2_working_data *wd; + struct vb2_working_data *wd_cbmem; - /* Always use the working data in this path since it's the object - * which has the result.. */ + wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb2_working_data_size()); + assert(wd_cbmem != NULL); + +#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) wd = vboot_get_working_data(); + /* No data to copy yet on platforms with VBOOT_STARTS_IN_ROMSTAGE. */ + memcpy(wd_cbmem, wd, vb2_working_data_size()); +#endif - sel_reg = cbmem_add(CBMEM_ID_VBOOT_SEL_REG, sizeof(*sel_reg)); - - assert(sel_reg != NULL); - - sel_reg->offset = wd->selected_region.offset; - sel_reg->size = wd->selected_region.size; + vb2_wd = wd_cbmem; } /* - * For platforms that employ VBOOT_STARTS_IN_ROMSTAGE, the vboot - * verification doesn't happen until after cbmem is brought online. - * Therefore, the selected region contents would not be initialized - * so don't automatically add results when cbmem comes online. + * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot verification + * occurs before cbmem is brought online. In order to make vboot data + * structures available downstream, copy vb2_working_data from SRAM into cbmem. */ -#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) -static void vb2_store_selected_region_cbmem(int unused) +static void vb2_store_cbmem(int unused) { - vb2_store_selected_region(); + vb2_store_working_data(); } -ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_selected_region_cbmem) -#endif +ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_cbmem) -- To view, visit https://review.coreboot.org/c/coreboot/+/31329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62c11268a83927bc00ae9bd93b1b31363b38e8cf Gerrit-Change-Number: 31329 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Update vboot submodule to upstream master
by Joel Kitching (Code Review) 14 Mar '19

14 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31872 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 1e177741: 2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE) to commit id 304aa429: 2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags) This brings in 18 new commits. Change-Id: Ie2889ed0217c38734eb2c496ca20f95b6a12b102 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31872/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 1e17774..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 1e177741c3a9bfb8bd69a92b6d3bf4b25655a71f +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca -- To view, visit https://review.coreboot.org/c/coreboot/+/31872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2889ed0217c38734eb2c496ca20f95b6a12b102 Gerrit-Change-Number: 31872 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Optimise PCI IO config accessor
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31754 ) Change subject: arch/x86: Optimise PCI IO config accessor ...................................................................... arch/x86: Optimise PCI IO config accessor By design only 'reg' parameter can have the two least- significant bits set. As 'reg' is often a constant, '0xCFC + (reg & 3)' resolves to an immediate value already at buildtime, unlike (addr & 3) which depends of a constant (but non-immediate) value of 'dev' in ramstage. Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/pci_io_cfg.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 317c50a..6c88b3c 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -34,7 +34,7 @@ { uint32_t addr = pci_io_encode_addr(dev, reg); outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); + return inb(0xCFC + (reg & 3)); } static __always_inline @@ -42,7 +42,7 @@ { uint32_t addr = pci_io_encode_addr(dev, reg); outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); + return inw(0xCFC + (reg & 2)); } static __always_inline @@ -58,7 +58,7 @@ { uint32_t addr = pci_io_encode_addr(dev, reg); outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); + outb(value, 0xCFC + (reg & 3)); } static __always_inline @@ -66,7 +66,7 @@ { uint32_t addr = pci_io_encode_addr(dev, reg); outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + outw(value, 0xCFC + (reg & 2)); } static __always_inline -- To view, visit https://review.coreboot.org/c/coreboot/+/31754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958 Gerrit-Change-Number: 31754 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/mainboard/pcengines/apu2: Bring back copyrights
by Michał Żygowski (Code Review) 14 Mar '19

14 Mar '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31842 Change subject: src/mainboard/pcengines/apu2: Bring back copyrights ...................................................................... src/mainboard/pcengines/apu2: Bring back copyrights The copyright notices of Eltan B.V. have been removed by mistake before sending the patch with board support. Revert back to be consent with the license. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ic5948ab60a661ef78e4e5c8571535a096fc88ea5 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31842/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6e65a6e..8487612 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -2,7 +2,8 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki(a)gmail.com> +# Copyright (C) 2015 KyÃ¶sti MÃ¤lkki <kyosti.malkki(a)gmail.com> +# Copyright (C) 2016 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 0e89740..4e6364e 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -- To view, visit https://review.coreboot.org/c/coreboot/+/31842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5948ab60a661ef78e4e5c8571535a096fc88ea5 Gerrit-Change-Number: 31842 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019