coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Nico Huber (Code Review) 14 Mar '19

14 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 55: > Yes @Idwer, can you please help me to know your requirements so that i can intercept the same in this CL or future CL as it required. I can't speak for Idwer, but he seemed to have similar thoughts. Here are mine: 1. Stop replacing open-source coreboot functionality with blobs. The justification for this change seems to be that the SkipMpInit option will vanish. To me, it seems like a huge offense to coreboot. There are hundreds of copyright holders on the open-source side and a single one on the blob side, yet the blob side enforces their will. This change shows me that even after the past 5 years of FSP integration and promises, we are still running coreboot down further and further. Maybe this is a strategy? only stop when coreboot development has become that expensive that nobody wants it anymore? At least for a smaller company, the one I work for, the costs for coreboot development exploded since the introduction of FSP. 2. In case 1. happens anyway, find a less offensive way to integrate the blob. Calling GPL code from the blob makes it harder for me to see them as separate works as requested by the GPL (not to mention the requested separate distribution). We have learned during the discussion of this change that there are alternatives that could avoid calling GPL code from the blob. In that case, coreboot and FSP would run redundant code and I assume things would be slowed down. So I see this change as a mitigation for the ugly design of FSP, spitting into the faces of contributors that saw their code protected by the GPL. -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 55 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Thu, 14 Mar 2019 11:33:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Remove leftover files
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31871 ) Change subject: Remove leftover files ...................................................................... Remove leftover files Change-Id: I7fa27a2cbc73b4acae41373a51f600f32b9002bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31871 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- D src/lib/debug.c D src/southbridge/intel/i82801dx/tco_timer.c D src/superio/smsc/lpc47b397/early_gpio.c 3 files changed, 0 insertions(+), 172 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/lib/debug.c b/src/lib/debug.c deleted file mode 100644 index 80ee416..0000000 --- a/src/lib/debug.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void print_debug_pci_dev(unsigned int dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%x", - (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7); -} - -static inline void print_pci_devices(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev; -#else - struct device *dev; -#endif - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - } -} - -static void dump_pci_device(unsigned int dev) -{ - int i; - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - - for (i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = pci_read_config8(dev, i); - printk(BIOS_DEBUG, " %02x", val); - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - } -} - -static inline void dump_pci_devices(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev; -#else - struct device *dev; -#endif - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - - -static inline void dump_io_resources(unsigned int port) -{ - int i; - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - u8 val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); - printk(BIOS_DEBUG, " %02x", val); - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - port++; - } -} diff --git a/src/southbridge/intel/i82801dx/tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c deleted file mode 100644 index e773fa4..0000000 --- a/src/southbridge/intel/i82801dx/tco_timer.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void i82801dx_halt_tco_timer(void) -{ - /* Set the LPC device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Temporarily set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); - - /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), - PMBASE_ADDR + TCOBASE + TCO1_CNT); -} diff --git a/src/superio/smsc/lpc47b397/early_gpio.c b/src/superio/smsc/lpc47b397/early_gpio.c deleted file mode 100644 index 66a040c..0000000 --- a/src/superio/smsc/lpc47b397/early_gpio.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) -{ - outb(value, iobase + offset); -} - -static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) -{ - return inb(iobase+offset); -} - -#if 0 -/* For GP60-GP64, GP66-GP85. */ -#define LPC47B397_GPIO_CNTL_INDEX 0x70 -#define LPC47B397_GPIO_CNTL_DATA 0x71 - -static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); -} - -static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase + LPC47B397_GPIO_CNTL_DATA); -} -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fa27a2cbc73b4acae41373a51f600f32b9002bf Gerrit-Change-Number: 31871 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Remove leftover files
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31871 ) Change subject: Remove leftover files ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31871/1/src/lib/debug.c File src/lib/debug.c: https://review.coreboot.org/#/c/31871/1/src/lib/debug.c@a90 PS1, Line 90: > Say again? Read 256 bytes from single IO port? line 94 increments port -- To view, visit https://review.coreboot.org/c/coreboot/+/31871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fa27a2cbc73b4acae41373a51f600f32b9002bf Gerrit-Change-Number: 31871 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 14 Mar 2019 11:32:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: gigabyte/ga-h61m-s2pv: fix PS/2 ACPI
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31831 ) Change subject: gigabyte/ga-h61m-s2pv: fix PS/2 ACPI ...................................................................... gigabyte/ga-h61m-s2pv: fix PS/2 ACPI Change-Id: Ia806d8470aa36e04f1b0b714a80d4e7b1eb80100 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31831 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl index 78bf687..450c7fd 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl @@ -13,7 +13,4 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse +#include <drivers/pc80/pc/ps2_controller.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/31831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia806d8470aa36e04f1b0b714a80d4e7b1eb80100 Gerrit-Change-Number: 31831 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: gigabyte/ga-h61m-s2pv: fix PS/2 ACPI
by Patrick Georgi (Code Review) 14 Mar '19

14 Mar '19

Patrick Georgi has uploaded a new patch set (#2) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/31831 ) Change subject: gigabyte/ga-h61m-s2pv: fix PS/2 ACPI ...................................................................... gigabyte/ga-h61m-s2pv: fix PS/2 ACPI Change-Id: Ia806d8470aa36e04f1b0b714a80d4e7b1eb80100 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31831/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia806d8470aa36e04f1b0b714a80d4e7b1eb80100 Gerrit-Change-Number: 31831 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: device/root_device: Scan bridges on LPC bus too
by Kyösti Mälkki (Code Review) 14 Mar '19

14 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device/root_device: Scan bridges on LPC bus too ...................................................................... Patch Set 5: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/29474/5/src/device/root_device.c File src/device/root_device.c: https://review.coreboot.org/#/c/29474/5/src/device/root_device.c@66 PS5, Line 66: void scan_lpc_bus(struct device *bus) Looks very much like scan_usb_bus() and root_dev_scan_bus(). https://review.coreboot.org/#/c/29474/5/src/device/root_device.c@105 PS5, Line 105: link->secondary = ++bus_max; This is weird, each path type (PCI/SMBus/LPC/xx) should have separate enumeration for the bus number. -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 14 Mar 2019 11:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: fix RCompResistor[0] value
by Shelley Chen (Code Review) 14 Mar '19

14 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31868 Change subject: mb/google/hatch: fix RCompResistor[0] value ...................................................................... mb/google/hatch: fix RCompResistor[0] value From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information User Guide, RCompResistor[0] should be 121. BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/memory.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31868/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index 6ca98e4..b6a6615 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -30,8 +30,8 @@ .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - /* Baseboard uses 120, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 120, 81, 100 }, + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 121, 81, 100 }, /* Baseboard Rcomp target values */ .rcomp_targets = { 100, 40, 20, 20, 26 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a Gerrit-Change-Number: 31868 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Update DRAM IDs
by Shelley Chen (Code Review) 14 Mar '19

14 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31862 Change subject: mb/google/hatch: Update DRAM IDs ...................................................................... mb/google/hatch: Update DRAM IDs Update Hatch DRAM IDs to use the new DRAM ID assignment for general spds: 0 = 4G 2400 1 = 4G 2666 2 = 8G 2400 3 = 8G 2666 4 = 16G 2400 5 = 16G 2666 Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/Makefile.inc 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31862/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index 074fc54..c93a45b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -14,11 +14,11 @@ ## SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += empty_ddr4 # 0b010 -SPD_SOURCES += empty_ddr4 # 0b011 -SPD_SOURCES += empty_ddr4 # 0b100 -SPD_SOURCES += 8G_2666 # 0b101 +SPD_SOURCES += 4G_2666 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Gerrit-Change-Number: 31862 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku
by Shelley Chen (Code Review) 14 Mar '19

14 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31358 Change subject: mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku ...................................................................... mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize MemorySpdPrt pointers based on the value read from MEM_CH_SEL, which is read from GPP_F2. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/baseboard/memory.c 4 files changed, 47 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31358/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..b2db7ee 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg memcfg; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; + variant_memory_params(&memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + &memcfg, &spd); } diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f8d5d7d..b87cfa8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -115,6 +115,8 @@ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), + /* MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), /* UART_WWANTX_WLANRX_COEX1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* UART_WWANRX_WLANTX_COEX2 */ @@ -185,6 +187,8 @@ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 038ec6e..aa7c67d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H +#include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -29,7 +30,7 @@ int variant_memory_sku(void); /* Return board specific memory configuration */ -const struct cnl_mb_cfg *variant_memory_params(void); +void variant_memory_params(struct cnl_mb_cfg *bcfg); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index 80f3ba4..977573d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -18,33 +18,46 @@ #include <gpio.h> #include <soc/cnl_memcfg_init.h> -static const struct cnl_mb_cfg baseboard_memcfg = { - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - - /* Baseboard uses 120, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 120, 81, 100 }, - - /* Baseboard Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* Set CaVref config to 2 */ - .vref_ca_config = 2, - - /* Enable Early Command Training */ - .ect = 1, +/* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ +static const uint8_t dqs_map_ddr4[][8] = { + { 0, 1, 4, 5, 2, 3, 6, 7 }, + { 0, 1, 4, 5, 2, 3, 6, 7 } }; +/* Baseboard uses 120, 81 and 100 rcomp resistors */ +const static uint16_t rcomp_resistor_ddr4[] = { 120, 81, 100 }; +/* Baseboard Rcomp target values */ +const static uint16_t rcomp_targets_ddr4[] = { 100, 40, 20, 20, 26 }; -const struct cnl_mb_cfg *__weak variant_memory_params(void) +void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { - return &baseboard_memcfg; + int i; + + for (i = 0; i < sizeof(dqs_map_ddr4[DDR_CH0])/sizeof(uint8_t); i++) { + bcfg->dqs_map[DDR_CH0][i] = dqs_map_ddr4[DDR_CH0][i]; + bcfg->dqs_map[DDR_CH1][i] = dqs_map_ddr4[DDR_CH1][i]; + } + + for (i = 0; i < sizeof(rcomp_resistor_ddr4)/sizeof(uint16_t); i++) + bcfg->rcomp_resistor[i] = rcomp_resistor_ddr4[i]; + + for (i = 0; i < sizeof(rcomp_targets_ddr4)/sizeof(uint16_t); i++) + bcfg->rcomp_targets[i] = rcomp_targets_ddr4[i]; + + bcfg->vref_ca_config = 2; + bcfg->ect = 1; + + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + if (gpio_get(GPP_F2) == 1) + bcfg->single_channel = 1; } int __weak variant_memory_sku(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Gerrit-Change-Number: 31358 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

3 22

Change in ...coreboot[master]: mb/google/octopus: Create Bloog varianta
by Tony Huang (Code Review) 14 Mar '19

14 Mar '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31860 Change subject: mb/google/octopus: Create Bloog varianta ...................................................................... mb/google/octopus: Create Bloog varianta This commit create bloog variant for Octopus. Initial settings are copy from meep. Remove I2C tuning, WACOM digitizer and WEIDA touchscreen. BUG=b:127736039 BRANCH=octopus TEST=None Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/bloog/Makefile.inc A src/mainboard/google/octopus/variants/bloog/gpio.c A src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/bloog/include/variant/ec.h A src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h A src/mainboard/google/octopus/variants/bloog/overridetree.cb 8 files changed, 201 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31860/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 8c13961..6dd062a 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -58,6 +58,7 @@ default "meep" if BOARD_GOOGLE_MEEP default "ampton" if BOARD_GOOGLE_AMPTON default "casta" if BOARD_GOOGLE_CASTA + default "bloog" if BOARD_GOOGLE_BLOOG default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -78,6 +79,7 @@ default "Meep" if BOARD_GOOGLE_MEEP default "Ampton" if BOARD_GOOGLE_AMPTON default "Casta" if BOARD_GOOGLE_CASTA + default "Bloog" if BOARD_GOOGLE_BLOOG default "Octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -95,6 +97,7 @@ default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA + default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS @@ -126,12 +129,14 @@ default y if BOARD_GOOGLE_FLEEX default y if BOARD_GOOGLE_BOBBA default y if BOARD_GOOGLE_CASTA + default y if BOARD_GOOGLE_BLOOG config DRAM_PART_NUM_ALWAYS_IN_CBI bool depends on DRAM_PART_NUM_IN_CBI default y if BOARD_GOOGLE_AMPTON default y if BOARD_GOOGLE_CASTA + default y if BOARD_GOOGLE_BLOOG config DRAM_PART_IN_CBI_BOARD_ID_MIN int diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 498da36..adc7060 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -52,3 +52,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_BLOOG + bool "-> Bloog" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/bloog/Makefile.inc b/src/mainboard/google/octopus/variants/bloog/Makefile.inc new file mode 100644 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c new file mode 100644 index 0000000..001a488 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO(GPIO_178, 0, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb new file mode 100644 index 0000000..98d0179 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -0,0 +1,93 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00171a1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + device domain 0 on + device pci 16.0 off end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 7 + end + + # Disable compliance mode + register "DisableComplianceMode" = "1" +end -- To view, visit https://review.coreboot.org/c/coreboot/+/31860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Gerrit-Change-Number: 31860 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019