Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 )
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add GPIO API
......................................................................
Patch Set 15: Code-Review+2
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Gerrit-Change-Number: 29955
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SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31827
Change subject: TEMP:NOT FOR REVIEW:google/mistral: Implement board reset
......................................................................
TEMP:NOT FOR REVIEW:google/mistral: Implement board reset
Implement reset using PSHOLD.
Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c
Signed-off-by: Santhosh Hassan <sahassan(a)google.com>
---
M src/mainboard/google/mistral/Kconfig
M src/mainboard/google/mistral/Makefile.inc
A src/mainboard/google/mistral/reset.c
M src/soc/qualcomm/qcs405/include/soc/iomap.h
4 files changed, 37 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31827/1
diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig
index eacb9f4..87d2df8 100644
--- a/src/mainboard/google/mistral/Kconfig
+++ b/src/mainboard/google/mistral/Kconfig
@@ -13,7 +13,6 @@
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_CHROMEOS
- select MISSING_BOARD_RESET
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_SPI_TPM_CR50
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
index 9eb8246..7f6cb7c 100644
--- a/src/mainboard/google/mistral/Makefile.inc
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -1,15 +1,19 @@
bootblock-y += memlayout.ld
+bootblock-y += reset.c
bootblock-y += bootblock.c
verstage-y += memlayout.ld
verstage-y += chromeos.c
+verstage-y += reset.c
verstage-y += verstage.c
romstage-y += memlayout.ld
romstage-y += chromeos.c
+romstage-y += reset.c
romstage-y += romstage.c
ramstage-y += memlayout.ld
ramstage-y += chromeos.c
+ramstage-y += reset.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/mistral/reset.c b/src/mainboard/google/mistral/reset.c
new file mode 100644
index 0000000..98fbc0c
--- /dev/null
+++ b/src/mainboard/google/mistral/reset.c
@@ -0,0 +1,31 @@
+/*
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+#include <reset.h>
+
+void do_board_reset(void)
+{
+ /*
+ * At boot time the boot loaders would have set a magic cookie
+ * here to detect watchdog reset. However, since this is a
+ * normal reset clear the magic numbers.
+ */
+ write32(TCSR_BOOT_MISC_DETECT, 0);
+ write32(TCSR_RESET_DEBUG_SW_ENTRY, 0);
+ write32(GCNT_PSHOLD, 0);
+}
diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h
index 968d6ce..851c607 100644
--- a/src/soc/qualcomm/qcs405/include/soc/iomap.h
+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h
@@ -36,6 +36,8 @@
#ifndef __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
#define __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
+#include <arch/io.h>
+#include <gpio.h>
#include <device/mmio.h>
#include <soc/cdp.h>
#include <soc/blsp.h>
--
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nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30714
Change subject: mistral: qcs405: copy calibration data to CBMEM
......................................................................
mistral: qcs405: copy calibration data to CBMEM
This pacth adds support to copy the wifi calibration
data to CBMEM so that the depthcharge can use it to
populate the data into wifi dt node.
Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/mainboard/google/mistral/mainboard.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30714/1
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
index f4fc31e..3605fba 100644
--- a/src/mainboard/google/mistral/mainboard.c
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -17,6 +17,7 @@
#include <bootblock_common.h>
#include <timestamp.h>
#include <soc/usb.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#if 0
static struct usb_board_data usb0_board_data = {
@@ -46,6 +47,10 @@
static void mainboard_init(device_t dev)
{
setup_usb();
+ if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ /* Copy WIFI calibration data into CBMEM. */
+ cbmem_add_vpd_calibration_data();
+ }
}
static void mainboard_enable(device_t dev)
--
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31974
Change subject: soc/intel/cannonlake: Fix return values for get_param_value
......................................................................
soc/intel/cannonlake: Fix return values for get_param_value
Commit 41483c9 (soc/intel/cannonlake: Add required FSP UPD changes for
CML) changed the enum values for PCH_SERIAL_IO_MODE so that 0 is
invalid and valid values start from 1. However, get_param_value was
not updated to correctly subtract 1 before returning any value. This
change adds a macro PCH_SERIAL_IO_INDEX to apply the subtract 1
operation on any value that get_param_value needs to return.
BUG=b:128946016
TEST=Verified that hatch boots successfully.
Change-Id: I4e32fcd1efe4a535251f0ec58662a2dc5f70e8b0
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 9 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31974/1
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index e3a2310..77d82d6 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -40,22 +40,28 @@
PCH_DEVFN_UART2
};
+/*
+ * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP
+ * UPD expected value for Serial IO since valid enum index starts from 1.
+ */
+#define PCH_SERIAL_IO_INDEX(x) ((x) - 1)
+
static uint8_t get_param_value(const config_t *config, uint32_t dev_offset)
{
struct device *dev;
dev = dev_find_slot(0, serial_io_dev[dev_offset]);
if (!dev || !dev->enabled)
- return PchSerialIoDisabled;
+ return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled);
if ((config->SerialIoDevMode[dev_offset] >= PchSerialIoMax) ||
(config->SerialIoDevMode[dev_offset] == PchSerialIoNotInitialized))
- return PchSerialIoPci;
+ return PCH_SERIAL_IO_INDEX(PchSerialIoPci);
/*
* Correct Enum index starts from 1, so subtract 1 while returning value
*/
- return config->SerialIoDevMode[dev_offset] - 1;
+ return PCH_SERIAL_IO_INDEX(config->SerialIoDevMode[dev_offset]);
}
#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE)
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 )
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/#/c/29981/15/src/soc/qualcomm/qcs405/soc.c
File src/soc/qualcomm/qcs405/soc.c:
https://review.coreboot.org/#/c/29981/15/src/soc/qualcomm/qcs405/soc.c@26
PS15, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31);
line over 80 characters
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 )
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add GPIO API
......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/#/c/29955/15/src/soc/qualcomm/qcs405/include/so…
File src/soc/qualcomm/qcs405/include/soc/gpio.h:
https://review.coreboot.org/#/c/29955/15/src/soc/qualcomm/qcs405/include/so…
PS15, Line 90: #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
Macros with complex values should be enclosed in parentheses
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Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29967
to look at the new patch set (#16).
Change subject: TEMP: NOT FOR REVIEW: qclib: Add qclib support
......................................................................
TEMP: NOT FOR REVIEW: qclib: Add qclib support
Add to load and execute qclib blob to configure pmic,
clocks and ddr. This is the basic support without
one-training and interface table to pass data
between coreboot and qclib. That would be added later.
Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
---
M src/mainboard/google/mistral/Makefile.inc
M src/mainboard/google/mistral/romstage.c
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
M src/soc/qualcomm/qcs405/include/soc/mmu.h
A src/soc/qualcomm/qcs405/include/soc/qclib.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/mmu.c
A src/soc/qualcomm/qcs405/qclib_execute.c
9 files changed, 153 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/16
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29968
to look at the new patch set (#16).
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add blsp spi driver and enable SPI-NOR
......................................................................
TEMP: NOT FOR REVIEW: qcs405: Add blsp spi driver and enable SPI-NOR
Add the blsp spi driver required for qcs405 and also
enable the support for WINBOND spi-nor flash
Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/mainboard/google/mistral/Kconfig
M src/soc/qualcomm/qcs405/Kconfig
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/clock.c
A src/soc/qualcomm/qcs405/flash_controller.c
A src/soc/qualcomm/qcs405/include/soc/flash_controller.h
A src/soc/qualcomm/qcs405/include/soc/qup.h
A src/soc/qualcomm/qcs405/include/soc/spi.h
M src/soc/qualcomm/qcs405/spi.c
9 files changed, 1,255 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/16
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 )
Change subject: mb/solidrun/solidpc: Do initial commit
......................................................................
Patch Set 12:
(1 comment)
The change is ready for review. Unfortunately I do not have hardware to verify WiFi/BT M.2 slot and the DisplayPort is not working on the board I have tested (both coreboot and official AMI BIOS) - probably broken.
https://review.coreboot.org/#/c/23027/12/src/mainboard/solidrun/solidpc/acp…
File src/mainboard/solidrun/solidpc/acpi/mainboard.asl:
https://review.coreboot.org/#/c/23027/12/src/mainboard/solidrun/solidpc/acp…
PS12, Line 39: Method (_AEI, 0, Serialized) // _AEI: ACPI Event Interrupts
This method gives me errors:
ACPI Error: Unknown opcode 0xFE at table offset 0x0E85, ignoring (20160831/psobject-108)
ACPI Error: [RBU8] Namespace lookup failure, AE_NOT_FOUND (20160831/psargs-359)
ACPI Error: Method parse/execution failed [\_SB.GPNC._AEI] (Node ffff8ae9fa1b8e38), AE_NOT_FOUND (20160831/psparse-543)
When I get rid of this method, the IASL compiler complains on corrupted DSDT. Any ideas what is wrong with this implementation?
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