coreboot-gerrit March 2019

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Change in ...coreboot[master]: mb/solidrun/solidpc: Do initial commit
by build bot (Jenkins) (Code Review) 20 Mar '19

20 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/23027/12/src/mainboard/solidrun/solidpc/irq… File src/mainboard/solidrun/solidpc/irqroute.h: https://review.coreboot.org/#/c/23027/12/src/mainboard/solidrun/solidpc/irq… PS12, Line 21: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/23027/12/src/mainboard/solidrun/solidpc/irq… PS12, Line 36: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 20 Mar 2019 11:50:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Michał Żygowski (Code Review) 20 Mar '19

20 Mar '19

Michał Żygowski has uploaded a new patch set (#12) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... mb/solidrun/solidpc: Do initial commit Code based on G33KatWork patch from GitHub Initial support for SolidRun SolidPC mainboard. Working and tested: - HDMI (SeaBIOS + OS) - Audio (OS settings detecting input on mic and playing sound) - USB (SeaBIOS + OS: MSC, keyboard, mouse) - SD card (SeaBIOS detection and booting Ubuntu installer, OS storage) - eMMC (SeaBIOS detection and booting Ubuntu installer, OS storage) - SATA M.2 SSD (SeaBIOS detection and booting installed Debian Stretch) - Ethernet (PXE boot, OS network access) - built-in serial debug port UART0 (coreboot + SeaBIOS, OS console) TODO: - test DisplayPort - test M.2 slot for WiFi/BT - fix ACPI error with AEI method on GPIO north - mainboard documentation TEST=booting Debian Stretch with Linux kernel 4.9.144 on IB8000 SOM Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- A src/mainboard/solidrun/Kconfig A src/mainboard/solidrun/Kconfig.name A src/mainboard/solidrun/solidpc/Kconfig A src/mainboard/solidrun/solidpc/Kconfig.name A src/mainboard/solidrun/solidpc/Makefile.inc A src/mainboard/solidrun/solidpc/acpi/ec.asl A src/mainboard/solidrun/solidpc/acpi/mainboard.asl A src/mainboard/solidrun/solidpc/acpi/superio.asl A src/mainboard/solidrun/solidpc/acpi_tables.c A src/mainboard/solidrun/solidpc/board_info.txt A src/mainboard/solidrun/solidpc/boardid.c A src/mainboard/solidrun/solidpc/cmos.layout A src/mainboard/solidrun/solidpc/com_init.c A src/mainboard/solidrun/solidpc/devicetree.cb A src/mainboard/solidrun/solidpc/dsdt.asl A src/mainboard/solidrun/solidpc/fadt.c A src/mainboard/solidrun/solidpc/gpio.c A src/mainboard/solidrun/solidpc/irqroute.c A src/mainboard/solidrun/solidpc/irqroute.h A src/mainboard/solidrun/solidpc/onboard.h A src/mainboard/solidrun/solidpc/ramstage.c A src/mainboard/solidrun/solidpc/romstage.c A src/mainboard/solidrun/solidpc/smihandler.c A src/mainboard/solidrun/solidpc/spd/2Gb.spd.hex A src/mainboard/solidrun/solidpc/spd/4Gb.spd.hex A src/mainboard/solidrun/solidpc/spd/8Gb.spd.hex A src/mainboard/solidrun/solidpc/spd/Makefile.inc A src/mainboard/solidrun/solidpc/spd/spd.c 28 files changed, 1,407 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23027/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: {northbridge, soc, southbridge}/intel: Make use of generic set_subsys...
by Subrata Banik (Code Review) 20 Mar '19

20 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31985 Change subject: {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() ...................................................................... {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: Ibe0905559943796adf5c89826cc0a99ed077ec63 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/northbridge/intel/sandybridge/pcie.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c 10 files changed, 11 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31985/1 diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 16bc314..344cd80 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -65,20 +65,8 @@ } #endif -static void -pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!ven || !device) - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (ven & 0xffff)); -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 32135ee..472e8da 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,16 +649,6 @@ root_port_commit_config(); } -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); -} - static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ @@ -666,7 +656,7 @@ } static struct pci_operations pcie_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 8295765..d74b098 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -25,8 +25,6 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 -/* PCI-E Sub-System ID */ -#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 static void pch_pcie_init(struct device *dev) { @@ -72,16 +70,9 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } -static void pcie_dev_set_subsystem(struct device *dev, - unsigned int vendor, unsigned int device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 39c53e8..0bc75b5 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -306,21 +306,8 @@ return NULL; } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 9446527..3e5dbc3 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -252,22 +252,8 @@ root_port_commit_config(dev); } - -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a36fdc6..3b90ce6 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -95,19 +95,6 @@ } } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801ix_config *config = dev->chip_info; @@ -121,7 +108,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index fb90cd9..84b2b6a 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -95,19 +95,6 @@ } } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801jx_config *config = dev->chip_info; @@ -121,7 +108,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 695abf2..2a8b44e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -727,21 +727,8 @@ root_port_commit_config(); } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 4d8b6e6..c94722c 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -200,8 +200,8 @@ /* Enable subsystem id register writes */ pci_write_config16(dev, 0x82, miscreg | 0x40); - pci_write_config16(dev, 0x40, vendor); - pci_write_config16(dev, 0x42, device); + pci_dev_set_subsystem(dev, vendor, device); + /* restore original contents */ pci_write_config16(dev, 0x82, miscreg); } diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index f84d866..bfb5ab9 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -46,8 +46,7 @@ * to the sub-vendor/device ids at 40 and 42. */ pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); - pci_write_config16(dev, 0x40, vendor); - pci_write_config16(dev, 0x42, device); + pci_dev_set_subsystem(dev, vendor, device); pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe0905559943796adf5c89826cc0a99ed077ec63 Gerrit-Change-Number: 31985 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
by Krishna P Bhat D (Code Review) 20 Mar '19

20 Mar '19

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 ) Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/31520/8/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/31520/8/src/soc/intel/cannonlake/chip.h@388 PS8, Line 388: DdiPortEdp > Where is this used? supposed to used in fsp_params.c to enable Edp port. Fixed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/31520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Gerrit-Change-Number: 31520 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 20 Mar 2019 06:20:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
by Krishna P Bhat D (Code Review) 20 Mar '19

20 Mar '19

Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Balaji Manigandan, Maulik V Vaghela, Duncan Laurie, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Ronak Kanabar, V Sowmya, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31520 to look at the new patch set (#9). Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports ...................................................................... soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31520/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/31520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Gerrit-Change-Number: 31520 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: lib/ramtest: Use Kconfig switch CONFIG_RAMBASE for RAM test
by Kyösti Mälkki (Code Review) 20 Mar '19

20 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29106 ) Change subject: lib/ramtest: Use Kconfig switch CONFIG_RAMBASE for RAM test ...................................................................... Patch Set 2: CB:31978 -- To view, visit https://review.coreboot.org/c/coreboot/+/29106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc57e684a677ac64225ea54cb43e6fbb68930354 Gerrit-Change-Number: 29106 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 20 Mar 2019 06:11:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/sandybridge: Fix domain resources
by Kyösti Mälkki (Code Review) 20 Mar '19

20 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27118 ) Change subject: nb/intel/sandybridge: Fix domain resources ...................................................................... Patch Set 1: Has this been fixed? -- To view, visit https://review.coreboot.org/c/coreboot/+/27118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c69ff8ec269d472f034fd79aafb337463193adf Gerrit-Change-Number: 27118 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 20 Mar 2019 06:03:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/*/chromeos.c: Be explicit about code for ramstage
by Kyösti Mälkki (Code Review) 20 Mar '19

20 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31930 ) Change subject: mb/*/chromeos.c: Be explicit about code for ramstage ...................................................................... Patch Set 1: Maybe we can submit this before virt-dev-switch removal? -- To view, visit https://review.coreboot.org/c/coreboot/+/31930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Gerrit-Change-Number: 31930 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Mar 2019 06:00:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
by Furquan Shaikh (Code Review) 20 Mar '19

20 Mar '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 ) Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/31520/8/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/31520/8/src/soc/intel/cannonlake/chip.h@388 PS8, Line 388: DdiPortEdp Where is this used? -- To view, visit https://review.coreboot.org/c/coreboot/+/31520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Gerrit-Change-Number: 31520 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 20 Mar 2019 05:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
by Krishna P Bhat D (Code Review) 20 Mar '19

20 Mar '19

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 ) Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/31520/7/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/devicetree.cb: https://review.coreboot.org/#/c/31520/7/src/mainboard/google/sarien/variant… PS7, Line 46: /D > this is not true anymore. Done https://review.coreboot.org/#/c/31520/7/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/31520/7/src/mainboard/google/sarien/variant… PS7, Line 50: /D > Not true anymore. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Gerrit-Change-Number: 31520 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 20 Mar 2019 05:17:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2019