Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Balaji Manigandan, Maulik V Vaghela, Duncan Laurie, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Ronak Kanabar, V Sowmya,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31520
to look at the new patch set (#8).
Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
......................................................................
soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
5 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31520/8
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Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 )
Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
......................................................................
Patch Set 7:
(2 comments)
> Patch Set 6:
>
> Verified on hatch, yet to be verified on sarien and arcada.
Verified on sarien and arcada.
https://review.coreboot.org/#/c/31520/6/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/#/c/31520/6/src/mainboard/google/sarien/variant…
PS6, Line 49: DdiPortDHpd
> This is not used as a hotplug pin on arcada: […]
Done
https://review.coreboot.org/#/c/31520/6/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/#/c/31520/6/src/mainboard/google/sarien/variant…
PS6, Line 53: DdiPortDHpd
> This is not used as a hotplug pin on sarien: […]
Done
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Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Maulik V Vaghela, Duncan Laurie, Rizwan Qureshi, Shelley Chen, V Sowmya, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31520
to look at the new patch set (#7).
Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
......................................................................
soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
5 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31520/7
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30289 )
Change subject: soc/intel/common: Remove common chip config use_fsp_mp_init
......................................................................
Patch Set 11:
> (1 comment)
I have made the same change already, anything else.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31841 )
Change subject: Documentation/soc/intel: Add MP Initialization document
......................................................................
Patch Set 2:
(2 comments)
@Patrick, any further comment here ?
https://review.coreboot.org/#/c/31841/1/Documentation/soc/intel/mp_init/mp_…
File Documentation/soc/intel/mp_init/mp_init.md:
https://review.coreboot.org/#/c/31841/1/Documentation/soc/intel/mp_init/mp_…
PS1, Line 49: external PPI service feature implemented.
> it would be great to list the features FSP2. […]
Done
https://review.coreboot.org/#/c/31841/1/Documentation/soc/intel/mp_init/mp_…
PS1, Line 53: :doc:`../fsp/ppi`
> with recommonmark 0.5 (which is the current version on doc.coreboot. […]
Done
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Change subject: soc/intel/common: Add Kconfig option to choose desired MP Init for platform
......................................................................
Patch Set 10:
> (2 comments)
HI Philipp, if you can kindly see what needs to be done here further.
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Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 )
Change subject: soc/intel/cannonlake: Clear PMCON status bits
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c
File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1…
PS3, Line 146: pmc_clear_suspwrflr
> Does FSP rely on these values? If yes, what for? Ideally I was thinking of doing this in pmc_init instead of pch_finalize.
Haven't looked at the FSP code, just wanted to steer clear if it does. Maybe we can have a look.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 )
Change subject: soc/intel/cannonlake: Clear PMCON status bits
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c
File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1…
PS3, Line 146: pmc_clear_suspwrflr
> makes sense, If FSP is relying on these values we have to make we clear these after FSP is done initialization.
Does FSP rely on these values? If yes, what for? Ideally I was thinking of doing this in pmc_init instead of pch_finalize.
> I think FSP will clear the PWR_FLR status itself anyway right? In PchOnPciEnumCompleteCommon function
I don't think we should rely on FSP doing this.
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