coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src: Use include <reset.h> when appropriate
by HAOUAS Elyes (Code Review) 19 Mar '19

19 Mar '19

Hello Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29301 to look at the new patch set (#7). Change subject: src: Use include <reset.h> when appropriate ...................................................................... src: Use include <reset.h> when appropriate Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c 39 files changed, 25 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Gerrit-Change-Number: 29301 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Remove unneeded include <reset.h>
by HAOUAS Elyes (Code Review) 19 Mar '19

19 Mar '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29301 ) Change subject: src: Remove unneeded include <reset.h> ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/29301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Gerrit-Change-Number: 29301 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Frans Hendriks (Code Review) 19 Mar '19

19 Mar '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29398 to look at the new patch set (#7). Change subject: soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... soc/intel/braswell/southcluster.c: Correct serial IRQ support Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and make mode configurable. Default is quiet mode. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29398/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'
by Subrata Banik (Code Review) 19 Mar '19

19 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31913 Change subject: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned' ...................................................................... soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned' Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/pcie/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31913/1 diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 0a5e1bf..8295765 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -73,7 +73,7 @@ } static void pcie_dev_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) + unsigned int vendor, unsigned int device) { pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); -- To view, visit https://review.coreboot.org/c/coreboot/+/31913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044 Gerrit-Change-Number: 31913 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Revert "lint/clang-format: set to 96 chars per line"
by Julius Werner (Code Review) 19 Mar '19

19 Mar '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31916 Change subject: Revert "lint/clang-format: set to 96 chars per line" ...................................................................... Revert "lint/clang-format: set to 96 chars per line" This reverts commit 626ba097a2cd1c87800a2154420829b09803467e. This change was submitted under the incorrect assumption that there was agreement on a coding style change. There wasn't, so while the issue is under discussion we should revert to the previous status quo. Making clang-format honor the line length is a separate issue from changing the line length, and can be reuploaded as a separate CL. Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf --- M .clang-format M util/lint/lint-007-checkpatch 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31916/1 diff --git a/.clang-format b/.clang-format index 5c8aa3c..d853f50 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 96 +ColumnLimit: 0 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index a7b63e8..afa593e 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -28,8 +28,6 @@ ^src/vendorcode\|\ ^Documentation" -opts="--max-line-length 96" - # default: test src and util if [ "$1" = "" ]; then INCLUDED_DIRS="src util" @@ -37,7 +35,7 @@ elif [ "$1" = "diff" ]; then args=$( echo $EXCLUDED_DIRS | \ sed -e 's,\\|, ,g' -e 's,\^,--exclude=,g' ) - util/lint/checkpatch.pl --quiet --no-signoff $opts $args - + util/lint/checkpatch.pl --quiet --no-signoff $args - exit $? # Space separated list of directories to test else @@ -51,5 +49,5 @@ grep -v $EXCLUDED_DIRS ) for FILE in $FILELIST; do - util/lint/checkpatch.pl --show-types --file --quiet $opts "$FILE" + util/lint/checkpatch.pl --show-types --file --quiet "$FILE" done -- To view, visit https://review.coreboot.org/c/coreboot/+/31916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf Gerrit-Change-Number: 31916 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKE
by Shelley Chen (Code Review) 19 Mar '19

19 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31852 Change subject: mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKE ...................................................................... mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKE BUG=b:127310803 BRANCH=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31852/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3c1f79e..15d052a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,7 +15,8 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE - select SOC_INTEL_WHISKEYLAKE + select SOC_INTEL_WHISKEYLAKE if BOARD_GOOGLE_HATCH_WHL + select SOC_INTEL_COMETLAKE if BOARD_GOOGLE_HATCH select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/31852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4 Gerrit-Change-Number: 31852 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Matthias Wiedhalm (Code Review) 19 Mar '19

19 Mar '19

Matthias Wiedhalm has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 7: At the moment the fhd mod board requires 3.3V from a separate cable, which causes elevated power consumption especially when the lid is closed or the machine is sleeping. This is because the tapped source is always on. Though if it was possible to provide power through the VCC3P power rail instead, the board could be supplied with power only when the display is supposed to be on. This would eliminate the extra cable and only requires that J1 jumper is closed on the board. I tried it myself and also measured a the corresponding pad but there seems to be no voltage present from the lvds connector with the current state of this patch. Maybe someone more knowledgeable has an idea on how to implement this? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 7 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2019 18:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Clear PMCON status bits
by Krishna P Bhat D (Code Review) 19 Mar '19

19 Mar '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31902 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Clear PMCON status bits ...................................................................... soc/intel/cannonlake: Clear PMCON status bits The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. BUG=b:128482282 BRANCH=None TEST=In cbmem logs, check for value of “prev_sleep_state” using command cbmem –c | grep “prev_sleep_state” For cold reboot, "prev_sleep_state 5" For warm reboot, "prev_sleep_state 0" Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/cannonlake/finalize.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31902/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Gerrit-Change-Number: 31902 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add DRAM resources
by Patrick Georgi (Code Review) 19 Mar '19

19 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29954 ) Change subject: qcs405: Add DRAM resources ...................................................................... qcs405: Add DRAM resources TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/soc.c 3 files changed, 12 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index d6e4dfb..8ed258b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -42,7 +42,9 @@ REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) BSRAM_END(0x8D80000) - DRAM_START(0x90000000) - POSTRAM_CBFS_CACHE(0x90000000, 384K) - RAMSTAGE(0x90800000, 128K) + DRAM_START(0x80000000) + /* DDR Carveout for BL31 usage */ + REGION(dram_reserved, 0x85000000, 0x5100000, 4096) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 128K) } diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index ef2285c..45e6988 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -21,5 +21,6 @@ DECLARE_REGION(ssram); DECLARE_REGION(bsram); +DECLARE_REGION(dram_reserved); #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index f7591a7..b3bfb99 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -13,12 +13,17 @@ * GNU General Public License for more details. */ +#include <symbols.h> #include <device/device.h> #include <timestamp.h> +#include <soc/mmu.h> +#include <soc/symbols.h> static void soc_read_resources(struct device *dev) { - + ram_resource(dev, 0, (uintptr_t)_dram / KiB, (1 * GiB) / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + REGION_SIZE(dram_reserved) / KiB); } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Gerrit-Change-Number: 29954 Gerrit-PatchSet: 15 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: libpayload: qcs405: Add new Configs
by Patrick Georgi (Code Review) 19 Mar '19

19 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29953 ) Change subject: libpayload: qcs405: Add new Configs ...................................................................... libpayload: qcs405: Add new Configs Add Additional configs to enable Timer and CHROMEOS build. TEST=build Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- A payloads/libpayload/configs/config.mistral 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral new file mode 100644 index 0000000..5f60392 --- /dev/null +++ b/payloads/libpayload/configs/config.mistral @@ -0,0 +1,3 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/29953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Gerrit-Change-Number: 29953 Gerrit-PatchSet: 15 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2019