coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP
by Angel Pons (Code Review) 24 Mar '19

24 Mar '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32032 ) Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Gerrit-Change-Number: 32032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 10:26:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Arthur Heymans (Code Review) 24 Mar '19

24 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/#/c/18548/21/src/northbridge/intel/i945/raminit… File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/18548/21/src/northbridge/intel/i945/raminit… PS21, Line 2460: : The logic is not the same as the new code. This condition is entered only if a dimm or both are not installed. IDK what the correct logic ought to be... -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 21 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 09:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP
by HAOUAS Elyes (Code Review) 24 Mar '19

24 Mar '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32032 ) Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32032/1/src/mainboard/ibase/mb899/romstage.c File src/mainboard/ibase/mb899/romstage.c: https://review.coreboot.org/#/c/32032/1/src/mainboard/ibase/mb899/romstage.… PS1, Line 234: if (CONFIG(DEBUG_RAM_SETUP)) : dump_spd_registers(); > do we really need to dump MCHBAR at this stage ? […] no, that is fine. it is just for debugging and one can those lines at whatever stage below. sorry for the noise. -- To view, visit https://review.coreboot.org/c/coreboot/+/32032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Gerrit-Change-Number: 32032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 09:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP
by HAOUAS Elyes (Code Review) 24 Mar '19

24 Mar '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32032 ) Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32032/1/src/mainboard/ibase/mb899/romstage.c File src/mainboard/ibase/mb899/romstage.c: https://review.coreboot.org/#/c/32032/1/src/mainboard/ibase/mb899/romstage.… PS1, Line 234: if (CONFIG(DEBUG_RAM_SETUP)) : dump_spd_registers(); do we really need to dump MCHBAR at this stage ? some of registers may be affected by this reading ? we probably need to split it : 1- debug/dump SPD (here it makes sense 2- debug/dump MCHBAR (but, I think, not here) -- To view, visit https://review.coreboot.org/c/coreboot/+/32032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Gerrit-Change-Number: 32032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 08:56:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Remove common chip config use_fsp_mp_init
by Subrata Banik (Code Review) 24 Mar '19

24 Mar '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30289 ) Change subject: soc/intel/common: Remove common chip config use_fsp_mp_init ...................................................................... soc/intel/common: Remove common chip config use_fsp_mp_init This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/chip.h M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c 9 files changed, 9 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 524bcca..f2b7344 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,6 +32,7 @@ select SADDLEBROOK_USES_FSP1_1 select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select USE_INTEL_FSP_MP_INIT config SADDLEBROOK_USES_FSP1_1 bool "FSP driver 1.1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 8f78249..2f84a5d 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,11 +140,6 @@ .voltage_limit = 0x5F0 \ }" - # Skip coreboot MP Init - register "common_soc_config" = "{ - .use_fsp_mp_init = 1, - }" - # Enable x1 slot register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..9d72167 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -733,7 +733,7 @@ if (!CONFIG(SOC_INTEL_GLK)) silconfig->MonitorMwaitEnable = 0; - silconfig->SkipMpInit = !chip_get_fsp_mp_init(); + silconfig->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 791a6c8..3e3aa5e 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -64,8 +64,9 @@ m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; + #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) - m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif /* Disable CPU Flex Ratio and SaGv in recovery mode */ diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 3dae621..eed1ada 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -32,18 +32,3 @@ return soc_config; } - -/* - * This function will get MP Init config - * - * Return values: - * 0 = Make use of coreboot MP Init - * 1 = Make use of FSP MP Init - */ -int chip_get_fsp_mp_init(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->use_fsp_mp_init; -} diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 48bc496..342a120 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -133,7 +133,7 @@ struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); - if (chip_get_fsp_mp_init()) + if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; microcode_patch = intel_microcode_find(); @@ -151,7 +151,7 @@ /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { - if (chip_get_fsp_mp_init()) + if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0) diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h index d761f6b..555bdaa 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -33,24 +33,9 @@ int chipset_lockdown; struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* - * Option for mainboard to skip coreboot MP initialization - * 0 = Make use of coreboot MP Init - * 1 = Make use of FSP MP Init - */ - uint8_t use_fsp_mp_init; }; /* This function to retrieve soc config structure required by common code */ const struct soc_intel_common_config *chip_get_common_soc_structure(void); -/* - * This function will get MP Init config - * - * Return values: - * 0 = Make use of coreboot MP Init - * 1 = Make use of FSP MP Init - */ -int chip_get_fsp_mp_init(void); - #endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 98e5baf..9094348 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -197,7 +197,7 @@ params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; - params->SkipMpInit = !chip_get_fsp_mp_init(); + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 15eb6b2..c16a913 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -27,6 +27,7 @@ #include <intelblocks/chip.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -422,7 +423,7 @@ params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; - params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init(); + params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/30289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Gerrit-Change-Number: 30289 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/common: Add Kconfig option to choose desired MP Init for pl...
by Subrata Banik (Code Review) 24 Mar '19

24 Mar '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30287 ) Change subject: soc/intel/common: Add Kconfig option to choose desired MP Init for platform ...................................................................... soc/intel/common: Add Kconfig option to choose desired MP Init for platform mainboard users can select correct MP Init Kconfig in order to perform MP initialization. 1. Native coreboot MP Init. 2. FSP to do MP Init. 3. FSP to make use of coreboot MP service PPI to perform MP Initialization Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30287 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 48f3f16..9ec5307 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -50,3 +50,30 @@ the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. + +menu "Multiple Processor (MP) Initialization Options" +config USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + default y if !PLATFORM_USES_FSP2_1 + default n + help + This option allows user to select native coreboot option to perform + multiprocessor initialization. + +config USE_INTEL_FSP_MP_INIT + bool "Perform MP Initialization by FSP" + default n + help + This option allows FSP to perform multiprocessor initialization. + +config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + default y if PLATFORM_USES_FSP2_1 + default n + select USE_COREBOOT_NATIVE_MP_INIT + help + This option allows FSP to make use of MP services PPI published by + coreboot to perform multiprocessor initialization. + +endmenu # Multiple Processor (MP) Initialization Options -- To view, visit https://review.coreboot.org/c/coreboot/+/30287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b Gerrit-Change-Number: 30287 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: [WIP] add i945G based mainboard
by HAOUAS Elyes (Code Review) 23 Mar '19

23 Mar '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25509 ) Change subject: [WIP] add i945G based mainboard ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/#/c/25509/27/src/mainboard/nec/945g-m4/Kconfig File src/mainboard/nec/945g-m4/Kconfig: https://review.coreboot.org/#/c/25509/27/src/mainboard/nec/945g-m4/Kconfig@… PS27, Line 19: missing "select BOOT_DEVICE_NOT_SPI_FLASH" Thx to Kyösti Mälkki -- To view, visit https://review.coreboot.org/c/coreboot/+/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 27 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Mar 2019 13:01:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [NOTFORMERGE] PCI accessor testcases
by build bot (Jenkins) (Code Review) 23 Mar '19

23 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31811 ) Change subject: [NOTFORMERGE] PCI accessor testcases ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-000.c File src/testcase/testcase-000.c: https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-000.c@12 PS4, Line 12: static const pci_devfn_t bdf = PCI_DEV(0,0x1f,7); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-000.c@12 PS4, Line 12: static const pci_devfn_t bdf = PCI_DEV(0,0x1f,7); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-001.c File src/testcase/testcase-001.c: https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-001.c@15 PS4, Line 15: static const pci_devfn_t bdf = PCI_DEV(0,0x1f,7); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/31811/4/src/testcase/testcase-001.c@15 PS4, Line 15: static const pci_devfn_t bdf = PCI_DEV(0,0x1f,7); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/31811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca4d5556d2ac80986a909cf4df029ee575f3940 Gerrit-Change-Number: 31811 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Mar 2019 12:31:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by build bot (Jenkins) (Code Review) 23 Mar '19

23 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 7: (4 comments) https://review.coreboot.org/#/c/31752/7/src/arch/x86/include/arch/pci_mmio_… File src/arch/x86/include/arch/pci_mmio_cfg_romcc.h: https://review.coreboot.org/#/c/31752/7/src/arch/x86/include/arch/pci_mmio_… PS7, Line 36: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); line over 80 characters https://review.coreboot.org/#/c/31752/7/src/arch/x86/include/arch/pci_mmio_… PS7, Line 44: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); line over 80 characters https://review.coreboot.org/#/c/31752/7/src/arch/x86/include/arch/pci_mmio_… PS7, Line 60: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); line over 80 characters https://review.coreboot.org/#/c/31752/7/src/arch/x86/include/arch/pci_mmio_… PS7, Line 68: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sat, 23 Mar 2019 12:30:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [NOTFORMERGE] PCI accessor testcases
by Kyösti Mälkki (Code Review) 23 Mar '19

23 Mar '19

Hello Aaron Durbin, build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31811 to look at the new patch set (#4). Change subject: [NOTFORMERGE] PCI accessor testcases ...................................................................... [NOTFORMERGE] PCI accessor testcases Change-Id: I0ca4d5556d2ac80986a909cf4df029ee575f3940 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc A src/testcase/Makefile.inc A src/testcase/testcase-000.c A src/testcase/testcase-001.c 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31811/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca4d5556d2ac80986a909cf4df029ee575f3940 Gerrit-Change-Number: 31811 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2019