coreboot-gerrit March 2019

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Change in ...coreboot[master]: fix i82801jx
by Patrick Rudolph (Code Review) 24 Mar '19

24 Mar '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32040 Change subject: fix i82801jx ...................................................................... fix i82801jx Change-Id: I463e563860a9538aacd43fe7ebb9d09a5908f506 --- M src/southbridge/intel/i82801jx/i82801jx.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32040/1 diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2a85d5a..80d6cbd 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -240,7 +240,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -int southbridge_detect_s3_resume(void); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I463e563860a9538aacd43fe7ebb9d09a5908f506 Gerrit-Change-Number: 32040 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 24 Mar '19

24 Mar '19

Hello Patrick Rudolph, Angel Pons, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32038 to look at the new patch set (#2). Change subject: sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/p5qc/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc D src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/i82801jx/i82801jx.h 6 files changed, 3 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/32038/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Gerrit-Change-Number: 32038 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Nico Huber (Code Review) 24 Mar '19

24 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/#/c/29398/10/src/mainboard/google/cyan/variants… File src/mainboard/google/cyan/variants/banon/devicetree.cb: https://review.coreboot.org/#/c/29398/10/src/mainboard/google/cyan/variants… PS10, Line 98: register "serirq_mode" = "SERIRQ_QUIET" `SERIRQ_QUIET` is the default (0 case in `enum serirq_mode`), so we don't have to clutter all devicetrees. https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste… PS10, Line 304: sc_enable_serial_irqs(dev); Why enable continuous mode first and then change the mode later? Can't we just set the final mode here? -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 10 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 24 Mar 2019 13:30:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Nico Huber (Code Review) 24 Mar '19

24 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 7: > At the moment the fhd mod board requires 3.3V from a separate cable, which causes elevated power consumption especially when the lid is closed or the machine is sleeping. > This is because the tapped source is always on. > Though if it was possible to provide power through the VCC3P power rail instead, the board could be supplied with power only when the display is supposed to be on. This would eliminate the extra cable and only requires that J1 jumper is closed on the board. I tried it myself and also measured a the corresponding pad but there seems to be no voltage present from the lvds connector with the current state of this patch. > > Maybe someone more knowledgeable has an idea on how to implement this? Did you also measure the voltage when Linux has booted? I would assume that it works in Linux. If that is the case, all that is left (as mentioned before) is to make libgfxinit aware of the panel at the DP connector (needs some restructuring, though). -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 7 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Sun, 24 Mar 2019 13:13:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/apollolake: Add HDA to disable_dev function
by Nico Huber (Code Review) 24 Mar '19

24 Mar '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31353 ) Change subject: intel/apollolake: Add HDA to disable_dev function ...................................................................... intel/apollolake: Add HDA to disable_dev function Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31353 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/chip.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9d72167..c3de4ee 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -532,6 +532,9 @@ silconfig->IpuEn = 0; break; #endif + case PCH_DEVFN_HDA: + silconfig->HdaEnable = 0; + break; default: printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", PCI_SLOT(dev->path.pci.devfn), -- To view, visit https://review.coreboot.org/c/coreboot/+/31353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06 Gerrit-Change-Number: 31353 Gerrit-PatchSet: 5 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Arthur Heymans (Code Review) 24 Mar '19

24 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 22: (3 comments) Please justify this by checking what the vendor firmware does. https://review.coreboot.org/#/c/18548/22/src/northbridge/intel/i945/raminit… File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/18548/22/src/northbridge/intel/i945/raminit… PS22, Line 2452: : for (i = 0; i < (2 * DIMM_SOCKETS); i++) { : if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) : dimm_mask |= (1 << i); : } I'm not fond of such arithmetics. https://review.coreboot.org/#/c/18548/22/src/northbridge/intel/i945/raminit… PS22, Line 2463: (dimm_mask & 3) != 3 you have to look up what this means, while the previous statement was very clear. https://review.coreboot.org/#/c/18548/22/src/northbridge/intel/i945/raminit… PS22, Line 2473: MCHBAR32(C1ODT) There is no documentation on this one and only very limited documentation on C0ODT. Did you observe with vendor firmware if this can differ from the setting in C0ODT? -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 10:48:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP
by Kyösti Mälkki (Code Review) 24 Mar '19

24 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32032 ) Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP ...................................................................... nb/intel/i945: Use DEBUG_RAM_SETUP Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 14 files changed, 23 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index ffb3bf9..a93009f 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -220,9 +220,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : boot_mode, NULL); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 423b4e8..461e394 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -271,9 +271,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, NULL); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index b2d4bb4..d23df35 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -172,9 +172,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : boot_mode, NULL); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 1257fa5..49bb1e5 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -231,9 +231,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, NULL); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 18a7721..6cb24a6 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -151,9 +151,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : boot_mode, NULL); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 52432a0..394522c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -279,9 +279,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, NULL); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 070ee59..0ca690b 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -208,9 +208,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 39e0ed5..e655ddf 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -211,9 +211,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 45cd9ec..0c1d7b9 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -209,9 +209,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index dbc4b6c..46ef808 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -244,9 +244,8 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, NULL); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d3ed277..08dd675 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -940,22 +940,8 @@ i945_setup_root_complex_topology(); -#if !CONFIG(HAVE_ACPI_RESUME) -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG(DEBUG_RAM_SETUP) - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + sdram_dump_mchbar_registers(); MCHBAR16(SSKPD) = 0xCAFE; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 8c08241..ebcc8bc 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -375,6 +375,7 @@ void dump_pci_device(unsigned int dev); void dump_pci_devices(void); void dump_spd_registers(void); +void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a93cf1e..05b5777 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -96,7 +96,6 @@ read32((void *)offset); } -#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -108,7 +107,6 @@ printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i)); } } -#endif static int memclk(void) { diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d1eee6..e9e66d1 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,8 +69,4 @@ void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); void udelay(u32 us); - -#if CONFIG(DEBUG_RAM_SETUP) -void sdram_dump_mchbar_registers(void); -#endif #endif /* RAMINIT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Gerrit-Change-Number: 32032 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by HAOUAS Elyes (Code Review) 24 Mar '19

24 Mar '19

Hello Patrick Rudolph, Arthur Heymans, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/18548 to look at the new patch set (#22). Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... nb/intel/i945: Programm CxODT value for each channel Programm C1ODT value for channel B. Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/18548/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP
by Arthur Heymans (Code Review) 24 Mar '19

24 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32032 ) Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Gerrit-Change-Number: 32032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 10:37:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Arthur Heymans (Code Review) 24 Mar '19

24 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31832/1/src/mainboard/gigabyte/ga-h61m-s2pv… File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig: https://review.coreboot.org/#/c/31832/1/src/mainboard/gigabyte/ga-h61m-s2pv… PS1, Line 25: select NORTHBRIDGE_INTEL_SANDYBRIDGE if BOARD_GIGABYTE_GA_H61MA_D3V : select NORTHBRIDGE_INTEL_IVYBRIDGE if BOARD_GIGABYTE_GA_H61M_S2PV > The selected northbridge in the code should not make much difference except for libgfxinit, which wi […] Ok, better add a comment here about libgfxinit and why the distinction is made. -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Mar 2019 10:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit March 2019