Hello Patrick Rudolph, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31755
to look at the new patch set (#4).
Change subject: device/pci_ops: Define pci_find_capability() just once
......................................................................
device/pci_ops: Define pci_find_capability() just once
Wrap the simple romstage implementation to be called
from ramstage.
Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/device/pci_device.c
M src/device/pci_early.c
M src/device/pci_ops.c
M src/drivers/usb/pci_ehci.c
M src/include/device/pci.h
M src/include/device/pci_ops.h
M src/soc/cavium/common/ecam.c
7 files changed, 94 insertions(+), 133 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31755/4
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31978 )
Change subject: Move calls to quick_ram_check() before CBMEM init
......................................................................
Patch Set 5: Code-Review+1
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31833
Change subject: console: qemu_debugcon support additional stages
......................................................................
console: qemu_debugcon support additional stages
Add support for bootblock and postcar, which were introduced on qemu
in the last few month.
Fixes non working debugcon in those stages.
Change-Id: I553f12c2105237d81ae3f492ec85b17434d8334c
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/include/console/qemu_debugcon.h
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31833/1
diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h
index 359e01a..a22c843 100644
--- a/src/include/console/qemu_debugcon.h
+++ b/src/include/console/qemu_debugcon.h
@@ -6,7 +6,8 @@
void qemu_debugcon_init(void);
void qemu_debugcon_tx_byte(unsigned char data);
-#if CONFIG(CONSOLE_QEMU_DEBUGCON) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
+#if CONFIG(CONSOLE_QEMU_DEBUGCON) && \
+ (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR || ENV_BOOTBLOCK)
static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); }
static inline void __qemu_debugcon_tx_byte(u8 data)
{
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22200 )
Change subject: nb/intel/sandybridge/raminit: Add extended memtest
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/22200/4/src/northbridge/intel/sandybridge/r…
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/#/c/22200/4/src/northbridge/intel/sandybridge/r…
PS4, Line 461: ram_check(basek << 10, (basek + (1 << 10)) << 10);
> That second argument has been ignored for ages now... […]
I agree. I'll have a look at the common API to get memory ranges next.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22200 )
Change subject: nb/intel/sandybridge/raminit: Add extended memtest
......................................................................
Patch Set 4:
(1 comment)
We could do somethink like this; if quick_ram_check() fails run the more thorough check in verbose mode. If necessary to save space, this could be behind config DEBUG_RAM_SETUP.
https://review.coreboot.org/#/c/22200/4/src/northbridge/intel/sandybridge/r…
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/#/c/22200/4/src/northbridge/intel/sandybridge/r…
PS4, Line 461: ram_check(basek << 10, (basek + (1 << 10)) << 10);
That second argument has been ignored for ages now...
To have generic primitive memtest is second reason to have common API to get TOLM/TOM (or TOM / TOM2 as AMD calls them).
You might want to call primitive_memtest() to actually write the entire range.
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Hello Alexander Couzens, Aaron Durbin, Patrick Rudolph, Julius Werner, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31978
to look at the new patch set (#5).
Change subject: Move calls to quick_ram_check() before CBMEM init
......................................................................
Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/intel/haswell/romstage.c
M src/include/lib.h
M src/lib/imd_cbmem.c
M src/lib/ramtest.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/packardbell/ms2290/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/x4x/raminit.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
13 files changed, 11 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31978/5
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31841 )
Change subject: Documentation/soc/intel: Add MP Initialization document
......................................................................
Patch Set 3:
> (6 comments)
>
> Thank you for this patch.
>
> IMHO, it would be nice to explain a bit more the advantages and
> inconvenients of each option: as I understand it, the open-source
> code can initialize less things but it is open-source, as opposed
> to FSP. And the third option would be a mixture of both worlds I
> guess?
yes, your understanding is correct for #3 one. the pieces that we can't open source right now in MP init flow, will be part of FSP Mp service using coreboot PPI, rest is anyway open source.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27118 )
Change subject: nb/intel/sandybridge: Fix domain resources
......................................................................
Patch Set 1:
> Patch Set 1:
>
> Has this been fixed?
Using PCI ops on the DEVICE_PATH_DOMAIN is not done anymore. The other suggestions need to be adressed however.
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