Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31912
Change subject: mb/asus/{p5qc,p5q_pro}: Correct mapping of PCI-E 1x ports
......................................................................
mb/asus/{p5qc,p5q_pro}: Correct mapping of PCI-E 1x ports
There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to
the first three functions of 1c.
Confirmed on a p5q_pro board.
Change-Id: I779400494e27bf046996512d1f772311e6e4e091
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31912/1
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
index d645609..a1310b9 100644
--- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
@@ -52,8 +52,8 @@
device pci 1a.7 on end # USB
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1
- device pci 1c.1 off end # PCIe 2
- device pci 1c.2 off end # PCIe 3
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 on end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 on end # PCIe 5 MARVELL IDE
device pci 1c.5 on end # PCIe 6
diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
index 8420124..b6146ec 100644
--- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
@@ -52,8 +52,8 @@
device pci 1a.7 on end # USB
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1
- device pci 1c.1 off end # PCIe 2
- device pci 1c.2 off end # PCIe 3
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 on end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 on end # PCIe 5 MARVELL IDE
device pci 1c.5 on end # PCIe 6
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I779400494e27bf046996512d1f772311e6e4e091
Gerrit-Change-Number: 31912
Gerrit-PatchSet: 1
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-MessageType: newchange
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31993
Change subject: gale: add dev switch back as physical presence GPIO
......................................................................
gale: add dev switch back as physical presence GPIO
gale has a button which is essentially used as a
"physical presence" button. Its only use is to emulate
^D or ^U on boot when the button is pressed.
(See depthcharge src/board/gale/board.c)
Previously (and currently in CrOS firmware branch) this
GPIO was defined as the physical developer switch,
and read as such in depthcharge. It was removed in
cleanup patch CB:18980.
Add the GPIO back as "physical presence", which will
be read by depthcharge in CL:1532492.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6
Signed-off-by: Joel Kitching <kitching(a)google.com>
---
M src/mainboard/google/gale/chromeos.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31993/1
diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c
index 939b061..78ca900 100644
--- a/src/mainboard/google/gale/chromeos.c
+++ b/src/mainboard/google/gale/chromeos.c
@@ -25,6 +25,8 @@
#include <timer.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#define PP_SW 41
+#define PP_POL ACTIVE_LOW
#define REC_POL ACTIVE_LOW
#define WP_POL ACTIVE_LOW
@@ -69,6 +71,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
+ {PP_SW, PP_POL, read_gpio(DEV_SW), "physical presence"},
{get_rec_sw_gpio_pin(), REC_POL,
read_gpio(get_rec_sw_gpio_pin()), "recovery"},
{get_wp_status_gpio_pin(), WP_POL,
--
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Gerrit-Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6
Gerrit-Change-Number: 31993
Gerrit-PatchSet: 1
Gerrit-Owner: Joel Kitching <kitching(a)google.com>
Gerrit-MessageType: newchange
Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32030
Change subject: mainboard/google/sarien: skip tpm check when !verstage
......................................................................
mainboard/google/sarien: skip tpm check when !verstage
The TPM driver isn't loaded in other stages but verstage so when we try
to communicate with the TPM it fails. We don't need to communicate with
it anyway since the TPM won't continue to tell us that recovery was
requested, only the first query responds with the recovery request.
BRANCH=none
BUG=b:129150074
TEST=1)boot arcada without recovery and notice that the "tpm transaction
failed" log lines are no longer present. 2) boot into recovery using the
ESC refresh power key combination and verify that the recovery reason
was "recovery button pressed"
Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4
Signed-off-by: Jett Rink <jettrink(a)chromium.org>
---
M src/mainboard/google/sarien/chromeos.c
1 file changed, 19 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32030/1
diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c
index 1e363fd..2bef829 100644
--- a/src/mainboard/google/sarien/chromeos.c
+++ b/src/mainboard/google/sarien/chromeos.c
@@ -30,7 +30,6 @@
REC_MODE_NOT_REQUESTED,
REC_MODE_REQUESTED,
};
-static enum rec_mode_state saved_rec_mode;
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -84,25 +83,31 @@
int get_recovery_mode_switch(void)
{
- enum rec_mode_state state = saved_rec_mode;
- uint8_t recovery_button_state = 0;
+ static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
+ enum rec_mode_state state = REC_MODE_NOT_REQUESTED;
+ uint8_t cr50_state = 0;
- /* Check the global variable first. */
- if (state == REC_MODE_NOT_REQUESTED)
- return 0;
- else if (state == REC_MODE_REQUESTED)
- return 1;
+ /* Check cached state, since TPM will only tell us the first time */
+ if (saved_rec_mode != REC_MODE_UNINITIALIZED)
+ return saved_rec_mode == REC_MODE_REQUESTED;
- state = REC_MODE_NOT_REQUESTED;
+ /*
+ * Read one-time recovery request from cr50 in verstage only since
+ * the TPM driver won't be set up in time for other stages like romstage
+ * and the value from the TPM would be wrong anyway since the verstage
+ * read would have cleared the value on the TPM.
+ *
+ * The TPM recovery request is passed between stages through the
+ * vboot_get_shared_data or cbmem depending on stage.
+ */
+ if (ENV_VERSTAGE &&
+ tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS &&
+ cr50_state)
+ state = REC_MODE_REQUESTED;
/* Read state from the GPIO controlled by servo. */
if (cros_get_gpio_value(CROS_GPIO_REC))
state = REC_MODE_REQUESTED;
- /* Read one-time recovery request from cr50. */
- else if (tlcl_cr50_get_recovery_button(&recovery_button_state)
- == TPM_SUCCESS)
- state = recovery_button_state ?
- REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED;
/* Store the state in case this is called again in verstage. */
saved_rec_mode = state;
--
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Gerrit-Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4
Gerrit-Change-Number: 32030
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Gerrit-Owner: Jett Rink <jettrink(a)chromium.org>
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 )
Change subject: soc/intel/braswell/southcluster.c: Correct serial IRQ support
......................................................................
Patch Set 11:
(1 comment)
Correction after comment.
https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste…
File src/soc/intel/braswell/southcluster.c:
https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste…
PS10, Line 304: sc_enable_serial_irqs(dev);
> Why enable continuous mode first and then change the […]
No, required to set continuous mode for at least one frame before switching into quiet mode.
--
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Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29398
to look at the new patch set (#11).
Change subject: soc/intel/braswell/southcluster.c: Correct serial IRQ support
......................................................................
soc/intel/braswell/southcluster.c: Correct serial IRQ support
Serial IRQ was configured in quiet mode, but not enabled.
Enable serial IRQ and use 'enum seriirq_mode' as a devicetree
option.
enable_serirq_quiet_mode() is renamed to
sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to
set the mode.
BUG=N/A
TEST=Portwell PQ7-M107
Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/soc/intel/braswell/chip.h
M src/soc/intel/braswell/include/soc/lpc.h
M src/soc/intel/braswell/southcluster.c
3 files changed, 38 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29398/11
--
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