coreboot-gerrit March 2019

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Change in ...coreboot[master]: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by ...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31357 to review the following change. Change subject: src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware G505S does not have any SAS or NVMe controllers and could not have a TPM, so it makes sense to disable the related SeaBIOS options for this laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5b2ee6403d7d2298725729d8d833e37627a4f202 --- M src/mainboard/lenovo/g505s/Kconfig A src/mainboard/lenovo/g505s/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31357/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..71ab909 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,8 @@ string default "1002,990b" +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios new file mode 100644 index 0000000..8d3957b --- /dev/null +++ b/src/mainboard/lenovo/g505s/config_seabios @@ -0,0 +1,6 @@ +# +# SeaBIOS custom configuration for Lenovo G505S +# +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set -- To view, visit https://review.coreboot.org/c/coreboot/+/31357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b2ee6403d7d2298725729d8d833e37627a4f202 Gerrit-Change-Number: 31357 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/945 boards: Use smp_write_pci_intsrc()
by Kyösti Mälkki (Code Review) 25 Jun '19

25 Jun '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30740 Change subject: intel/945 boards: Use smp_write_pci_intsrc() ...................................................................... intel/945 boards: Use smp_write_pci_intsrc() Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/apple/macbook21/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/lenovo/z61t/mptable.c 4 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30740/1 diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index f508eaf..b11b7bb 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x16); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x11); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x15); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x13); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x10); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x12); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x13); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x03, 0x02, 0x10); /* SATA 0:1f.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x03, 0x03, 0x00, 0x02, 0x13); /* Firewire 3:03.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 7b23d5a..091fea7 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -42,23 +42,23 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/z61t/mptable.c b/src/mainboard/lenovo/z61t/mptable.c index 8a9ee48..86c6f6d 100644 --- a/src/mainboard/lenovo/z61t/mptable.c +++ b/src/mainboard/lenovo/z61t/mptable.c @@ -42,21 +42,21 @@ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); -- To view, visit https://review.coreboot.org/c/coreboot/+/30740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Gerrit-Change-Number: 30740 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add VBNV flags to save the Cr50 recovery switch state
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31800 Change subject: security/vboot: Add VBNV flags to save the Cr50 recovery switch state ...................................................................... security/vboot: Add VBNV flags to save the Cr50 recovery switch state Add flags to save the Cr50 recovery switch state. This ensures that the Cr50 recovery switch state is only read during verstage. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vbnv_layout.h 4 files changed, 71 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31800/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 636e5e3..8156fc5 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,6 +140,42 @@ return vbnv_data(RECOVERY_OFFSET); } +/* Save the recovery switch state into VBNV. */ +void set_recovery_switch_into_vbnv(int recovery_switch) +{ + uint8_t vbnv_copy[VBOOT_VBNV_BLOCK_SIZE]; + + read_vbnv(vbnv_copy); + + vbnv_copy[MISC_FLAGS_OFFSET] |= MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK; + if (recovery_switch) + vbnv_copy[MISC_FLAGS_OFFSET] |= + MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + else + vbnv_copy[MISC_FLAGS_OFFSET] &= + ~MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + + save_vbnv(vbnv_copy); +} + +/* Read the recovery switch state from VBNV. */ +int get_recovery_switch_from_vbnv(int *recovery_switch) +{ + uint8_t misc_flags; + vbnv_setup(); + misc_flags = vbnv_data(MISC_FLAGS_OFFSET); + + if (!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK)) + return -1; + + *recovery_switch = + !!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK); + + return 0; +} + /* Read the BOOT_OPROM_NEEDED flag from VBNV. */ int vboot_wants_oprom(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689f..367a376 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,6 +25,22 @@ void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); + +/** + * Save the recovery switch state into VBNV + * + * @param recovery_switch Current state of the recovery switch. + */ +void set_recovery_switch_into_vbnv(int recovery_switch); +/** + * Get the recovery switch date from VBNV + * + * @param recovery_switch On success, set to the saved recovery switch state. + * + * @return 0 on success, !=0 if recovery switch state not saved. + */ +int get_recovery_switch_from_vbnv(int *recovery_switch); + int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4..322fcf7 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -43,7 +43,9 @@ #define DEV_ENABLE_UDC 0x40 #define MISC_FLAGS_OFFSET 8 -#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK 0x10 +#define MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK 0x20 #define KERNEL_FIELD_OFFSET 11 #define CRC_OFFSET 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/31800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Gerrit-Change-Number: 31800 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/sarien: Save the Cr50 recovery switch state in VBNV
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31801 Change subject: mainboard/sarien: Save the Cr50 recovery switch state in VBNV ...................................................................... mainboard/sarien: Save the Cr50 recovery switch state in VBNV Update sarien so the Cr50 recovery switch is only read during verstage and save the recovery switch state to VBNV. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31801/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Gerrit-Change-Number: 31801 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: currently riscv does not support fit payload, remove redundant...
by Xiang Wang (Code Review) 23 Jun '19

23 Jun '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31477 Change subject: riscv: currently riscv does not support fit payload, remove redundant code ...................................................................... riscv: currently riscv does not support fit payload, remove redundant code This code is not necessary and will trigger an error when I try to boot linux with bbl.If you want to add this code, it is recommended to add it with the support code of the fit payload. Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/boot.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31477/1 diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 29064b1..0c8143f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -32,14 +32,7 @@ { void (*doit)(int hart_id, void *fdt); int hart_id; - void *fdt = prog_entry_arg(prog); - - /* - * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS - * instead. - */ - if (fdt == NULL) - fdt = HLS()->fdt; + void *fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); -- To view, visit https://review.coreboot.org/c/coreboot/+/31477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Gerrit-Change-Number: 31477 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths
by Xiang Wang (Code Review) 23 Jun '19

23 Jun '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31976 Change subject: riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths ...................................................................... riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/mcall.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31976/1 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 192d2b4..652d21b 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -20,14 +20,16 @@ // nice to have. #if __riscv_xlen == 64 #define HLS_SIZE 88 +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) #endif #if __riscv_xlen == 32 #define HLS_SIZE 52 +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 4) #endif -/* We save 37 registers, currently. */ -#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) #ifndef __ASSEMBLER__ -- To view, visit https://review.coreboot.org/c/coreboot/+/31976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Gerrit-Change-Number: 31976 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: enable DDR low power feature
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32010 Change subject: mediatek/mt8183: enable DDR low power feature ...................................................................... mediatek/mt8183: enable DDR low power feature BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/emi.h 6 files changed, 132 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32010/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 3ca5c22..15771ee 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -154,9 +154,6 @@ for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { - /* Track rising and update rising/falling together */ - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], - 0x1 << 29); clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), @@ -172,8 +169,6 @@ (0x3 << 18) | (0x3 << 16)); } - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); - /* Rx DLY tracking setting (Static) */ clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), @@ -181,6 +176,7 @@ clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); for (u8 b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[9], @@ -201,10 +197,12 @@ static void dramc_hw_dqs_gating_tracking(u8 chn) { - setbits_le32(&ch[chn].ao.stbcal, (0x3 << 26) | (0x1 << 0)); + clrsetbits_le32(&ch[chn].ao.stbcal, + (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4), + (0x3 << 26) | (0x1 << 0)); clrsetbits_le32(&ch[chn].ao.stbcal1, (0xffff << 16) | (0x1 << 8) | (0x1 << 6), - (0x1 << 16) | (0x1 << 8) | (0x0 << 6)); + (0x1 << 16) | (0x1 << 8) | (0x1 << 6)); clrsetbits_le32(&ch[chn].phy.misc_ctrl0, (0x1 << 24) | (0x1f << 11) | (0xf << 0), @@ -262,6 +260,72 @@ dramc_set_broadcast(broadcast_bak); } + +static void DramcDummyReadForTrackingEnable(u8 chn) +{ + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16); + + for (size_t r = 0; r < 2; r++) + for (size_t i = 0; i < 4; i++) + write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i], + 0xaaaa5555); + + clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + for (size_t r = 0; r < 2; r++) { + clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, + (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), + (0x7fff << 0) | (0x3f0 << 17)); + setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + } + + clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); +} + +static void SetCKE2RankIndependent(u8 chn) +{ + clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); + clrsetbits_le32(&ch[chn].ao.ckectrl, + (0x1 << 1) | (0xf << 8) | (0x7 << 13), + (0x4 << 8) | (0x2 << 13)); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits_le32(&ch[chn].ao.shu[shu].conf[2], + (0x1 << 29) | (0x1 << 31)); + clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9); +} + +static void dramc_pa_improve(u8 chn) +{ + clrbits_le32(&ch[chn].ao.clkar, 0xffff); + clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); +} + +static void dramc_set_mr13_vrcg_to_Normal(u8 chn) +{ + for (u8 rank = 0; rank < RANK_MAX; rank++) + dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); +} + +static void dramc_enable_dramc_dcm(void) +{ + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + (0x7 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[chn].ao.clkar, 0x1 << 31); + } +} + void dramc_runtime_config(void) { clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); @@ -270,39 +334,83 @@ transfer_pll_to_spm_control(); setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25); + dramc_show("%s with: broadcast %d\n", __func__, dramc_get_broadcast()); + + + /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); + /* HW_GATING: ON */ dramc_hw_gating_init(); dramc_hw_gating_onoff(CHANNEL_A, true); + dramc_hw_gating_onoff(CHANNEL_B, true); + /* HW_GATING DBG: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) clrbits_le32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); + /* DUMMY_READ_FOR_TRACKING: ON */ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + DramcDummyReadForTrackingEnable(chn); + + /* ZQCS_ENABLE_LP4: ON */ clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30); + /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ dramc_phy_low_power_enable(); dramc_enable_phy_dcm(true); + /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); + /* SPM_CONTROL_AFTERK: ON */ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef); write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef); + /* IMPEDANCE_TRACKING: ON */ dramc_impedance_tracking_enable(); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + /* TEMP_SENSOR: ON */ clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28); setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); - clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 18); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + + /* PER_BANK_REFRESH: ON */ + clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + + /* HW_SAVE_FOR_SR: ON */ + clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); + setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0); + clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); + + /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */ + SetCKE2RankIndependent(chn); + + /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */ + clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); + clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19); + + /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */ + dramc_pa_improve(chn); + + /* DRAM DRS DISABLE */ + clrsetbits_le32(&ch[chn].ao.drsctrl, + (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), + (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | + (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26); + + dramc_set_mr13_vrcg_to_Normal(chn); } + + enable_emi_dcm(); + dramc_enable_dramc_dcm(); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f3c76a9..11a46bb 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -127,7 +127,7 @@ setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); } -static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 757a453..b7d7d7b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -292,6 +292,15 @@ emi_init2(params); } +void enable_emi_dcm(void) +{ + clrsetbits_le32(&emi_regs->conm, 0xff << 24, 0x0 << 24); + clrsetbits_le32(&emi_regs->conn, 0xff << 24, 0x0 << 24); + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].emi.chn_conb, 0xff << 24, 0x0 << 24); +} + static void do_calib(const struct sdram_params *params) { dramc_apply_pre_calibration_config(); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 781443a..7e0f34e 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -127,4 +127,6 @@ void dramc_calibrate_all_channels(const struct sdram_params *params); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value); + #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 2487504..f0720a7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -265,10 +265,7 @@ struct dramc_ao_regs_rk { uint32_t dqsosc; uint32_t rsvd_1[5]; - uint32_t dummy_rd_wdata0; - uint32_t dummy_rd_wdata1; - uint32_t dummy_rd_wdata2; - uint32_t dummy_rd_wdata3; + uint32_t dummy_rd_wdata[4]; uint32_t dummy_rd_adr; uint32_t dummy_rd_bk; uint32_t pre_tdqsck[12]; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 81e3d91..2c04a50 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -38,6 +38,7 @@ int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); +void enable_emi_dcm(void); void mt_set_emi(const struct sdram_params *params); void mt_mem_init(const struct sdram_params *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/32010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Gerrit-Change-Number: 32010 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

8 20

Change in ...coreboot[master]: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31193 Change subject: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place ...................................................................... cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31193/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31c921d..733205a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -37,6 +37,8 @@ #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_MISC_ENABLE 0x1a0 +#define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define SPEED_STEP_ENABLE_BIT (1 << 16) #define IA32_ENERGY_PERF_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1b27eef..0d469c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -96,10 +96,6 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) - /* Read BCLK from MSR */ unsigned int bus_freq_khz(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/31193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Gerrit-Change-Number: 31193 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: x86/smmstub: Fix compiling with external toolchains
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30504 Change subject: x86/smmstub: Fix compiling with external toolchains ...................................................................... x86/smmstub: Fix compiling with external toolchains Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30504/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..e6add1d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,8 +47,8 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. -$(obj)/smmstub/smmstub.o: $$(smmstub-objs) - $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ +$(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/30504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb Gerrit-Change-Number: 30504 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: WIP: mediatek/mt8183: Add infra group DCM setting
by Weiyi Lu (Code Review) 21 Jun '19

21 Jun '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31977 to review the following change. Change subject: WIP: mediatek/mt8183: Add infra group DCM setting ...................................................................... WIP: mediatek/mt8183: Add infra group DCM setting Add infra group DCM setting BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/pll.h M src/soc/mediatek/mt8183/pll.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31977/1 diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 5a5f58d..d1c7cd1 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -270,4 +270,13 @@ SPI_HZ = MAINPLL_D5_D2_HZ, }; +enum { + DCM_INFRA_BUS_MASK = 0x40907ffb, + DCM_INFRA_BUS_ON = 0x40900843, + DCM_INFRA_MEM_ON = 0x1 << 27, + DCM_INFRA_P2PRX_MASK = 0xf, + DCM_INFRA_PERI_MASK = 0xf03ffffb, + DCM_INFRA_PERI_ON = 0xf03f83e3, +}; + #endif /* SOC_MEDIATEK_MT8183_PLL_H */ diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de..4157c1d 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -344,6 +344,12 @@ /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, DCM_INFRA_BUS_MASK, + DCM_INFRA_BUS_ON); + setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, DCM_INFRA_PERI_MASK, + DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); -- To view, visit https://review.coreboot.org/c/coreboot/+/31977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Gerrit-Change-Number: 31977 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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