coreboot-gerrit March 2019

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Change in ...coreboot[master]: mediatek/mt8183: modify vsim2 calibration
by hsin-hsiung wang (Code Review) 21 Jun '19

21 Jun '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32057 Change subject: mediatek/mt8183: modify vsim2 calibration ...................................................................... mediatek/mt8183: modify vsim2 calibration This patch modifies vsim2 calibration to meet 2.7V BUG=b:126139364 BRANCH=none TEST=measure vsim2 voltage with multimeter Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32057/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 02937ba..157f6be 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -27,6 +27,21 @@ PMIC_CPSDSA4 = 0x0a2e, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VSIM2_ANA_CON0 = 0x1c34, +}; + +enum { + VSIM2_CALI_POS_0_MV = 0, + VSIM2_CALI_POS_10_MV, + VSIM2_CALI_POS_20_MV, + VSIM2_CALI_POS_30_MV, + VSIM2_CALI_POS_40_MV, + VSIM2_CALI_POS_50_MV, + VSIM2_CALI_POS_60_MV, + VSIM2_CALI_POS_70_MV, + VSIM2_CALI_POS_80_MV, + VSIM2_CALI_POS_90_MV, + VSIM2_CALI_POS_100_MV, }; struct pmic_setting { diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 3dc9fe2..bcddb783 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -769,6 +769,23 @@ lp_setting[i].mask, lp_setting[i].shift); } +static void pmic_set_vsim2_cali(void) +{ + u16 vsim2_cali; + + /* [11:8]=0x8, RG_VSIM2_VOSEL = 2.7V */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, 0x8, 0xF, 8); + + /* [3:0], RG_VSIM2_VOCAL */ + vsim2_cali = pwrap_read_field(PMIC_VSIM2_ANA_CON0, 0xF, 0); + if (vsim2_cali > VSIM2_CALI_POS_60_MV) + vsim2_cali -= VSIM2_CALI_POS_60_MV; + else + vsim2_cali = VSIM2_CALI_POS_0_MV; + + pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_cali, 0xF, 0); +} + void mt6358_init(void) { if (pwrap_init()) @@ -780,4 +797,5 @@ wk_sleep_voltage_by_ddr(); wk_power_down_seq(); mt6358_lp_setting(); + pmic_set_vsim2_cali(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe Gerrit-Change-Number: 32057 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

6 32

Change in ...coreboot[master]: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands
by Frans Hendriks (Code Review) 20 Jun '19

20 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30800 Change subject: southbridge/intel/common/smbus.{c,h}: Add support for I2C commands ...................................................................... southbridge/intel/common/smbus.{c,h}: Add support for I2C commands Intel Braswell supports communication with I2C device using SMBus controller. This support is missing in actual smbus routines. Added i2c_block_read() and i2c_block_write() which configures the SMBus controller into I2C mode before sending the commands. Added do_i2c_block_write() for sending block writes in I2C mode. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h 2 files changed, 124 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30800/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index de4ff91..3b50e6b 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,7 @@ */ #include <arch/io.h> +#include <device/pci.h> #include <console/console.h> #include <device/smbus_def.h> #include <stdlib.h> @@ -96,9 +98,8 @@ unsigned char val; smbus_delay(); val = inb(smbus_base + SMBHSTSTAT); - if ((val & SMBHSTSTS_HOST_BUSY)) { + if ((val & SMBHSTSTS_HOST_BUSY)) break; - } } while (--loops); return loops ? 0 : -1; } @@ -208,6 +209,7 @@ int slave_bytes; int bytes_read = 0; unsigned int loops = SMBUS_TIMEOUT; + if (smbus_wait_until_ready(smbus_base) < 0) return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -220,7 +222,7 @@ /* Set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); /* Set the command/address... */ - outb(cmd & 0xff, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTCMD); /* Set up for a block data read */ outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, (smbus_base + SMBHSTCTL)); @@ -350,6 +352,19 @@ } /* Only since ICH5 */ +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + return do_i2c_block_read((unsigned int)reg, device, cmd, bytes, buf); +} + int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, const unsigned int bytes, u8 *buf) { @@ -418,3 +433,102 @@ return bytes_read; } + +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf) +{ + struct device *smbus_dev; + u32 reg; + u32 smb_ctlr_reg; + int status; + + /* SMBus I/O BAR */ + smbus_dev = dev_find_slot(0, PCI_DEVFN(smbus_devnr, smbus_func)); + reg = pci_read_config32(smbus_dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE; + + smb_ctlr_reg = pci_read_config32(smbus_dev, 0x40); + + /* Enable I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg | 4); + + status = do_i2c_block_write((unsigned int)reg, device, cmd, bytes, + buf); + + /* Restore I2C_EN bit */ + pci_write_config32(smbus_dev, 0x40, smb_ctlr_reg); + + return status; +} + +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf) +{ + u8 status; + int bytes_write; + unsigned int loops = SMBUS_TIMEOUT; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Set up transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, + smbus_base + SMBHSTCTL); + + /* Set the slave address */ + outb(((device & 0x7f) << 1), smbus_base + SMBXMITADD); + + outb(cmd, smbus_base + SMBHSTCMD); + outb(cmd, smbus_base + SMBHSTDAT1); + + /* Number of bytes to write */ + outb(bytes, smbus_base + SMBHSTDAT0); + + /* Set up for a smbus block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA, + (smbus_base + SMBHSTCTL)); + + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Send first byte from buffer */ + outb(*buf++, smbus_base + SMBBLKDAT); + + for (bytes_write = 0; bytes_write < bytes; bytes_write++) { + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), + smbus_base + SMBHSTCTL); + + /* poll for it to start */ + if (smbus_wait_until_active(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT; + + loops = SMBUS_TIMEOUT; + do { + loops--; + status = inb(smbus_base + SMBHSTSTAT); + if (status & (SMBHSTSTS_FAILED | /* FAILED */ + SMBHSTSTS_BUS_ERR | /* BUS ERR */ + SMBHSTSTS_DEV_ERR)) /* DEV ERR */ + return SMBUS_ERROR; + } while (!(status & SMBHSTSTS_BYTE_DONE) && loops); + + if (status & SMBHSTSTS_BYTE_DONE) { + if (bytes_write+1 < bytes) + outb(*buf++, smbus_base + SMBBLKDAT); + if ((bytes_write + 1 >= bytes) && (bytes > 1)) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | + SMBHSTCNT_LAST_BYTE, + smbus_base + SMBHSTCTL); + } + + outb(status & (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR), + smbus_base + SMBHSTSTAT); + } else { + return SMBUS_ERROR; + } + } + return (bytes_write+1); +} + diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..f272165 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,4 +44,10 @@ /* Only since ICH5 */ int do_i2c_block_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); +int do_i2c_block_write(unsigned int smbus_base, u8 device, u8 cmd, + const unsigned int bytes, u8 *buf); +int i2c_block_read(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); +int i2c_block_write(u8 smbus_devnr, u8 smbus_func, unsigned int device, u8 cmd, + u32 bytes, u8 *buf); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Gerrit-Change-Number: 30800 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

10 56

Change in ...coreboot[master]: superio/fintek: Add code for superio f81803a
by Richard Spiegel (Code Review) 18 Jun '19

18 Jun '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31374 Change subject: superio/fintek: Add code for superio f81803a ...................................................................... superio/fintek: Add code for superio f81803a In preparation to add padmelon to coreboot, add the the code for the f81803a superio. This code will also include ways to program fan control. TEST=To be tested later with padmelon board. Change-Id: I1d9a79f681be795dbd07fd0f0f179b06915e07ab Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/superio/fintek/Makefile.inc A src/superio/fintek/common/fan_control.h A src/superio/fintek/f81803a/Kconfig A src/superio/fintek/f81803a/Makefile.inc A src/superio/fintek/f81803a/acpi/superio.asl A src/superio/fintek/f81803a/f81803a.h A src/superio/fintek/f81803a/f81803a_hwm.h A src/superio/fintek/f81803a/fan_control.c A src/superio/fintek/f81803a/superio.c 9 files changed, 822 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31374/1 diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 796e519..db683fd 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,3 +26,4 @@ subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +subdirs-y += f81803a diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h new file mode 100644 index 0000000..8828c4b --- /dev/null +++ b/src/superio/fintek/common/fan_control.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_FAN_CONTROL_H +#define SUPERIO_FINTEK_FAN_CONTROL_H + +#include <stdint.h> +#include <arch/io.h> + +#define EXTERNAL_SENSOR1 1 +#define EXTERNAL_SENSOR2 2 +#define EXTERNAL_SENSOR3 3 +#define EXTERNAL_SENSOR_4 4 +#define TEMP_SENSOR_THERMISTOR 0 +#define TEMP_SENSOR_BJT 1 +#define TEMP_SENSOR_DEFAULT 2 + +#define FAN_TYPE_PWM_PUSH_PULL 0 +#define FAN_TYPE_DAC_POWER 1 +#define FAN_TYPE_PWM_OPEN_DRAIN 2 +#define FAN_TYPE_SET_BY_STRAP 3 +#define FAN_TYPE_PWM_CHECK 1 /* bit 0 must be 0 for PWM */ + +#define FAN_MODE_AUTO_RPM 0 +#define FAN_MODE_AUTO_PWM_DAC 1 +#define FAN_MODE_MANUAL_RPM 2 +#define FAN_MODE_MANUAL_PWM_DAC 3 +#define FAN_MODE_DEFAULT 4 + +#define FAN_PWM_FREQ_23500 0 +#define FAN_PWM_FREQ_11750 1 +#define FAN_PWM_FREQ_5875 2 +#define FAN_PWM_FREQ_220 3 + +#define FAN_TEMP_PECI 0 +#define FAN_TEMP_EXTERNAL_1 1 +#define FAN_TEMP_EXTERNAL_2 2 +#define FAN_TEMP_TSI 4 +#define FAN_TEMP_MXM 5 + +#define FAN_UP_RATE_2HZ 0 +#define FAN_UP_RATE_5HZ 1 +#define FAN_UP_RATE_10HZ 2 +#define FAN_UP_RATE_20HZ 3 +#define FAN_UP_RATE_DEFAULT 4 +#define FAN_UP_RATE_JUMP 8 + +#define FAN_DOWN_RATE_2HZ 0 +#define FAN_DOWN_RATE_5HZ 1 +#define FAN_DOWN_RATE_10HZ 2 +#define FAN_DOWN_RATE_20HZ 3 +#define FAN_DOWN_RATE_DEFAULT 4 +#define FAN_DOWN_RATE_SAME_AS_UP 5 +#define FAN_DOWN_RATE_JUMP 8 + +#define FAN_FOLLOW_STEP 0 +#define FAN_FOLLOW_INTERPOLATION 1 + +#define HWM_STATUS_SUCCESS 0 +#define HWM_STATUS_INVALID_FAN -1 +#define HWM_STATUS_INVALID_TEMP_SOURCE -2 +#define HWM_STATUS_INVALID_TYPE -3 +#define HWM_STATUS_INVALID_MODE -4 +#define HWM_STATUS_INVALID_RATE -5 +#define HWM_STATUS_INVALID_FREQUENCY -6 +#define HWM_STATUS_INVALID_TEMP_SENSOR -7 +#define HWM_STATUS_INVALID_BOUNDARY_VALUE -8 +#define HWM_STATUS_INVALID_SECTION_VALUE -9 +#define HWM_STATUS_BOUNDARY_WRONG_ORDER -20 +#define HWM_STATUS_SECTIONS_WRONG_ORDER -21 +#define HWM_STATUS_WARNING_SENSOR_DISCONECTED 1 +#define HWM_STATUS_WARNING_FAN_NOT_PWM 2 + +/* + * Boundaries order is from highest temp. to lowest. Values from 0 to 127. + * Boundaries should be defined as u8 boundaries[fintek_boundaries_size]. + */ +#define fintek_boundaries_size 4 +/* + * Section defines the duty_cycle/voltage to be used based on where the + * temperature lies with respect to the boundaries. There are 5 sections + * (4 boundaries) and the order must be from highest to lowest. Values + * from 0% to 100%, will be converted internally to percent of 255. + * Sections should be defined as u8 sections[fintek_sections_size]. + */ +#define fintek_sections_size 5 + +int set_sensor_type(u16 base_address, u8 sensor, u8 type); +int set_fan_temperature_source(u16 base_address, u8 fan, u8 source); +int set_fan_type_mode(u16 base_address, u8 fan, u8 type, u8 mode); +int set_pwm_frequency(u16 base_address, u8 fan, u8 frequency); +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections); +int set_fan_speed_change_rate(u16 base_address, u8 fan, u8 rate_up, + u8 rate_down); + +#endif /* SUPERIO_FINTEK_FAN_CONTROL_H */ diff --git a/src/superio/fintek/f81803a/Kconfig b/src/superio/fintek/f81803a/Kconfig new file mode 100644 index 0000000..f1f6ef3 --- /dev/null +++ b/src/superio/fintek/f81803a/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_FINTEK_F81803A + bool + select SUPERIO_FINTEK_COMMON_PRE_RAM + +config SUPERIO_FINTEK_F81803A_FAN_CONTROL + bool + depends on SUPERIO_FINTEK_COMMON_PRE_RAM + default n diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc new file mode 100644 index 0000000..a953b4a --- /dev/null +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c +endif + +romstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A_FAN_CONTROL) += fan_control.c diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl new file mode 100644 index 0000000..7568131 --- /dev/null +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the F81803A SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Not implemented + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0xa ACPI/PME/ERP Partially implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#define F81803A_SHOW_PME +#include <superio/acpi/pnp.asl> + + + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_PME + #undef SUPERIO_PME_LDN + #define SUPERIO_PME_LDN 0x0A + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1 /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(SUPERIO_PME_LDN) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } +#endif + +} diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h new file mode 100644 index 0000000..15361f3 --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Datasheet: + * - Name: F81803A + */ + +#ifndef SUPERIO_FINTEK_F81803_H +#define SUPERIO_FINTEK_F81803_H + +/* Logical Device Numbers (LDN) */ +#define F81803A_SP1 0x01 /* UART1 */ +#define F81803A_SP2 0x02 /* UART2 */ +#define F81803A_HWM 0x04 /* Hardware Monitor */ +#define F81803A_KBC 0x05 /* Keyboard/Mouse */ +#define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81803A_WDT 0x07 /* Watch Dog Timer */ +#define F81803A_PME 0x0a /* Power Management Events (PME) */ + +/* registers in Fintek F81803A */ +#define LDN_REG 0x07 + +/* Global Control Registers */ +#define CLOCK_SELECT_REG 0x26 +#define FUNC_PROG_SELECT (1<<3) +#define CONFIG_PORT_SELECT_REG 0x27 + +#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ +#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG 0x2C +#define WAKEUP_CONTROL_REG 0x2d + +/* LUN A - PME, ACPI, ERP */ +#define PME_DEVICE_ENABLE_REG 0x30 +#define PME_ENABLE (1<<0) +#define PME_ERP_ENABLE_REG 0xE0 +#define ERP_ENABLE (1<<7) +#define ERP_PME_EN (1<<1) +#define ERP_PSOUT_EN (1<<0) +#define PME_ERP_CONTROL_1_REG 0xE1 +#define PME_ERP_CONTROL_2_REG 0xE2 +#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 +#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 +#define PME_ERP_MODE_SELECT_REG 0xEC +#define PME_EVENT_ENABLE_1_REG 0xF0 +#define PME_EVENT_STATUS_1_REG 0xF1 +#define PME_EVENT_ENABLE_2_REG 0xF2 +#define PME_EVENT_STATUS_2_REG 0xF3 +#define PME_ACPI_CONTROL_1_REG 0xF4 +#define PME_ACPI_CONTROL_2_REG 0xF5 +#define PME_ACPI_CONTROL_3_REG 0xF6 +#define PME_ACPI_CONTROL_4_REG 0xF7 +#define PME_ACPI_CONTROL_5_REG 0xFB +#define PME_ACPI_CONTROL_6_REG 0xFC + +#endif /* SUPERIO_FINTEK_F81803_H */ + diff --git a/src/superio/fintek/f81803a/f81803a_hwm.h b/src/superio/fintek/f81803a/f81803a_hwm.h new file mode 100644 index 0000000..2fba52b --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a_hwm.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F81803_HWM_H +#define SUPERIO_FINTEK_F81803_HWM_H + +#define TP_SENSOR_TYPE 0x6b +#define TP_SENSOR1_TYPE_SHIFT 1 +#define TP_SENSOR2_TYPE_SHIFT 2 +#define TP_SENSOR_TYPE_MASK 0x01 +#define TP_DIODE_STATUS 0x6f +#define TP_MMX_OPEN 0x40 +#define TP_PECI_OPEN 0x20 +#define TP_TSI_OPEN 0x10 +#define TP_EXTERNAL_SENSOR2_OPEN 0x04 +#define TP_EXTERNAL_SENSOR1_OPEN 0x02 + +#define FAN_TYPE_REG 0x94 +#define FAN1_TYPE_SHIFT 0 +#define FAN2_TYPE_SHIFT 2 +#define FAN_TYPE_MASK 0x03 +#define FAN_MODE_REG 0x96 +#define FAN1_MODE_SHIFT 0 +#define FAN2_MODE_SHIFT 4 +#define FAN_MODE_MASK 0x07 +#define FAN1_FREQ_SEL_ADD_SHIFT 3 /* FUNC_PROG_SEL = 1 */ +#define FAN2_FREQ_SEL_ADD_SHIFT 4 /* FUNC_PROG_SEL = 1 */ +#define FAN_UP_RATE_REG 0x9a +#define FAN1_UP_RATE_SHIFT 0 +#define FAN2_UP_RATE_SHIFT 2 +#define FAN_UP_RATE_MASK 0x03 +#define FAN_DOWN_RATE_REG 0x9b +#define FAN1_DOWN_RATE_SHIFT 0 +#define FAN2_DOWN_RATE_SHIFT 2 +#define FAN_DOWN_RATE_MASK 0x03 +#define FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT 7 /* FUNC_PROG_SEL = 1 */ +#define FAN_DIRECT_LOAD_EN_SHIFT 6 /* FUNC_PROG_SEL = 1 */ +#define FAN_FAULT_TIME_REG 0x9f +#define FAN_FUNC_PROG_SEL_SHIFT 7 + +#define FAN1_BOUND_TEMP1 0xa6 +#define FAN1_BOUND_TEMP2 0xa7 +#define FAN1_BOUND_TEMP3 0xa8 +#define FAN1_BOUND_TEMP4 0xa9 +#define FAN1_SECTION_SPEED1 0xaa +#define FAN1_SECTION_SPEED2 0xab +#define FAN1_SECTION_SPEED3 0xac +#define FAN1_SECTION_SPEED4 0xad +#define FAN1_SECTION_SPEED5 0xae +#define FAN2_BOUND_TEMP1 0xb6 +#define FAN2_BOUND_TEMP2 0xb7 +#define FAN2_BOUND_TEMP3 0xb8 +#define FAN2_BOUND_TEMP4 0xb9 +#define FAN2_SECTION_SPEED1 0xba +#define FAN2_SECTION_SPEED2 0xbb +#define FAN2_SECTION_SPEED3 0xbc +#define FAN2_SECTION_SPEED4 0xbd +#define FAN2_SECTION_SPEED5 0xbe +#define FAN_DETAIL_SKIP (FAN2_BOUND_TEMP1 - FAN1_BOUND_TEMP1) + +#define FAN1_TMP_MAPPING 0xaf +#define FAN2_TMP_MAPPING 0xbf +#define FAN_TEMP_SEL_HIGH_SHIFT 7 +#define FAN_PWM_FREQ_SEL_SHIFT 6 +#define FAN_INTERPOLATION_SHIFT 4 +#define FAN_JUMP_UP_SHIFT 3 +#define FAN_JUMP_DOWN_SHIFT 2 +#define FAN_TEMP_SEL_LOW_SHIFT 0 +#define FAN_TEMP_SEL_LOW_MASK 0x03 +#define FAN_BIT_MASK 0x01 + +#define STATUS_INVALID_VALUE -1 +#define STATUS_INVALID_ORDER -2 + +#define FIRST_FAN 1 +#define LAST_FAN 2 +#define MAX_DUTY 100 + +#endif /* SUPERIO_FINTEK_F81803_HWM_H */ diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c new file mode 100644 index 0000000..47c8086 --- /dev/null +++ b/src/superio/fintek/f81803a/fan_control.c @@ -0,0 +1,263 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/fan_control.h" +#include "f81803a_hwm.h" + +static void write_hwm_reg(u16 address, u8 index, u8 value) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + outb(value, data_add); +} + +static u8 read_hwm_reg(u16 address, u8 index) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + return inb(data_add); +} + +static void read_and_or_write(u16 address, u8 index, u8 shift, u8 mask, + u8 value) +{ + u8 use_mask, use_value; + u8 temp = read_hwm_reg(address, index); + + use_mask = mask << shift; + use_value = (value & mask) << shift; + temp &= ~use_mask; + temp |= use_value; + write_hwm_reg(address, index, temp); +} + +static inline void set_prog_sel(u16 address, u8 value) +{ + read_and_or_write(address, FAN_FAULT_TIME_REG, FAN_FUNC_PROG_SEL_SHIFT, + FAN_BIT_MASK, value); +} + +static int check_value_seq(u8 *values, u8 count) +{ + u8 last_value = 128; /* max value is 127 */ + u8 current_value, i; + for (i = 0; i < count; i++) { + current_value = values[i]; + if (current_value > 127) + return STATUS_INVALID_VALUE; + if (current_value >= last_value) + return STATUS_INVALID_ORDER; + last_value = current_value; + } + return HWM_STATUS_SUCCESS; +} + +int set_sensor_type(u16 base_address, u8 sensor, u8 type) +{ + u8 sensor_status = read_hwm_reg(base_address, TP_DIODE_STATUS); + if (sensor == TEMP_SENSOR_DEFAULT) + return HWM_STATUS_SUCCESS; + switch (sensor) { + case EXTERNAL_SENSOR1: + if (sensor_status & TP_EXTERNAL_SENSOR1_OPEN) + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + read_and_or_write(base_address, TP_SENSOR_TYPE, + TP_SENSOR1_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + case EXTERNAL_SENSOR2: + if (sensor_status & TP_EXTERNAL_SENSOR2_OPEN) + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + read_and_or_write(base_address, TP_SENSOR_TYPE, + TP_SENSOR2_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + default: + return HWM_STATUS_INVALID_TEMP_SENSOR; + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_temperature_source(u16 base_address, u8 fan, u8 source) +{ + u8 index, high_value, low_value; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + high_value = (source >> 2) & FAN_BIT_MASK; + low_value = source & FAN_TEMP_SEL_LOW_MASK; + read_and_or_write(base_address, index, FAN_TEMP_SEL_HIGH_SHIFT, + FAN_BIT_MASK, high_value); + read_and_or_write(base_address, index, FAN_TEMP_SEL_LOW_SHIFT, + FAN_TEMP_SEL_LOW_MASK, low_value); + return HWM_STATUS_SUCCESS; +} + +int set_fan_type_mode(u16 base_address, u8 fan, u8 type, u8 mode) +{ + u8 shift; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + set_prog_sel(base_address, 0); + if (type < FAN_TYPE_SET_BY_STRAP) { + shift = FAN1_TYPE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_TYPE_SHIFT; + read_and_or_write(base_address, FAN_TYPE_REG, shift, + FAN_TYPE_MASK, type); + } + if (mode < FAN_MODE_DEFAULT) { + shift = FAN1_MODE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_MODE_SHIFT; + read_and_or_write(base_address, FAN_MODE_REG, shift, + FAN_MODE_MASK, mode); + } + return HWM_STATUS_SUCCESS; +} + +int set_pwm_frequency(u16 base_address, u8 fan, u8 frequency) +{ + u8 shift, index, byte; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + byte = read_hwm_reg(base_address, FAN_TYPE_REG); + shift = FAN1_TYPE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_TYPE_SHIFT; + if (((byte >> shift) & FAN_TYPE_PWM_CHECK) == FAN_TYPE_PWM_CHECK) + return HWM_STATUS_WARNING_FAN_NOT_PWM; + set_prog_sel(base_address, 1); + shift = FAN1_FREQ_SEL_ADD_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_FREQ_SEL_ADD_SHIFT; + byte = (frequency >> 1) & FAN_BIT_MASK; + read_and_or_write(base_address, FAN_MODE_REG, shift, FAN_BIT_MASK, + byte); + set_prog_sel(base_address, 0); + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + byte = frequency & FAN_BIT_MASK; + read_and_or_write(base_address, index, FAN_PWM_FREQ_SEL_SHIFT, + FAN_BIT_MASK, byte); + return HWM_STATUS_SUCCESS; +} + +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections) +{ + int status, temp; + u8 i, index, value; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + status = check_value_seq(boundaries, + fintek_boundaries_size); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return HWM_STATUS_INVALID_BOUNDARY_VALUE; + return HWM_STATUS_BOUNDARY_WRONG_ORDER; + } + status = check_value_seq(sections, + fintek_sections_size); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return HWM_STATUS_INVALID_SECTION_VALUE; + return HWM_STATUS_SECTIONS_WRONG_ORDER; + } + index = FAN1_BOUND_TEMP1; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + for (i = 0; i < fintek_boundaries_size; i++) { + value = boundaries[i]; + write_hwm_reg(base_address, index, value); + index++; + } + index = FAN1_SECTION_SPEED1; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + for (i = 0; i < fintek_sections_size; i++) { + value = sections[i]; + if (value > 100) + return HWM_STATUS_INVALID_SECTION_VALUE; + temp = (255 * value) / 100; + value = (u8) (temp & 0x00ff); + write_hwm_reg(base_address, index, value); + index++; + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_speed_change_rate(u16 base_address, u8 fan, u8 rate_up, + u8 rate_down) +{ + u8 shift, index; + + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return HWM_STATUS_INVALID_FAN; + + index = FAN1_TMP_MAPPING; + if (fan == LAST_FAN) + index += FAN_DETAIL_SKIP; + shift = FAN1_UP_RATE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_UP_RATE_SHIFT; + + if (rate_up == FAN_UP_RATE_JUMP) { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 1); + } else { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + if (rate_up < FAN_UP_RATE_DEFAULT) { + read_and_or_write(base_address, FAN_UP_RATE_REG, + shift, FAN_UP_RATE_MASK, rate_up); + } + } + + shift = FAN1_DOWN_RATE_SHIFT; + if (fan == LAST_FAN) + shift = FAN2_DOWN_RATE_SHIFT; + if (rate_down == FAN_DOWN_RATE_JUMP) { + read_and_or_write(base_address, index, FAN_JUMP_DOWN_SHIFT, + FAN_BIT_MASK, 1); + } else { + read_and_or_write(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + set_prog_sel(base_address, 1); + if (rate_down < FAN_DOWN_RATE_DEFAULT) { + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + shift, FAN_DOWN_RATE_MASK, rate_down); + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 0); + } + if (rate_down == FAN_DOWN_RATE_SAME_AS_UP) { + read_and_or_write(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 1); + } + set_prog_sel(base_address, 0); + } + return HWM_STATUS_SUCCESS; +} diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c new file mode 100644 index 0000000..bc4cbba --- /dev/null +++ b/src/superio/fintek/f81803a/superio.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81803a.h" + +static void f81803a_pme_init(struct device *dev) +{ + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + /* enable ERP function*/ + /* also set PSIN to generate PSOUT*/ + pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN); + pnp_exit_conf_mode(dev); +} + +static void f81803a_init(struct device *dev) +{ + if (!dev->enabled) + return; + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F81803A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case F81803A_PME: + f81803a_pme_init(dev); + break; + } + +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81803a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81803A_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, + { &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + //{ &ops, F81803A_WDT, PNP_IO0, 0x7f8 }, + { &ops, F81803A_PME, }, +}; + +static void enable_dev(struct device *dev) +{ + printk(BIOS_INFO, "F81803A : %s\n", __func__); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81803a_ops = { + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a79f681be795dbd07fd0f0f179b06915e07ab Gerrit-Change-Number: 31374 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: vendorcode/amd/pi: Add merlinfalcon vendor code
by Richard Spiegel (Code Review) 18 Jun '19

18 Jun '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31373 Change subject: vendorcode/amd/pi: Add merlinfalcon vendor code ...................................................................... vendorcode/amd/pi: Add merlinfalcon vendor code Merlinfalcon is essentially stoneyridge (00670F00), but using a carizo CPU. Therefore, it needs carizo AGESA (00660F01), but a stoneyridge vendor code with a small modification to gcccar.inc due to carizo AGESA requiring CAR at 0x3000 to 0x4000. Please notice: Most of the new files are duplicate from src/vendorcode/amd/pi/00670F00, the only difference is gcccar.inc which has 1 extra instruction. I would rather have some conditional build on a config parameter, but I was not aware how to do it for an assembly file. I'm open to suggestions. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: I01b4cdef01ba185fd0d96e6674f8b1c56307d1f2 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/vendorcode/amd/pi/00670F00_CZ/AGESA.h A src/vendorcode/amd/pi/00670F00_CZ/AMD.h A src/vendorcode/amd/pi/00670F00_CZ/Include/Filecode.h A src/vendorcode/amd/pi/00670F00_CZ/Include/PlatformMemoryConfiguration.h A src/vendorcode/amd/pi/00670F00_CZ/Include/Topology.h A src/vendorcode/amd/pi/00670F00_CZ/Makefile.inc A src/vendorcode/amd/pi/00670F00_CZ/Porting.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/Family/cpuFamRegisters.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/Table.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/cpuFamilyTranslation.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/cpuRegisters.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/cpuServices.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/CPU/heapManager.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/Common/AmdFch.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/Fch/Common/FchCommonCfg.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/Fch/Fch.h A src/vendorcode/amd/pi/00670F00_CZ/Proc/Fch/FchPlatform.h A src/vendorcode/amd/pi/00670F00_CZ/agesa_headers.h A src/vendorcode/amd/pi/00670F00_CZ/binaryPI/AGESA.c A src/vendorcode/amd/pi/00670F00_CZ/binaryPI/OptionsIds.h A src/vendorcode/amd/pi/00670F00_CZ/binaryPI/gcccar.inc A src/vendorcode/amd/pi/00670F00_CZ/check_for_wrapper.h A src/vendorcode/amd/pi/00670F00_CZ/gcc-intrin.h M src/vendorcode/amd/pi/Kconfig 24 files changed, 15,360 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31373/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01b4cdef01ba185fd0d96e6674f8b1c56307d1f2 Gerrit-Change-Number: 31373 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

1 5

Change in ...coreboot[master]: soc/amd: Add support to soc merlinfalcon
by Richard Spiegel (Code Review) 18 Jun '19

18 Jun '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31372 Change subject: soc/amd: Add support to soc merlinfalcon ...................................................................... soc/amd: Add support to soc merlinfalcon Merlinfalcon is essentially stoneyridge (00670F00), but using a carizo CPU. Therefore add CPU_CARIZO config parameter and minor changes when this config is selected. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: I67cf11432901857354a8f7192b330dacad383a9e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 8 files changed, 66 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31372/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 80798d9..2d1ac1e 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,6 +23,15 @@ help AMD Stoney Ridge FT4 support +config STONEYRIDGE_CPU_CARIZO + bool + default n + help + For SOC MerlinFalcon, select SOC_AMD_STONEYRIDGE_FP4 and + STONEYRIDGE_CPU_CARIZO as the only difference between StoneyRidge + and MerlinFalcon is the internal CPU, and therefore the video + (3rdparty/blobs/soc/amd/merlinfalcon). + if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 config CPU_SPECIFIC_OPTIONS @@ -128,6 +137,7 @@ config VGA_BIOS_ID string + default "1002,9874" if STONEYRIDGE_CPU_CARIZO default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 414326e..94638b0 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -34,7 +34,15 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { \_PR.P000, diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 92223d1..432ed04 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -24,8 +24,13 @@ #include <arch/acpi_device.h> #define MAX_NODES 1 +#if IS_ENABLED(CONFIG_STONEYRIDGE_CPU_CARIZO) +#define MAX_DRAM_CH 2 +#define MAX_DIMMS_PER_CH 4 +#else #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#endif #define STONEY_I2C_DEV_MAX 4 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..3c47ec8 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -145,7 +145,11 @@ }; static struct cpu_device_id cpu_table[] = { +#if IS_ENABLED(CONFIG_STONEYRIDGE_CPU_CARIZO) + { X86_VENDOR_AMD, 0x660f01 }, +#else { X86_VENDOR_AMD, 0x670f00 }, +#endif { 0, 0 }, }; diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 20ab99b..60125b1 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -43,14 +43,16 @@ /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVID_CZ 0x9874 /* subject to SKU/OPN variation */ +#define GFX_DEVID_ST 0x98e4 /* subject to SKU/OPN variation */ #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) /* HD Audio 0 */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 +#define HDA0_DEVID_CZ 0x9840 +#define HDA0_DEVID_ST 0x15b3 #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) @@ -113,42 +115,48 @@ /* HT Configuration */ #define HT_DEV 0x18 #define HT_FUNC 0 -#define HT_DEVID 0x15b0 +#define HT_DEVID_CZ 0x1570 +#define HT_DEVID_ST 0x15b0 #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) #define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) /* Address Maps */ #define ADDR_DEV 0x18 #define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 +#define ADDR_DEVID_CZ 0x1571 +#define ADDR_DEVID_ST 0x15b1 #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) #define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) /* DRAM Configuration */ #define DCT_DEV 0x18 #define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 +#define DCT_DEVID_CZ 0x1572 +#define DCT_DEVID_ST 0x15b2 #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) #define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) /* Misc. Configuration */ #define MISC_DEV 0x18 #define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 +#define MISC_DEVID_CZ 0x1573 +#define MISC_DEVID_ST 0x15b3 #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) #define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) /* PM Configuration */ #define PM_DEV 0x18 #define PM_FUNC 4 -#define PM_DEVID 0x15b4 +#define PM_DEVID_CZ 0x1574 +#define PM_DEVID_ST 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) /* Northbridge Configuration */ #define NB_DEV 0x18 #define NB_FUNC 5 -#define NB_DEVID 0x15b5 +#define NB_DEVID_CZ 0x1575 +#define NB_DEVID_ST 0x15b5 #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3ae6b4a..705fe7a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -186,6 +186,7 @@ #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ +#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ /* XHCI_PM Registers: 0xfed81c00 */ #define XHCI_PM_INDIRECT_INDEX 0x48 @@ -477,7 +478,7 @@ void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_i2c(void); -void sb_clk_output_48Mhz(void); +void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..0e7b4b8 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -338,7 +338,11 @@ static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, +#if IS_ENABLED(CONFIG_STONEYRIDGE_CPU_CARIZO) + .device = PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, +#else .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, +#endif }; /* @@ -453,8 +457,13 @@ { u32 new_vendev; new_vendev = +#if IS_ENABLED(CONFIG_STONEYRIDGE_CPU_CARIZO) + ((vendev >= 0x10029870) && (vendev <= 0x1002987f)) ? + 0x10029870 : vendev; +#else ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? 0x100298e0 : vendev; +#endif if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c8d66ac..798bcb4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -389,7 +389,7 @@ pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); } -void sb_clk_output_48Mhz(void) +void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE @@ -401,8 +401,16 @@ */ ctrl = read32(misc_clk_cntl_1_ptr); - /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } write32(misc_clk_cntl_1_ptr, ctrl); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cf11432901857354a8f7192b330dacad383a9e Gerrit-Change-Number: 31372 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: Grunt platforms: Change bayhub BH720 eMMC speed to 200 MHz
by Richard Spiegel (Code Review) 18 Jun '19

18 Jun '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31772 Change subject: Grunt platforms: Change bayhub BH720 eMMC speed to 200 MHz ...................................................................... Grunt platforms: Change bayhub BH720 eMMC speed to 200 MHz Currently bayhub BH7720 eMMC is set to internal clock of 50MHz. This is because some eMMC device don't work at 200 MHz without clock tuning. This was never intended as permanent code, as it also slowed eMMC after OS loaded because internal clock remained at 50MHz. In order to solve this issue, code must be added to execute clock tuning, and BH720_PCR_CSR_EMMC_MODE_SEL bit must be set, not cleared (to revert clock back to 200 MHz). BUG=b:122244718 TEST=Built grunt without code, boot/reboot, measured eMMC time, saved results. Added code, rebuilt grunt, boot/reboot, measured eMMC time. Time saved: 123.5 milliseconds. Change-Id: I8aefb524a76ab469e776f2f22aed80b29b67ae8e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/pci_sdhci.c M src/commonlib/storage/sdhci.h M src/drivers/generic/bayhub/bh720.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 5 files changed, 80 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31772/1 diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 6ddfb70..96554e6 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -19,6 +19,7 @@ #include "bouncebuf.h" #include <halt.h> #include "storage.h" +#include "sd_mmc.h" #include <string.h> #include <commonlib/stdlib.h> diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 2bba084..329e069 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -22,9 +22,12 @@ #include <commonlib/sdhci.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> #include "sd_mmc.h" #include <stdint.h> #include "storage.h" +#include "sdhci.h" +#include <delay.h> /* Initialize an SDHCI port */ int sdhci_controller_init(struct sdhci_ctrlr *sdhci_ctrlr, void *ioaddr) @@ -54,9 +57,59 @@ return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr); } +static void bh720_tuning_start(struct sd_mmc_ctrlr *ctrlr, int retune) +{ + /* switch to 4bit, for bh720 didn't support 8bit tuning */ + u16 host_ctrl2, vendor_spec; + struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr; + + host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2); + host_ctrl2 &= ~(SDHCI_CTRL_8BITBUS); + host_ctrl2 |= (SDHCI_CTRL_4BITBUS); + sdhci_writew(sdhci_ctrlr, SDHCI_HOST_CONTROL2, host_ctrl2); + + /* set tuning mode to hw tuning */ + vendor_spec = sdhci_readw(sdhci_ctrlr, SDHCI_VENDOR_SPEC_CTRL); + vendor_spec &= ~SDHCI_VENDOR_HW_TUNING; + sdhci_writew(sdhci_ctrlr, vendor_spec, SDHCI_VENDOR_SPEC_CTRL); + + /* Start the bus tuning */ + host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2); + host_ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + host_ctrl2 |= (retune ? SDHCI_CTRL_TUNED_CLK : 0) + | SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(sdhci_ctrlr, host_ctrl2, SDHCI_HOST_CONTROL2); +} + +static int bh720_is_tuning_complete(struct sd_mmc_ctrlr *ctrlr, int *successful) +{ + /* if tuning complete, switch to 8bit */ + int index; + u16 regval; + struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr; + + for (index = 0; index < 1000; index++) { + regval = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2); + if ((regval & SDHCI_CTRL_EXEC_TUNING) == 0) { + regval = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2); + *successful = ((regval & SDHCI_CTRL_TUNED_CLK) != 0); + + /*switch back to 8bit after tuning complete*/ + regval |= (SDHCI_CTRL_8BITBUS); + regval &= ~(SDHCI_CTRL_4BITBUS); + sdhci_writew(sdhci_ctrlr, SDHCI_HOST_CONTROL2, regval); + return 1; + } + else + udelay(100); + } while (1); +} + struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev) { uint32_t addr; + uint32_t vendor_id, device_id; + struct sd_mmc_ctrlr *sd_mmc_ctrlr; addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (addr == ((uint32_t)~0)) { @@ -65,5 +118,15 @@ } addr &= ~0xf; - return new_mem_sdhci_controller((void *)addr); + sd_mmc_ctrlr = new_mem_sdhci_controller((void *)addr); + + vendor_id = pci_read_config32(dev, PCI_VENDOR_ID); + device_id = pci_read_config32(dev, PCI_DEVICE_ID); + if (vendor_id == PCI_VENDOR_ID_O2 && + device_id == PCI_DEVICE_ID_O2_BH720) { + sd_mmc_ctrlr->tuning_start = bh720_tuning_start; + sd_mmc_ctrlr->is_tuning_complete = bh720_is_tuning_complete; + } + + return sd_mmc_ctrlr; } diff --git a/src/commonlib/storage/sdhci.h b/src/commonlib/storage/sdhci.h index ed8984a..ea0c501 100644 --- a/src/commonlib/storage/sdhci.h +++ b/src/commonlib/storage/sdhci.h @@ -217,6 +217,9 @@ #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_VENDOR_SPEC_CTRL 0x110 +#define SDHCI_VENDOR_HW_TUNING 0x10 + /* * End of controller registers. */ diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index 3183bf1..03da99e 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -41,6 +41,8 @@ BH720_PCR_DrvStrength_PLL = 0x304, BH720_PCR_DATA_CMD_DRV_MAX = 7, BH720_PCR_CLK_DRV_MAX = 7, + BH720_PCR_PLL_MASK = 0xFFFF0000, + BH720_PCR_PLL_200M = 0x25100000, BH720_PCR_EMMC_SETTING = 0x308, BH720_PCR_EMMC_SETTING_1_8V = BIT(4), diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 518d457..ba3bf96 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -61,12 +61,20 @@ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */ + /* Set Bayhub SD base CLK 200MHz */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + (bh720_pcr_data & ~BH720_PCR_PLL_MASK) | BH720_PCR_PLL_200M); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_CSR); bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_CSR); -- To view, visit https://review.coreboot.org/c/coreboot/+/31772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aefb524a76ab469e776f2f22aed80b29b67ae8e Gerrit-Change-Number: 31772 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: postcarpayload: Boot to payload from postcar stage directly [WIP]
by Subrata Banik (Code Review) 12 Jun '19

12 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30985 Change subject: postcarpayload: Boot to payload from postcar stage directly [WIP] ...................................................................... postcarpayload: Boot to payload from postcar stage directly [WIP] Changes: 1. Make only required changes to load generic payload [payload_init.c] 2. Compile required functions in postcar stage 3. Call postcar_payload_init() from postcar stage 4. soc and mainboard related changes TEST=Able to boot iclrvp and dragonegg to chrome os with limited FW changes. Change-Id: I27479187461ceb078167f2d726f40839865a9233 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/acpi.c M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/commonlib/Makefile.inc M src/console/post.c M src/cpu/intel/microcode/Makefile.inc M src/cpu/intel/turbo/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/name/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/device/Makefile.inc M src/device/pci_early.c M src/drivers/elog/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/gma/Makefile.inc M src/drivers/mrc_cache/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/drivers/pc80/pc/Makefile.inc M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/ec/google/chromeec/Makefile.inc M src/include/memlayout.h M src/include/mrc_cache.h M src/include/rules.h M src/include/stddef.h M src/lib/Makefile.inc M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/mainboard/google/dragonegg/Kconfig M src/mainboard/google/dragonegg/Makefile.inc M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/Kconfig M src/security/vboot/Makefile.inc M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/graphics/Makefile.inc M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/itss/Makefile.inc M src/soc/intel/common/block/lpc/Makefile.inc M src/soc/intel/common/block/pcr/Makefile.inc M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c A src/soc/intel/icelake/include/soc/payload_init.h A src/soc/intel/icelake/payload_init.c M src/southbridge/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Makefile.inc 67 files changed, 477 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30985/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8dafac8..2ee4921 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -260,6 +260,11 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += gdt_init.S @@ -270,6 +275,7 @@ postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += c_start.S postcar-y += memcpy.c postcar-y += memmove.c postcar-y += memset.c @@ -310,11 +316,13 @@ ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c +postcar-$(CONFIG_IOAPIC) += ioapic.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c ramstage-y += memlayout.ld @@ -327,10 +335,13 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c +postcar-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3b33f1b..e8c7cb4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -48,6 +48,9 @@ #include <cpu/cpu.h> #include <cbfs.h> +#include <soc/pci_devs.h> +#include <intelblocks/graphics.h> + u8 acpi_checksum(u8 *table, u32 length) { u8 ret = 0; @@ -1264,6 +1267,7 @@ printk(BIOS_DEBUG, "current = %lx\n", current); +#if 0 // TODO: Bad hack to enable GFX for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { current = dev->ops->write_acpi_tables(dev, current, @@ -1271,6 +1275,9 @@ current = acpi_align_current(current); } } +#endif + graphics_soc_write_acpi_opregion(SA_DEV_IGD, current, rsdp); + current = acpi_align_current(current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ec..5bb3cfd 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -37,8 +37,8 @@ #else .code32 #endif - .globl _start -_start: + .globl _start1 +_start1: cli lgdt %cs:gdtaddr #ifndef __x86_64__ diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 018ce9e..d9d0762 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -227,15 +227,11 @@ * from secondary cpus to a minimum, when debugging is * disabled. */ - struct device *cpu; - struct cpu_info *info; + struct device *cpu = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct cpuinfo_x86 c; - info = cpu_info(); - printk(BIOS_INFO, "Initializing CPU #%d\n", index); - cpu = info->cpu; if (!cpu) die("CPU: missing CPU device structure"); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a061a27..7ddda19 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -837,7 +837,7 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if (ENV_RAMSTAGE || ENV_POSTCAR) && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea..b10b984 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,7 +210,7 @@ ); return ci; } - +#if !ENV_POSTCAR static inline unsigned long cpu_index(void) { struct cpu_info *ci; @@ -218,6 +218,7 @@ return ci->index; } #endif +#endif #ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..da02d6b 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <soc/payload_init.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -37,6 +38,8 @@ display_mtrrs(); + postcar_payload_init(); + /* Load and run ramstage. */ run_ramstage(); } diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 4d89c48..3d68cb4 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -23,6 +23,8 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c + bootblock-y += cbfs.c verstage-y += cbfs.c romstage-y += cbfs.c diff --git a/src/console/post.c b/src/console/post.c index 4c37535..50c84df 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -41,7 +41,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void cmos_post_log(void) { u8 code = 0; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..cdef0e0 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc index 48ec55d..6a62f59 100644 --- a/src/cpu/intel/turbo/Makefile.inc +++ b/src/cpu/intel/turbo/Makefile.inc @@ -1 +1,2 @@ +postcar-y += turbo.c ramstage-y += turbo.c diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..639d1f8 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,9 +6,11 @@ subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name +postcar-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c +postcar-y += backup_default_smm.c additional-dirs += $(obj)/cpu/x86 @@ -19,6 +21,7 @@ ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN).manual +postcar-srcs += $(SIPI_BIN).manual endif rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S @@ -37,3 +40,22 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + + +rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^ + +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +endif + +$(SIPI_BIN): $(SIPI_RMOD) + $(OBJCOPY_postcar) -O binary $< $@ + +$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..3381d04 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += lapic.c +postcar-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..0042f49 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -194,6 +194,19 @@ } } +#if ENV_POSTCAR +static inline unsigned long cpu_index(void) +{ + int i; + + for (i=0; i < CONFIG_MAX_CPUS; i++) { + if (mp_get_apic_id(i) == lapicid()) + return i; + } + return 0; +} +#endif + static void park_this_cpu(void *unused) { stop_this_cpu(); @@ -203,12 +216,11 @@ * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) { - struct cpu_info *info; + static struct cpu_info *info; /* Ensure the local APIC is enabled */ enable_lapic(); - info = cpu_info(); info->index = cpu; info->cpu = cpus[cpu].dev; @@ -399,7 +411,7 @@ /* Assuming linear APIC space allocation. AP will set its own APIC id in the ap_init() path above. */ - cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i; + cpu_path.apic.apic_id = lapicid() + i; /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); @@ -565,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; + static struct cpu_info *info; /* Print processor name */ fill_processor_name(processor_name); @@ -579,9 +591,9 @@ cpu_path.apic.apic_id = lapicid(); /* Find the device structure for the boot CPU. */ - info = cpu_info(); info->cpu = alloc_find_dev(cpu_bus, &cpu_path); info->cpu->name = processor_name; + info->index = cpu_index(); if (info->index != 0) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); @@ -661,8 +673,7 @@ static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ - struct cpu_info *info = cpu_info(); - cpu_initialize(info->index); + cpu_initialize(cpu_index()); } /* Returns APIC id for coreboot CPU number or < 0 on failure. */ diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..15ee4e1 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mtrr.c +postcar-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2..6c62814 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += name.c +postcar-y += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..83b7ff8 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -14,6 +14,7 @@ ## ramstage-y += smm_module_loader.c +postcar-y += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) @@ -23,6 +24,14 @@ $(eval $(call create_class_compiler,smmstub,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call create_class_compiler,smm,x86_32)) +$(eval $(call create_class_compiler,smmstub,x86_32)) +else +$(eval $(call create_class_compiler,smm,x86_64)) +$(eval $(call create_class_compiler,smmstub,x86_64)) +endif + smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) @@ -36,6 +45,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -45,6 +58,9 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual + # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) @@ -57,6 +73,13 @@ $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) +endif + + $(obj)/smmstub/smmstub: $(obj)/smmstub/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ @@ -64,6 +87,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,6 +99,12 @@ $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +endif + $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ @@ -84,6 +117,7 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual endif smm-y += smmhandler.S diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..3a2636c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -1,9 +1,14 @@ ramstage-y += device.c +postcar-y += device.c ramstage-y += root_device.c +postcar-y += root_device.c ramstage-y += cpu_device.c +postcar-y += cpu_device.c ramstage-y += device_util.c +postcar-y += device_util.c ramstage-$(CONFIG_PCI) += pci_class.c ramstage-$(CONFIG_PCI) += pci_device.c +postcar-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c @@ -12,9 +17,13 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +postcar-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c +postcar-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..568b517 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <delay.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..191a89a 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..efe6208 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -28,6 +28,7 @@ ramstage-y += debug.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c +postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c @@ -39,6 +40,10 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +postcar-y += silicon_init.c +postcar-y += util.c +postcar-y += debug.c + postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0670663..834dbb0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -54,13 +54,14 @@ post_code(POST_FSP_SILICON_EXIT); fsp_debug_after_silicon_init(status); - +#if 0 // TODO: bad hack /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die("FspSiliconINit returned an error!\n"); } +#endif } void fsps_load(bool s3wake) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..c9dbb13 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,7 +20,7 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c - +postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 0d226fe..f3a6dd9 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 4dd0dbc..549470a 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -542,7 +542,7 @@ printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..70cc516 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) +postcar-y += isa-dma.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9b5f57c..62f315f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 94a7fc9..2db824a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..949525f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,7 +6,9 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c bootblock-y += ec.c +postcar-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -31,6 +33,7 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..7d65fbd 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -40,7 +40,7 @@ /* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE || ENV_POSTCAR) #endif #define STR(x) #x diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf..6ecb132 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -41,4 +41,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size); +void update_mrc_cache(void *unused); + #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/rules.h b/src/include/rules.h index deea50b..424fa39 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -270,7 +270,7 @@ * For now only x86 is supported. */ -#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index a82a68d..865ab12 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -23,10 +23,10 @@ /* The devicetree data structures are only mutable in ramstage. All other stages have a constant devicetree. */ -#if !ENV_RAMSTAGE -#define DEVTREE_EARLY 1 -#else +#if ENV_RAMSTAGE || ENV_POSTCAR #define DEVTREE_EARLY 0 +#else +#define DEVTREE_EARLY 1 #endif #if DEVTREE_EARLY diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..4be2fc9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c +postcar-y += region_file.c romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c @@ -113,20 +114,27 @@ ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +postcar-y += selfboot.c ramstage-y += coreboot_table.c +postcar-y += coreboot_table.c ramstage-y += bootmem.c +postcar-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c +postcar-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c +postcar-y += fallback_boot.c ramstage-y += compute_ip_checksum.c +postcar-y += compute_ip_checksum.c ramstage-y += cbfs.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +postcar-y += stack.c ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -139,6 +147,7 @@ ramstage-y += edid_fill_fb.c endif ramstage-y += memrange.c +postcar-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 29682eb..3b1b4c3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,7 +16,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ff1cb95..ae1b416 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -303,8 +303,8 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if ENV_RAMSTAGE || ENV_POSTCAR || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ + && (ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..a32f284 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,7 @@ range_entry_unlink(&ranges->free_list, r); return r; } - if (ENV_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ac80a62..a9a6681 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -160,7 +160,7 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if ENV_RAMSTAGE || ENV_POSTCAR // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -213,10 +213,12 @@ timestamp_add_now(TS_SELFBOOT_JUMP); +#if ENV_RAMSTAGE /* Before we go off to run the payload, see if * we stayed within our bounds. */ checkstack(_estack, 0); +#endif prog_run(payload); } diff --git a/src/lib/program.ld b/src/lib/program.ld index 156b862..5694e72 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f4..2b51841 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -28,15 +28,15 @@ default 512 # Select this option to enable use of cr50 SPI TPM on dragon egg. -config DRAGONEGG_USE_SPI_TPM - bool - default y - select MAINBOARD_HAS_SPI_TPM_CR50 - select MAINBOARD_HAS_TPM2 +#config DRAGONEGG_USE_SPI_TPM +# bool +# default y +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 -config DRIVER_TPM_SPI_BUS - depends on DRAGONEGG_USE_SPI_TPM - default 0x1 +#config DRIVER_TPM_SPI_BUS +# depends on DRAGONEGG_USE_SPI_TPM +# default 0x1 config GBB_HWID string @@ -78,6 +78,7 @@ config VBOOT select VBOOT_LID_SWITCH select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0..0388de3 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -21,10 +21,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c +postcar-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +postcar-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320c..ac26a7d 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -21,7 +21,7 @@ #include <variant/gpio.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 22736b9..f86ac87 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -18,3 +18,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +postcar-y += gpio.c diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..722956e 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -12,14 +12,14 @@ device lapic 0 on end end - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 @@ -278,7 +278,7 @@ device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_06" @@ -311,7 +311,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 7cc4e53..0e1b69d 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -15,7 +15,7 @@ select SOC_INTEL_ICELAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE - + select EC_ACPI config MAINBOARD_DIR string default "intel/icelake_rvp" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ae80a02..570e47f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -29,16 +29,19 @@ bootblock-y += vbnv.c verstage-y += vbnv.c romstage-y += vbnv.c +postcar-y += vbnv.c ramstage-y += vbnv.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..f55e41a 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -18,7 +18,9 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c +postcar-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5..d792111 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0ea6cb9..247e9e4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -446,7 +446,7 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ -static void acpi_save_wake_source(void *unused) +void acpi_save_wake_source(void *unused) { global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); uint32_t pm1, *gpe0; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227..57f1386 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -7,6 +7,8 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index b0ffee3..8db62fd 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index 44dfc7e..f58b3e7 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f72adfc..a6df4ee 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..cfbdf15 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -91,4 +91,6 @@ */ void soc_power_states_generation(int core_id, int cores_per_package); +void acpi_save_wake_source(void *unused); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index babf9ce..329051f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -64,6 +64,8 @@ */ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); + +void systemagent_read_resources(struct device *dev); /* * API to set BIOS Reset CPL through MCHBAR * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h diff --git a/src/soc/intel/common/block/itss/Makefile.inc b/src/soc/intel/common/block/itss/Makefile.inc index bc0e97a..ba3bcb9 100644 --- a/src/soc/intel/common/block/itss/Makefile.inc +++ b/src/soc/intel/common/block/itss/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc index 428ade9..400dfe4 100644 --- a/src/soc/intel/common/block/lpc/Makefile.inc +++ b/src/soc/intel/common/block/lpc/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc index 0577e0a..3da14ea 100644 --- a/src/soc/intel/common/block/pcr/Makefile.inc +++ b/src/soc/intel/common/block/pcr/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636..e4d4b0b 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..cfbbbe9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -250,7 +250,7 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +void systemagent_read_resources(struct device *dev) { int index = 0; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index c1cef5d..7884961 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" #include <timer.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182..84458aa 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -33,12 +33,15 @@ romstage-y += uart.c ramstage-y += acpi.c +postcar-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c +postcar-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c @@ -50,17 +53,22 @@ ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c +postcar-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += payload_init.c + smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c - +postcar-y += fsp_params.c +postcar-y += gpio.c +postcar-y += payload_init.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a..c147692 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -220,7 +220,7 @@ gnvs->dpte = config->dptf_enable; /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); +// gnvs->cid1 = wifi_regulatory_domain(); // TODO: bad hack /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/include/soc/payload_init.h b/src/soc/intel/icelake/include/soc/payload_init.h new file mode 100644 index 0000000..4e838cd --- /dev/null +++ b/src/soc/intel/icelake/include/soc/payload_init.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PAYLOAD_INIT_H_ +#define _PAYLOAD_INIT_H_ + +#include <stdint.h> + +void postcar_payload_init(void); +#endif diff --git a/src/soc/intel/icelake/payload_init.c b/src/soc/intel/icelake/payload_init.c new file mode 100644 index 0000000..20fe90c --- /dev/null +++ b/src/soc/intel/icelake/payload_init.c @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <boot/tables.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/systemagent.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <romstage_handoff.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <program_loading.h> +#include <soc/payload_init.h> + +#include <cpu/intel/microcode.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "mrc_cache.h" +#include <soc/intel/common/acpi.h> + +#define XHCI_FIXED_BAR 0xb2310000 +#define XHCI_BAR_SIZE 0x10000 + +#define IGD_FIXED_BAR 0xb0000000 +#define IGD_BAR_SIZE 0x1000000 +#define IGD_FIXED_BAR_2 0xa0000000 +#define IGD_BAR_SIZE_2 0x10000000 + +static void pch_set_bar(struct device *dev, uintptr_t tempbar, + uintptr_t tempbar_1, uintptr_t tempbar_2) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, tempbar_1); + pci_write_config32(dev, PCI_BASE_ADDRESS_2, tempbar_2); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +static void allocate_device_resource(struct device *dev, int offset, + uint32_t base, uint32_t size) +{ + struct resource *res; + + res = new_resource(dev, offset); + res->base = base; + res->size = size; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; +} + +static void set_device_resource(struct device *dev, int offset, + uint32_t base) +{ + struct resource *res; + + res = find_resource(dev, offset); + dev->command |= 2; + res->flags = IORESOURCE_STORED; + report_resource_stored(dev, res, "Device BAR 0"); + + pci_dev_enable_resources(dev); +} + +static void enable_xhci_device(void) +{ + struct device *dev = PCH_DEV_XHCI; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR, XHCI_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR); + + pch_set_bar(dev, XHCI_FIXED_BAR, 0, 0); +} + +static void enable_igd_device(void) +{ + struct device *dev = SA_DEV_IGD; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR, IGD_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR); + + allocate_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2, IGD_BAR_SIZE_2); + set_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2); + + pch_set_bar(dev, IGD_FIXED_BAR, 0, IGD_FIXED_BAR_2); +} + +static void wrapper_x86_core_init(void *unused) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + + soc_core_init(dev); +} + +static void init_cpus(void) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + static const void *microcode_patch; + + intel_microcode_load_unlocked(microcode_patch); + + if (dev && dev->link_list) + soc_init_cpus(dev->link_list); + + if (mp_run_on_all_cpus(&wrapper_x86_core_init, NULL, 5000) < 0) + printk(BIOS_ERR, "CPU Init failure\n"); +} + +static void wrapper_x86_setup_mtrrs(void *unused) +{ + x86_setup_mtrrs_with_detect(); +} + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void post_cpus_init(void) +{ + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 5000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); + + x86_mtrr_check(); +} + +static void wake_from_s3(void) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + acpi_save_wake_source(NULL); + arch_bootstate_coreboot_exit(); + acpi_resume(wake_vector); + } +#endif +} + +static void finaize_smm(void) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(0xcb, 0xb2); +} + +void postcar_payload_init(void) +{ + struct device *dev = SA_DEV_ROOT; + int is_s3_resume = romstage_handoff_is_resume(); + + /* Initialize CPU cores */ + init_cpus(); + + /* Perform silicon specific init. */ + fsp_silicon_init(is_s3_resume); + + /* Save MRC cache into SPI*/ + update_mrc_cache(NULL); + + /* Read Resources for Root Device 0:0:0 */ + systemagent_read_resources(dev); + pci_dev_set_resources(dev); + pci_dev_enable_resources(dev); + + /* Make IGD Enable */ + enable_igd_device(); + + /* Make USB bootable */ + enable_xhci_device(); + + /* Add S3 Resume logic */ + if (is_s3_resume) { + finaize_smm(); + wake_from_s3(); + } + + acpi_prepare_resume_backup(); + + /* DSDT generation */ + southbridge_inject_dsdt(dev); + mainboard_chromeos_acpi_generate(); + + /* Post MP Init to program MTRR on APs */ + post_cpus_init(); + + /* Create coreboot tables */ + write_tables(); + + /* Load Payload */ + payload_load(); + + finaize_smm(); + + /* Run Payload */ + payload_run(); +} diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3224e1f..bc43da6 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..28abd2e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,10 +13,13 @@ ## GNU General Public License for more details. ## +postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27479187461ceb078167f2d726f40839865a9233 Gerrit-Change-Number: 30985 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: autoport: Generate a libgfxinit template
by Iru Cai (vimacs) (Code Review) 09 Jun '19

09 Jun '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30912 to review the following change. Change subject: autoport: Generate a libgfxinit template ...................................................................... autoport: Generate a libgfxinit template Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/main.go 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30912/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1a7907 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -748,6 +748,10 @@ ScanRoot(ctx) + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { mf := Create(ctx, "Makefile.inc") defer mf.Close() @@ -882,4 +886,42 @@ } `) + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; +`) } -- To view, visit https://review.coreboot.org/c/coreboot/+/30912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Gerrit-Change-Number: 30912 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size
by Kacper Słomiński (Code Review) 09 Jun '19

09 Jun '19

Kacper Słomiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30980 Change subject: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size ...................................................................... mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size Signed-off-by: Kacper Słomiński <kacper.slominski72(a)gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30980/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 363df55..c88d317 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -24,6 +24,8 @@ bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_6144 + bool config BOARD_ROMSIZE_KB_8192 bool config BOARD_ROMSIZE_KB_10240 @@ -47,6 +49,7 @@ default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 @@ -94,6 +97,11 @@ help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_6144 + bool "6144 KB (6 MB)" + help + Choose this option if you have a 6144 KB (6 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_8192 bool "8192 KB (8 MB)" help @@ -136,6 +144,7 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 @@ -153,6 +162,7 @@ default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 -- To view, visit https://review.coreboot.org/c/coreboot/+/30980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Gerrit-Change-Number: 30980 Gerrit-PatchSet: 1 Gerrit-Owner: Kacper Słomiński <kacper.slominski72(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [TESTME]soc/intel/braswell: Implement and use open source CAR
by Arthur Heymans (Code Review) 08 Jun '19

08 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30778 Change subject: [TESTME]soc/intel/braswell: Implement and use open source CAR ...................................................................... [TESTME]soc/intel/braswell: Implement and use open source CAR Copied from baytrail. Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/cache_as_ram.inc 6 files changed, 242 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30778/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 6409ad5..10e3c60 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -21,36 +21,38 @@ #include <program_loading.h> #include <timestamp.h> -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc) { + /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram + * is still enabled. We can directly access work buffer here. */ + FSP_INFO_HEADER *fih; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); + timestamp_init(tsc); /* Call into pre-console init code then initialize console. */ car_soc_pre_console_init(); car_mainboard_pre_console_init(); console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + printk(BIOS_SPEW, "bist: 0x%08lx\n", bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", tsc); - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); + if (prog_locate(&fsp)) { + fih = NULL; + printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); } car_soc_post_console_init(); car_mainboard_post_console_init(); /* Return new stack value in RAM back to assembly stub. */ - cache_as_ram_stage_main(car_params->fih); + cache_as_ram_stage_main(fih); } /* Entry point taken when romstage is called after a separate verstage. */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index df5e0da..96c9cf9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -30,7 +30,7 @@ }; /* Entry points from the cache-as-ram assembly code. */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc); asmlinkage void after_cache_as_ram(void *chipset_context); asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d0a250a..b780038 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,7 +39,8 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC +# select USE_GENERIC_FSP_CAR_INC + select SKIP_FSP_CAR select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 3296331..1a5addb 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -18,6 +18,7 @@ postcar-y += memmap.c postcar-y += iosf.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..1ab1b45 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,5 @@ romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c + +cpu_incs-y += $(src)/soc/intel/braswell/romstage/cache_as_ram.inc diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc new file mode 100644 index 0000000..9db7f85 --- /dev/null +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> + +#include "fmap_config.h" + +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) + +#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Configure the default memory type to uncacheable as well as disable + * fixed and variable range mtrrs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x22) + /* Zero the variable MTRRs. */ + movl $IA32_MCG_CAP, %ecx + rdmsr + movzx %al, %ebx + /* First variable MTRR. */ + movl $MTRR_PHYS_BASE(0), %ecx + xorl %eax, %eax + xorl %edx, %edx +1: + wrmsr + inc %ecx + dec %ebx + jnz 1b + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRR_PHYS_MASK(0), %ecx + wrmsr + movl $MTRR_PHYS_MASK(1), %ecx + wrmsr + + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRR_PHYS_BASE(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRR_PHYS_MASK(0)), %ecx + rdmsr + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + post_code(0x25) + /* Set code caching up for romstage. */ + movl $(MTRR_PHYS_BASE(1)), %ecx + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x26) + + /* Enable the L2 cache. */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr + + post_code(0x27) + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + wrmsr + + post_code(0x28) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* enable no evict mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $2, %eax + wrmsr + + post_code(0x29) + + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp + + /* Push the initial TSC value from boot block. The low 32 bits are + * in mm0, and the high 32 bits are in mm1. */ + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x2a) + /* Call car.c main function. */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) + +.Lhlt: + hlt + jmp .Lhlt + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Gerrit-Change-Number: 30778 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019