coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: qemu-q35: die if started on wrong machine
by Patrick Rudolph (Code Review) 08 Jul '19

08 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31425 Change subject: qemu-q35: die if started on wrong machine ...................................................................... qemu-q35: die if started on wrong machine The QEMU machine "PC" doesn't support MCFG. Die in bootblock if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31425/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 18a083d..96d3457 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -14,6 +14,7 @@ #include <arch/io.h> #include <bootblock_common.h> #include <southbridge/intel/i82801ix/i82801ix.h> +#include <console/console.h> /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,6 +40,11 @@ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* MCFG is now active. If it's not qemu was started for machine PC */ + if (pci_read_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1)) + die("You must run qemu for machine Q35"); } static void enable_spi_prefetch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Gerrit-Change-Number: 31425 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/mips: Make MIPS specific options depend on select ARCH_MIPS
by Arthur Heymans (Code Review) 07 Jul '19

07 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31312 Change subject: arch/mips: Make MIPS specific options depend on select ARCH_MIPS ...................................................................... arch/mips: Make MIPS specific options depend on select ARCH_MIPS Also don't define the default as this result in spurious lines in the .config. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/mips/Kconfig M src/soc/imgtec/pistachio/Kconfig 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31312/1 diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 9e51d9c..b8570c1 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -16,12 +16,12 @@ config ARCH_MIPS bool - default n + +if ARCH_MIPS config ARCH_BOOTBLOCK_MIPS bool default n - select ARCH_MIPS select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK @@ -36,3 +36,5 @@ config ARCH_RAMSTAGE_MIPS bool default n + +endif # if ARCH_MIPS diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 333216d..40b63c3 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -15,6 +15,7 @@ # config CPU_IMGTEC_PISTACHIO + select ARCH_MIPS select ARCH_BOOTBLOCK_MIPS select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS -- To view, visit https://review.coreboot.org/c/coreboot/+/31312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Gerrit-Change-Number: 31312 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms
by Arthur Heymans (Code Review) 02 Jul '19

02 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31311 Change subject: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms ...................................................................... arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31311/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..f5253bb 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,6 +24,7 @@ # one implementation that will not have it due # to security concerns. bool + depends on ARCH_RISCV default n if ARCH_RISCV_M_DISABLED default y -- To view, visit https://review.coreboot.org/c/coreboot/+/31311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Gerrit-Change-Number: 31311 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gat...
by Jeremy Soller (Code Review) 01 Jul '19

01 Jul '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31534 Change subject: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter ...................................................................... soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31534/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..534065f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -128,6 +128,10 @@ /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = config->clock_gate_8254; + params->Enable8254ClockGatingOnS3 = config->clock_gate_8254; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- To view, visit https://review.coreboot.org/c/coreboot/+/31534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e Gerrit-Change-Number: 31534 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add devicetreee options for root ports
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32011 Change subject: soc/apl: Add devicetreee options for root ports ...................................................................... soc/apl: Add devicetreee options for root ports List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency - PcieRpAspm Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..8b38895 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -695,6 +695,24 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + memcpy(silconfig->PcieRpPmSci, cfg->pcie_rp_pm_sci, + sizeof(silconfig->PcieRpPmSci)); + + memcpy(silconfig->PcieRpTransmitterHalfSwing, + cfg->pcie_rp_transmitter_halfswing, + sizeof(silconfig->PcieRpTransmitterHalfSwing)); + + memcpy(silconfig->PcieRpLtrMaxSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxSnoopLatency)); + + memcpy(silconfig->PcieRpLtrMaxNonSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxNonSnoopLatency)); + + memcpy(silconfig->PcieRpAspm, cfg->pcie_rp_aspm, + sizeof(silconfig->PcieRpAspm)); + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/32011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Gerrit-Change-Number: 32011 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add eMMC and Sdcard config options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32049 Change subject: soc/apl: Add eMMC and Sdcard config options ...................................................................... soc/apl: Add eMMC and Sdcard config options Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32049/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..3a405af 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,9 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->eMMCEnabled = cfg->emmc_enabled; + silconfig->SdcardEnabled = cfg->sdcard_enabled; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..a995f2d 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,9 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t emmc_enabled; + uint8_t sdcard_enabled; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Gerrit-Change-Number: 32049 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add HdAudioDspUaaCompliance to devicetree
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32047 Change subject: soc/apl: Add HdAudioDspUaaCompliance to devicetree ...................................................................... soc/apl: Add HdAudioDspUaaCompliance to devicetree Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32047/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..5f83906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,8 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->HdAudioDspUaaCompliance = cfg->hdaudio_dsp_uaa_compliance; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..e3bcfe5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -127,6 +127,8 @@ uint8_t hdaudio_pwr_gate_enable; uint8_t hdaudio_bios_config_lockdown; + uint8_t hdaudio_dsp_uaa_compliance; + /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; -- To view, visit https://review.coreboot.org/c/coreboot/+/32047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Gerrit-Change-Number: 32047 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add C-States configuration options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32050 Change subject: soc/apl: Add C-States configuration options ...................................................................... soc/apl: Add C-States configuration options FSP-S options: - C1e - PkgCStateLimit - CStateAutoDemotion - CStateUnDemotion - PkgCStateDemotion - PkgCStateUnDemotion Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32050/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..15f2ba8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,13 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->C1e = cfg->c1e; + silconfig->PkgCStateLimit = cfg->pkg_cstate_limit; + silconfig->CStateAutoDemotion = cfg->cstate_auto_demotion; + silconfig->CStateUnDemotion = cfg->cstate_undemotion; + silconfig->PkgCStateDemotion = cfg->pkg_cstate_demotion; + silconfig->PkgCStateUnDemotion = cfg->pkg_cstate_undemotion; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..6015acf 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,13 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t c1e; + uint8_t pkg_cstate_limit; + uint8_t cstate_auto_demotion; + uint8_t cstate_undemotion; + uint8_t pkg_cstate_demotion; + uint8_t pkg_cstate_undemotion; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Gerrit-Change-Number: 32050 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S AtomBIOS ROMs: known good binaries with a script to check their...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31944 to review the following change. Change subject: G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 ...................................................................... G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 This change is a mirror for the known good AMD Lenovo G505S AtomBIOS ROMs from this repository - https://github.com/g505s-opensource-researcher/g505s-atombios AtomBIOS ROMs are required to enable the integrated and discrete VGA adapters, however to add the discrete GPU support you will also need to apply these patches: https://review.coreboot.org/c/coreboot/+/31929 G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches Here are the SHA256 checksums for these AtomBIOS ROMs: 6104e6989ea3f494d7bfa30573bf38e830f1068bab9980caec5e890e0ccbfced ./pci1002,990b.rom - for integrated GPU (iGPU) HD-8650G 6052b5def3fda2a93f6c4d55ec91b819429e212e26cdb8e0fcca54599c9c92ed ./pci1002,6663.rom - for discrete GPU (dGPU) HD-8570M 15d74515332bc512de66e0dc910d8600aeb134bf715bbc34a4faac0257f4a0dc ./pci1002,6665.rom - for discrete GPU (dGPU) R5-M230 Save to ./coreboot/ then run ./extract_atombios_roms.sh and ./check... . Could analyze these ROMs with AtomDis - https://cgit.freedesktop.org/~mhopf/AtomDis/ pci1002,990b.rom (for iGPU HD-8650G) has been taken from G505S with R5-M230, and despite the tiny voltage difference - it's working great for all G505S versions. https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/ GZNWISLFHUTYN6C7RTWSQUMJIFOUHMED/ Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 --- A check_atombios_roms.sh A extract_atombios_roms.sh A pci1002,6663.rom.txt A pci1002,6665.rom.txt A pci1002,990b.rom.txt A sha256sums_atombios_correct.txt 6 files changed, 8,082 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31944/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 Gerrit-Change-Number: 31944 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31929 to review the following change. Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the three changes 31357, 31448, 31450 to add the discrete GPU support for AMD Lenovo G505S laptop. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31357 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31929/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..972800a --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < 54dd729.diff diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..cae1e9f --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,11 @@ +#!/bin/sh +rm -f ./sha256sums_dgpu_my.txt +sha256sum ./f5c1e4d.diff > ./sha256sums_dgpu_my.txt +sha256sum ./828c74a.diff >> ./sha256sums_dgpu_my.txt +sha256sum ./54dd729.diff >> ./sha256sums_dgpu_my.txt +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" +fi diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..c1703df --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,20 @@ +#!/bin/sh +rm -f ./*.diff && rm -f ./patch\?zip +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +wget https://review.coreboot.org/changes/31357/revisions/6/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +wget https://review.coreboot.org/changes/31448/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +wget https://review.coreboot.org/changes/31450/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 54dd729.diff diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b519a6a --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,3 @@ +1e6dff37ae1b8080c431f25b7a12c561bd949dfa68f6487a1bece39941f74195 ./f5c1e4d.diff +1879c633478c105eb9d66afa97fc59db0c850a813d4bcdb3693a6f52645092d8 ./828c74a.diff +a055e0d1fff668b95da68b7b6c7274d000bbf90572747b4f33de7f5f59a5bb44 ./54dd729.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/31929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 Gerrit-Change-Number: 31929 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019