coreboot-gerrit March 2019

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Change in ...coreboot[master]: arch/arm: Make ARM specific options depend on select ARCH_ARM
by Arthur Heymans (Code Review) 29 Aug '19

29 Aug '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31313 Change subject: arch/arm: Make ARM specific options depend on select ARCH_ARM ...................................................................... arch/arm: Make ARM specific options depend on select ARCH_ARM Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig 8 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31313/1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 6d9cc78..14d054a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,11 +1,11 @@ config ARCH_ARM bool - default n + +if ARCH_ARM config ARCH_BOOTBLOCK_ARM bool default n - select ARCH_ARM select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM @@ -26,3 +26,5 @@ config ARM_LPAE bool default n + +endif #if ARCH_ARM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index eecb59b..e9e43a5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA124 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV7 diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 8883baa..52118c3 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA210 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV4 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05fa..7a0648c 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ40XX bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0b112d9..3bea529 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ806X bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 53666c2..654374c 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -16,6 +16,7 @@ config SOC_ROCKCHIP_RK3288 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 5b39724..149d703 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5250 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7b87650..4ffbf7f 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5420 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Gerrit-Change-Number: 31313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 27 Aug '19

27 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30901 Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc D src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/include/soc/sd.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/sd.c 8 files changed, 490 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30901/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 2dac283..54d97f7 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,12 +11,26 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += memlayout.ld bootblock-y += flash.c -bootblock-y += bootblock.c +bootblock-y += media.c +romstage-y += memlayout.ld romstage-y += flash.c +romstage-y += media.c romstage-y += romstage.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld ramstage-y += memlayout.ld +ramstage-y += flash.c +ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw + diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c deleted file mode 100644 index 777b2aa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/bootblock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/spi.h> -#include <soc/spi_flash.h> -#include <soc/clock.h> - -extern void flash_init(void); -extern void bootblock_mainboard_init(void); - -void bootblock_mainboard_init(void) -{ - flash_init(); -} diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..4a8f463 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/sd.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> + +void flash_init(void); +// void boot_device_init(void); +// const struct region_device *boot_device_ro(void); + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device spi_mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + if (offset / 512 == (offset + count - 1) / 512) { + size_t lba = offset / 512; + size_t o = offset % 512; + size_t l = count; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } else { + int has_begin = !!(offset % 512); + int has_end = !!((offset + count) % 512); + size_t first_lba = offset / 512; + size_t last_lba = (offset + count - 1) / 512; + if (has_begin) { + size_t lba = first_lba; + size_t o = offset % 512; + size_t l = 512 - o; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } + if (first_lba + has_begin <= last_lba - has_end) { + size_t lba = first_lba + has_begin; + size_t size = (last_lba - has_end) - (first_lba + has_begin) + 1; + size_t o = 512 - offset % 512; + if (sd_copy((spi_ctrl*)FU540_QSPI2, dest + o, lba, size) != 0) { + return -1; + } + } + if (has_end) { + size_t lba = last_lba; + size_t o = 0; + size_t l = (offset + count) % 512; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest + count - l, tmp + o, l); + } + } + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + + +const struct region_device *boot_device_ro() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; +} + +void boot_device_init() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + flash_init(); + break; + case 11: + sd_init((spi_ctrl*)FU540_QSPI2, clock_get_tlclk_khz()); + mmap_helper_device_init(&sd_mdev, _cbfs_cache, _cbfs_cache_size); + break; + default: + die("Wrong configuration of MSEL"); + } +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 83c7b1c..866267e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,28 +15,31 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +# bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += spi.c +bootblock-y += sd.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +# romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c romstage-y += spi.c +romstage-y += sd.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +# ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sd.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } diff --git a/src/soc/sifive/fu540/include/soc/sd.h b/src/soc/sifive/fu540/include/soc/sd.h new file mode 100644 index 0000000..679d0f4 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/sd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _LIBRARIES_SD_H +#define _LIBRARIES_SD_H + +#define SD_INIT_ERROR_CMD0 1 +#define SD_INIT_ERROR_CMD8 2 +#define SD_INIT_ERROR_ACMD41 3 +#define SD_INIT_ERROR_CMD58 4 +#define SD_INIT_ERROR_CMD16 5 + +#define SD_COPY_ERROR_CMD18 1 +#define SD_COPY_ERROR_CMD18_CRC 2 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +int sd_init(spi_ctrl* spi, unsigned int input_clk_hz); +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size); + +#endif /* !__ASSEMBLER__ */ + +#endif /* _LIBRARIES_SD_H */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/sd.c b/src/soc/sifive/fu540/sd.c new file mode 100644 index 0000000..3af26ad --- /dev/null +++ b/src/soc/sifive/fu540/sd.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/spi.h> +#include <soc/sd.h> + + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SD_CMD_GO_IDLE_STATE 0 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_CMD 55 +#define SD_CMD_READ_OCR 58 +#define SD_RESPONSE_IDLE 0x1 +// Data token for commands 17, 18, 24 +#define SD_DATA_TOKEN 0xfe + + +// SD card initialization must happen at 100-400kHz +#define SD_POWER_ON_FREQ_KHZ 400L +// SD cards normally support reading/writing at 20MHz +#define SD_POST_INIT_CLK_KHZ 20000L + + +// Command frame starts by asserting low and then high for first two clock edges +#define SD_CMD(cmd) (0x40 | (cmd)) + + +/** + * Send dummy byte (all ones). + * + * Used in many cases to read one byte from SD card, since SPI is a full-duplex + * protocol and it is necessary to send a byte in order to read a byte. + */ +static inline uint8_t sd_dummy(spi_ctrl* spi) +{ + return spi_txrx(spi, 0xFF); +} + + +static int sd_cmd(spi_ctrl* spi, uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + spi->csmode.mode = SPI_CSMODE_HOLD; + sd_dummy(spi); + spi_txrx(spi, cmd); + spi_txrx(spi, arg >> 24); + spi_txrx(spi, arg >> 16); + spi_txrx(spi, arg >> 8); + spi_txrx(spi, arg); + spi_txrx(spi, crc); + + n = 1000; + do { + r = sd_dummy(spi); + if (!(r & 0x80)) { + break; + } + } while (--n > 0); + return r; +} + + +static inline void sd_cmd_end(spi_ctrl* spi) +{ + sd_dummy(spi); + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(spi_ctrl* spi, unsigned int input_clk_khz) +{ + // Initialize SPI controller + spi->fmt.raw_bits = ((spi_reg_fmt) { + .proto = SPI_PROTO_S, + .dir = SPI_DIR_RX, + .endian = SPI_ENDIAN_MSB, + .len = 8, + }).raw_bits; + spi->csdef |= 0x1; + spi->csid = 0; + + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POWER_ON_FREQ_KHZ); + spi->csmode.mode = SPI_CSMODE_OFF; + + for (int i = 10; i > 0; i--) { + // Set SD card pin DI high for 74+ cycles + // SD CMD pin is the same pin as SPI DI, so CMD = 0xff means assert DI high + // for 8 cycles. + sd_dummy(spi); + } + + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +/** + * Reset card. + */ +static int sd_cmd0(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_GO_IDLE_STATE), 0, 0x95) != SD_RESPONSE_IDLE); + sd_cmd_end(spi); + return rc; +} + + +/** + * Check for SD version and supported voltages. + */ +static int sd_cmd8(spi_ctrl* spi) +{ + // Check for high capacity cards + // Fail if card does not support SDHC + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SEND_IF_COND), 0x000001AA, 0x87) != SD_RESPONSE_IDLE); + sd_dummy(spi); /* command version; reserved */ + sd_dummy(spi); /* reserved */ + rc |= ((sd_dummy(spi) & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy(spi) != 0xAA); /* check pattern */ + sd_cmd_end(spi); + return rc; +} + + +/** + * Send app command. Used as prefix to app commands (ACMD). + */ +static void sd_cmd55(spi_ctrl* spi) +{ + sd_cmd(spi, SD_CMD(SD_CMD_APP_CMD), 0, 0x65); + sd_cmd_end(spi); +} + + +/** + * Start SDC initialization process. + */ +static int sd_acmd41(spi_ctrl* spi) +{ + uint8_t r; + do { + sd_cmd55(spi); + r = sd_cmd(spi, SD_CMD(SD_CMD_APP_SEND_OP_COND), 0x40000000, 0x77); /* HCS = 1 */ + sd_cmd_end(spi); + } while (r == SD_RESPONSE_IDLE); + return (r != 0x00); +} + + +/** + * Read operation conditions register (OCR) to check for availability of block + * addressing mode. + */ +static int sd_cmd58(spi_ctrl* spi) +{ + // HACK: Disabled due to bugs. It is not strictly necessary + // to issue this command if we only support SD cards that support SDHC mode. + return 0; + // int rc; + // rc = (sd_cmd(spi, SD_CMD(SD_CMD_READ_OCR), 0, 0xFD) != 0x00); + // rc |= ((sd_dummy(spi) & 0x80) != 0x80); /* Power up status */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_cmd_end(spi); + // return rc; +} + + +/** + * Set block addressing mode. + */ +static int sd_cmd16(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SET_BLOCKLEN), 0x200, 0x15) != 0x00); + sd_cmd_end(spi); + return rc; +} + + +static uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + + +static uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + + +//int sd_init(spi_ctrl* spi, unsigned int input_clk_khz, int skip_sd_init_commands) +int sd_init(spi_ctrl* spi, unsigned int input_clk_khz) +{ + sd_poweron(spi, input_clk_khz); + if (sd_cmd0(spi)) + return SD_INIT_ERROR_CMD0; + if (sd_cmd8(spi)) + return SD_INIT_ERROR_CMD8; + if (sd_acmd41(spi)) + return SD_INIT_ERROR_ACMD41; + if (sd_cmd58(spi)) + return SD_INIT_ERROR_CMD58; + if (sd_cmd16(spi)) + return SD_INIT_ERROR_CMD16; + + // Increase clock frequency after initialization for higher performance. + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POST_INIT_CLK_KHZ); + return 0; +} + + +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t c = 0; + c = crc7(c, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE)); + c = crc7(c, src_lba >> 24); + c = crc7(c, (src_lba >> 16) & 0xff); + c = crc7(c, (src_lba >> 8) & 0xff); + c = crc7(c, src_lba & 0xff); + c = (c << 1) | 1; + if (sd_cmd(spi, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE), src_lba, c) != 0x00) { + sd_cmd_end(spi); + return SD_COPY_ERROR_CMD18; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy(spi) != SD_DATA_TOKEN); + do { + uint8_t x = sd_dummy(spi); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy(spi) << 8); + crc_exp |= sd_dummy(spi); + + if (crc != crc_exp) { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + } while (--i > 0); + + sd_cmd(spi, SD_CMD(SD_CMD_STOP_TRANSMISSION), 0, 0x01); + sd_cmd_end(spi); + return rc; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Gerrit-Change-Number: 30901 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

4 25

Change in ...coreboot[master]: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG
by You-Cheng Syu (Code Review) 26 Aug '19

26 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31844 Change subject: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG ...................................................................... google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG so that it will query the reset reason from EC during watchdog initialization. Besides, we should set BOOTBLOCK_EN_L before mtk_wdt_init so that we can communicate with EC at the time. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. see 'WDT: Last reset was hardware watchdog' in AP console 4. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/early_init.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31844/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..4d4feac 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -33,6 +33,7 @@ select FATAL_ASSERTS select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..9495af3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -25,11 +25,11 @@ void mainboard_early_init(void) { - mt8183_early_init(); - /* Turn on real eMMC and allow communication to EC. */ gpio_output(BOOTBLOCK_EN_L, 1); + mt8183_early_init(); + setup_chromeos_gpios(); /* Declare we are in S0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Gerrit-Change-Number: 31844 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: ec/google/chromeec: Add AP watchdog into reset causes and reset flags.
by You-Cheng Syu (Code Review) 23 Aug '19

23 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31834 Change subject: ec/google/chromeec: Add AP watchdog into reset causes and reset flags. ...................................................................... ec/google/chromeec: Add AP watchdog into reset causes and reset flags. Add the new reset cause (from ChromiumOS CL:1293132) and new reset flag (from ChromiumOS CL:1295890). BUG=b:109900671,b:118654976 BRANCH=none TEST=none Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/ec/google/chromeec/ec.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31834/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 629144c..a5f068e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -963,6 +963,7 @@ "reset: debug warm reboot", "reset: at AP's request", "reset: during EC initialization", + "reset: AP watchdog", }; static const size_t shutdown_cause_begin = 1 << 15; @@ -1016,7 +1017,8 @@ "usb-resume", "rdd", "rbox", - "security" + "security", + "ap-watchdog", }; struct ec_response_uptime_info cmd_resp; int i, flag, flag_count; -- To view, visit https://review.coreboot.org/c/coreboot/+/31834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d Gerrit-Change-Number: 31834 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

7 26

Change in ...coreboot[master]: ec/google/chromeec: Update ec_commands.h and add compile_time_macros.h
by You-Cheng Syu (Code Review) 23 Aug '19

23 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31885 Change subject: ec/google/chromeec: Update ec_commands.h and add compile_time_macros.h ...................................................................... ec/google/chromeec: Update ec_commands.h and add compile_time_macros.h Copy ec_commands.h from ChromiumOS CL:1520574 (except for keeping the long-form license header). Also copy compile_time_macros.h from ChromiumOS EC repository, with some modification to avoid compile errors (redefining ARRAY_SIZE and member_size). BUG=b:109900671,b:118654976 BRANCH=none TEST=emerge-kukui -j coreboot Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- A src/ec/google/chromeec/compile_time_macros.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 1,267 insertions(+), 665 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31885/1 diff --git a/src/ec/google/chromeec/compile_time_macros.h b/src/ec/google/chromeec/compile_time_macros.h new file mode 100644 index 0000000..c38ef55 --- /dev/null +++ b/src/ec/google/chromeec/compile_time_macros.h @@ -0,0 +1,42 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Handy clever tricks */ + +#ifndef __CROS_EC_COMPILE_TIME_MACROS_H +#define __CROS_EC_COMPILE_TIME_MACROS_H + +/* Test an important condition at compile time, not run time */ +#define _BA1_(cond, line) \ + extern int __build_assertion_ ## line[1 - 2*!(cond)] \ + __attribute__ ((unused)) +#define _BA0_(c, x) _BA1_(c, x) +#define BUILD_ASSERT(cond) _BA0_(cond, __LINE__) + +/* + * Test an important condition inside code path at run time, taking advantage of + * -Werror=div-by-zero. + */ +#define BUILD_CHECK_INLINE(value, cond_true) ((value) / (!!(cond_true))) + +/* Number of elements in an array */ +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/* Make for loops that iterate over pointers to array entries more readable */ +#define ARRAY_BEGIN(array) (array) +#define ARRAY_END(array) ((array) + ARRAY_SIZE(array)) + +/* Just in case - http://gcc.gnu.org/onlinedocs/gcc/Offsetof.html */ +#ifndef offsetof +#define offsetof(type, member) __builtin_offsetof(type, member) +#endif + +#ifndef member_size +#define member_size(type, member) sizeof(((type *)0)->member) +#endif + +#endif /* __CROS_EC_COMPILE_TIME_MACROS_H */ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 140ba5a..eb0ee55 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -35,6 +35,10 @@ #include <stdint.h> #endif +#ifdef __cplusplus +extern "C" { +#endif + /* * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This * generates more efficient code for accessing request/response structures on @@ -44,6 +48,12 @@ #include "common.h" #endif +#ifdef __KERNEL__ +#define BUILD_ASSERT(_cond) +#else +#include "compile_time_macros.h" +#endif + /* * Current version of this protocol * @@ -347,10 +357,19 @@ /* * Report device orientation - * bit 0 device is tablet mode + * Bits Definition + * 3:1 Device DPTF Profile Number (DDPN) + * 0 = Reserved for backward compatibility (indicates no valid + * profile number. Host should fall back to using TBMD). + * 1..7 = DPTF Profile number to indicate to host which table needs + * to be loaded. + * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 /* * Report device features. Uses the same format as the host command, except: @@ -615,7 +634,7 @@ /* EC desires to change state of host-controlled USB mux */ EC_HOST_EVENT_USB_MUX = 28, - /* TABLET/LAPTOP mode event*/ + /* TABLET/LAPTOP mode or detachable base attach/detach event */ EC_HOST_EVENT_MODE_CHANGE = 29, /* Keyboard recovery combo with hardware reinitialization */ @@ -633,17 +652,20 @@ /* Host event mask */ #define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) -/* Arguments at EC_LPC_ADDR_HOST_ARGS */ -struct __ec_align4 ec_lpc_host_args { +/** + * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS + * @flags: The host argument flags. + * @command_version: Command version. + * @data_size: The length of data. + * @checksum: Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ +struct ec_lpc_host_args { uint8_t flags; uint8_t command_version; uint8_t data_size; - /* - * Checksum; sum of command + flags + command_version + data_size + - * all params/response data bytes. - */ uint8_t checksum; -}; +} __ec_align4; /* Flags for ec_lpc_host_args.flags */ /* @@ -795,56 +817,45 @@ #define EC_HOST_REQUEST_VERSION 3 -/* Version 3 request from host */ -struct __ec_align4 ec_host_request { - /* Structure version (=3) - * - * EC will return EC_RES_INVALID_HEADER if it receives a header with a - * version it doesn't know how to parse. - */ +/** + * struct ec_host_request - Version 3 request from host. + * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it + * receives a header with a version it doesn't know how to + * parse. + * @checksum: Checksum of request and data; sum of all bytes including checksum + * should total to 0. + * @command: Command to send (EC_CMD_...) + * @command_version: Command version. + * @reserved: Unused byte in current protocol version; set to 0. + * @data_len: Length of data which follows this header. + */ +struct ec_host_request { uint8_t struct_version; - - /* - * Checksum of request and data; sum of all bytes including checksum - * should total to 0. - */ uint8_t checksum; - - /* Command code */ uint16_t command; - - /* Command version */ uint8_t command_version; - - /* Unused byte in current protocol version; set to 0 */ uint8_t reserved; - - /* Length of data which follows this header */ uint16_t data_len; -}; +} __ec_align4; #define EC_HOST_RESPONSE_VERSION 3 -/* Version 3 response from EC */ -struct __ec_align4 ec_host_response { - /* Structure version (=3) */ +/** + * struct ec_host_response - Version 3 response from EC. + * @struct_version: Struct version (=3). + * @checksum: Checksum of response and data; sum of all bytes including + * checksum should total to 0. + * @result: EC's response to the command (separate from communication failure) + * @data_len: Length of data which follows this header. + * @reserved: Unused bytes in current protocol version; set to 0. + */ +struct ec_host_response { uint8_t struct_version; - - /* - * Checksum of response and data; sum of all bytes including checksum - * should total to 0. - */ uint8_t checksum; - - /* Result code (EC_RES_*) */ uint16_t result; - - /* Length of data which follows this header */ uint16_t data_len; - - /* Unused bytes in current protocol version; set to 0 */ uint16_t reserved; -}; +} __ec_align4; /*****************************************************************************/ @@ -907,7 +918,7 @@ */ /* Version 4 request from host */ -struct __ec_align4 ec_host_request4 { +struct ec_host_request4 { /* * bits 0-3: struct_version: Structure version (=4) * bit 4: is_response: Is response (=0) @@ -934,10 +945,10 @@ /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ uint8_t header_crc; -}; +} __ec_align4; /* Version 4 response from EC */ -struct __ec_align4 ec_host_response4 { +struct ec_host_response4 { /* * bits 0-3: struct_version: Structure version (=4) * bit 4: is_response: Is response (=1) @@ -963,7 +974,7 @@ /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ uint8_t header_crc; -}; +} __ec_align4; /* Fields in fields0 byte */ #define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f @@ -1000,9 +1011,13 @@ */ #define EC_CMD_PROTO_VERSION 0x0000 -struct __ec_align4 ec_response_proto_version { +/** + * struct ec_response_proto_version - Response to the proto version command. + * @version: The protocol version. + */ +struct ec_response_proto_version { uint32_t version; -}; +} __ec_align4; /* * Hello. This is a simple command to test the EC is responsive to @@ -1010,13 +1025,21 @@ */ #define EC_CMD_HELLO 0x0001 -struct __ec_align4 ec_params_hello { - uint32_t in_data; /* Pass anything here */ -}; +/** + * struct ec_params_hello - Parameters to the hello command. + * @in_data: Pass anything here. + */ +struct ec_params_hello { + uint32_t in_data; +} __ec_align4; -struct __ec_align4 ec_response_hello { - uint32_t out_data; /* Output will be in_data + 0x01020304 */ -}; +/** + * struct ec_response_hello - Response to the hello command. + * @out_data: Output will be in_data + 0x01020304. + */ +struct ec_response_hello { + uint32_t out_data; +} __ec_align4; /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 @@ -1027,25 +1050,40 @@ EC_IMAGE_RW }; -struct __ec_align4 ec_response_get_version { - /* Null-terminated version strings for RO, RW */ +/** + * struct ec_response_get_version - Response to the get version command. + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @reserved: Unused bytes; was previously RW-B firmware version string. + * @current_image: One of ec_current_image. + */ +struct ec_response_get_version { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Was previously RW-B string */ - uint32_t current_image; /* One of ec_current_image */ -}; + char reserved[32]; + uint32_t current_image; +} __ec_align4; /* Read test */ #define EC_CMD_READ_TEST 0x0003 -struct __ec_align4 ec_params_read_test { - uint32_t offset; /* Starting value for read buffer */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_test - Parameters for the read test command. + * @offset: Starting value for read buffer. + * @size: Size to read in bytes. + */ +struct ec_params_read_test { + uint32_t offset; + uint32_t size; +} __ec_align4; -struct __ec_align4 ec_response_read_test { +/** + * struct ec_response_read_test - Response to the read test command. + * @data: Data returned by the read test command. + */ +struct ec_response_read_test { uint32_t data[32]; -}; +} __ec_align4; /* * Get build information @@ -1057,19 +1095,28 @@ /* Get chip info */ #define EC_CMD_GET_CHIP_INFO 0x0005 -struct __ec_align4 ec_response_get_chip_info { - /* Null-terminated strings */ +/** + * struct ec_response_get_chip_info - Response to the get chip info command. + * @vendor: Null-terminated string for chip vendor. + * @name: Null-terminated string for chip name. + * @revision: Null-terminated string for chip mask version. + */ +struct ec_response_get_chip_info { char vendor[32]; char name[32]; - char revision[32]; /* Mask version */ -}; + char revision[32]; +} __ec_align4; /* Get board HW version */ #define EC_CMD_GET_BOARD_VERSION 0x0006 -struct __ec_align2 ec_response_board_version { - uint16_t board_version; /* A monotonously incrementing number. */ -}; +/** + * struct ec_response_board_version - Response to the board version command. + * @board_version: A monotonously incrementing number. + */ +struct ec_response_board_version { + uint16_t board_version; +} __ec_align2; /* * Read memory-mapped data. @@ -1081,29 +1128,44 @@ */ #define EC_CMD_READ_MEMMAP 0x0007 -struct __ec_align1 ec_params_read_memmap { - uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ - uint8_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_memmap - Parameters for the read memory map command. + * @offset: Offset in memmap (EC_MEMMAP_*). + * @size: Size to read in bytes. + */ +struct ec_params_read_memmap { + uint8_t offset; + uint8_t size; +} __ec_align1; /* Read versions supported for a command */ #define EC_CMD_GET_CMD_VERSIONS 0x0008 -struct __ec_align1 ec_params_get_cmd_versions { - uint8_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions - Parameters for the get command versions. + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions { + uint8_t cmd; +} __ec_align1; -struct __ec_align2 ec_params_get_cmd_versions_v1 { - uint16_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions_v1 - Parameters for the get command + * versions (v1) + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions_v1 { + uint16_t cmd; +} __ec_align2; -struct __ec_align4 ec_response_get_cmd_versions { - /* - * Mask of supported versions; use EC_VER_MASK() to compare with a - * desired version. - */ +/** + * struct ec_response_get_cmd_version - Response to the get command versions. + * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with + * a desired version. + */ +struct ec_response_get_cmd_versions { uint32_t version_mask; -}; +} __ec_align4; /* * Check EC communications status (busy). This is needed on i2c/spi but not @@ -1119,24 +1181,29 @@ EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ }; -struct __ec_align4 ec_response_get_comms_status { +/** + * struct ec_response_get_comms_status - Response to the get comms status + * command. + * @flags: Mask of enum ec_comms_status. + */ +struct ec_response_get_comms_status { uint32_t flags; /* Mask of enum ec_comms_status */ -}; +} __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ #define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ -struct __ec_align4 ec_params_test_protocol { +struct ec_params_test_protocol { uint32_t ec_result; uint32_t ret_len; uint8_t buf[32]; -}; +} __ec_align4; /* Here it comes... */ -struct __ec_align4 ec_response_test_protocol { +struct ec_response_test_protocol { uint8_t buf[32]; -}; +} __ec_align4; /* Get protocol information */ #define EC_CMD_GET_PROTOCOL_INFO 0x000B @@ -1145,21 +1212,21 @@ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ #define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) -struct __ec_align4 ec_response_get_protocol_info { +/** + * struct ec_response_get_protocol_info - Response to the get protocol info. + * @protocol_versions: Bitmask of protocol versions supported (1 << n means + * version n). + * @max_request_packet_size: Maximum request packet size in bytes. + * @max_response_packet_size: Maximum response packet size in bytes. + * @flags: see EC_PROTOCOL_INFO_* + */ +struct ec_response_get_protocol_info { /* Fields which exist if at least protocol version 3 supported */ - - /* Bitmask of protocol versions supported (1 << n means version n)*/ uint32_t protocol_versions; - - /* Maximum request packet size, in bytes */ uint16_t max_request_packet_size; - - /* Maximum response packet size, in bytes */ uint16_t max_response_packet_size; - - /* Flags; see EC_PROTOCOL_INFO_* */ uint32_t flags; -}; +} __ec_align4; /*****************************************************************************/ @@ -1168,19 +1235,21 @@ /* The upper byte of .flags tells what to do (nothing means "get") */ #define EC_GSV_SET 0x80000000 -/* The lower three bytes of .flags identifies the parameter, if that has - meaning for an individual command. */ +/* + * The lower three bytes of .flags identifies the parameter, if that has + * meaning for an individual command. + */ #define EC_GSV_PARAM_MASK 0x00ffffff -struct __ec_align4 ec_params_get_set_value { +struct ec_params_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; -struct __ec_align4 ec_response_get_set_value { +struct ec_response_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; /* More than one command can use these structs to get/set parameters. */ #define EC_CMD_GSV_PAUSE_IN_S5 0x000C @@ -1286,13 +1355,26 @@ EC_FEATURE_CEC = 35, /* EC supports tight sensor timestamping. */ EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36, + /* + * EC supports tablet mode detection aligned to Chrome and allows + * setting of threshold by host command using + * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. + */ + EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* EC supports audio codec. */ + EC_FEATURE_AUDIO_CODEC = 38, + /* EC Supports SCP. */ + EC_FEATURE_SCP = 39, + /* The MCU is an Integrated Sensor Hub */ + EC_FEATURE_ISH = 40, }; #define EC_FEATURE_MASK_0(event_code) (1UL << (event_code % 32)) #define EC_FEATURE_MASK_1(event_code) (1UL << (event_code - 32)) -struct __ec_align4 ec_response_get_features { + +struct ec_response_get_features { uint32_t flags[2]; -}; +} __ec_align4; /*****************************************************************************/ /* Get the board's SKU ID from EC */ @@ -1301,9 +1383,9 @@ /* Set SKU ID from AP */ #define EC_CMD_SET_SKU_ID 0x000F -struct __ec_align4 ec_sku_id_info { +struct ec_sku_id_info { uint32_t sku_id; -}; +} __ec_align4; /*****************************************************************************/ /* Flash commands */ @@ -1312,39 +1394,56 @@ #define EC_CMD_FLASH_INFO 0x0010 #define EC_VER_FLASH_INFO 2 -/* Version 0 returns these fields */ -struct __ec_align4 ec_response_flash_info { - /* Usable flash size, in bytes */ +/** + * struct ec_response_flash_info - Response to the flash info command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * + * Version 0 returns these fields. + */ +struct ec_response_flash_info { uint32_t flash_size; - /* - * Write block size. Write offset and size must be a multiple - * of this. - */ uint32_t write_block_size; - /* - * Erase block size. Erase offset and size must be a multiple - * of this. - */ uint32_t erase_block_size; - /* - * Protection block size. Protection offset and size must be a - * multiple of this. - */ uint32_t protect_block_size; -}; +} __ec_align4; -/* Flags for version 1+ flash info command */ -/* EC flash erases bits to 0 instead of 1 */ +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ #define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) -/* Flash must be selected for read/write/erase operations to succeed. This may +/* + * Flash must be selected for read/write/erase operations to succeed. This may * be necessary on a chip where write/erase can be corrupted by other board * activity, or where the chip needs to enable some sort of programming voltage, * or where the read/write/erase operations require cleanly suspending other - * chip functionality. */ + * chip functionality. + */ #define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) -/* +/** + * struct ec_response_flash_info_1 - Response to the flash info v1 command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if + * size is exactly this and offset is a multiple of this. + * For example, an EC may have a write buffer which can do + * half-page operations if data is aligned, and a slower + * word-at-a-time write mode. + * @flags: Flags; see EC_FLASH_INFO_* + * * Version 1 returns the same initial fields as version 0, with additional * fields following. * @@ -1358,7 +1457,7 @@ * The EC returns the number of banks describing the flash memory. * It adds banks descriptions up to num_banks_desc. */ -struct __ec_align4 ec_response_flash_info_1 { +struct ec_response_flash_info_1 { /* Version 0 fields; see above for description */ uint32_t flash_size; uint32_t write_block_size; @@ -1366,24 +1465,16 @@ uint32_t protect_block_size; /* Version 1 adds these fields: */ - /* - * Ideal write size in bytes. Writes will be fastest if size is - * exactly this and offset is a multiple of this. For example, an EC - * may have a write buffer which can do half-page operations if data is - * aligned, and a slower word-at-a-time write mode. - */ uint32_t write_ideal_size; - - /* Flags; see EC_FLASH_INFO_* */ uint32_t flags; -}; +} __ec_align4; -struct __ec_align4 ec_params_flash_info_2 { +struct ec_params_flash_info_2 { /* Number of banks to describe */ uint16_t num_banks_desc; /* Reserved; set 0; ignore on read */ uint8_t reserved[2]; -}; +} __ec_align4; struct ec_flash_bank { /* Number of sector is in this bank. */ @@ -1400,7 +1491,7 @@ uint8_t reserved[2]; }; -struct __ec_align4 ec_response_flash_info_2 { +struct ec_response_flash_info_2 { /* Total flash in the EC. */ uint32_t flash_size; /* Flags; see EC_FLASH_INFO_* */ @@ -1412,7 +1503,7 @@ /* Number of banks described in banks array. */ uint16_t num_banks_desc; struct ec_flash_bank banks[0]; -}; +} __ec_align4; /* * Read flash @@ -1421,10 +1512,15 @@ */ #define EC_CMD_FLASH_READ 0x0011 -struct __ec_align4 ec_params_flash_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_flash_read - Parameters for the flash read command. + * @offset: Byte offset to read. + * @size: Size to read in bytes. + */ +struct ec_params_flash_read { + uint32_t offset; + uint32_t size; +} __ec_align4; /* Write flash */ #define EC_CMD_FLASH_WRITE 0x0012 @@ -1433,24 +1529,32 @@ /* Version 0 of the flash command supported only 64 bytes of data */ #define EC_FLASH_WRITE_VER0_SIZE 64 -struct __ec_align4 ec_params_flash_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ +/** + * struct ec_params_flash_write - Parameters for the flash write command. + * @offset: Byte offset to write. + * @size: Size to write in bytes. + */ +struct ec_params_flash_write { + uint32_t offset; + uint32_t size; /* Followed by data to write */ -}; +} __ec_align4; /* Erase flash */ #define EC_CMD_FLASH_ERASE 0x0013 -/* v0 */ -struct __ec_align4 ec_params_flash_erase { - uint32_t offset; /* Byte offset to erase */ - uint32_t size; /* Size to erase in bytes */ -}; +/** + * struct ec_params_flash_erase - Parameters for the flash erase command, v0. + * @offset: Byte offset to erase. + * @size: Size to erase in bytes. + */ +struct ec_params_flash_erase { + uint32_t offset; + uint32_t size; +} __ec_align4; - -#define EC_VER_FLASH_WRITE 1 -/* v1 add async erase: +/* + * v1 add async erase: * subcommands can returns: * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. @@ -1472,16 +1576,19 @@ FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; -struct __ec_align4 ec_params_flash_erase_v1 { - /* One of ec_flash_erase_cmd. */ +/** + * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. + * @cmd: One of ec_flash_erase_cmd. + * @reserved: Pad byte; currently always contains 0. + * @flag: No flags defined yet; set to 0. + * @params: Same as v0 parameters. + */ +struct ec_params_flash_erase_v1 { uint8_t cmd; - /* Pad byte; currently always contains 0 */ uint8_t reserved; - /* No flags defined yet; set to 0 */ uint16_t flag; - /* Same as v0 parameters. */ struct ec_params_flash_erase params; -}; +} __ec_align4; /* * Get/set flash protection. @@ -1527,23 +1634,31 @@ /* Rollback information flash region protected now */ #define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) -struct __ec_align4 ec_params_flash_protect { - uint32_t mask; /* Bits in flags to apply */ - uint32_t flags; /* New flags to apply */ -}; -struct __ec_align4 ec_response_flash_protect { - /* Current value of flash protect flags */ +/** + * struct ec_params_flash_protect - Parameters for the flash protect command. + * @mask: Bits in flags to apply. + * @flags: New flags to apply. + */ +struct ec_params_flash_protect { + uint32_t mask; uint32_t flags; - /* - * Flags which are valid on this platform. This allows the caller - * to distinguish between flags which aren't set vs. flags which can't - * be set on this platform. - */ +} __ec_align4; + +/** + * struct ec_response_flash_protect - Response to the flash protect command. + * @flags: Current value of flash protect flags. + * @valid_flags: Flags which are valid on this platform. This allows the + * caller to distinguish between flags which aren't set vs. flags + * which can't be set on this platform. + * @writable_flags: Flags which can be changed given the current protection + * state. + */ +struct ec_response_flash_protect { + uint32_t flags; uint32_t valid_flags; - /* Flags which can be changed given the current protection state */ uint32_t writable_flags; -}; +} __ec_align4; /* * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash @@ -1577,18 +1692,25 @@ /* Number of regions */ EC_FLASH_REGION_COUNT, }; -/* 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated */ +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ #define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE -struct __ec_align4 ec_params_flash_region_info { - uint32_t region; /* enum ec_flash_region */ -}; +/** + * struct ec_params_flash_region_info - Parameters for the flash region info + * command. + * @region: Flash region; see EC_FLASH_REGION_* + */ +struct ec_params_flash_region_info { + uint32_t region; +} __ec_align4; -struct __ec_align4 ec_response_flash_region_info { +struct ec_response_flash_region_info { uint32_t offset; uint32_t size; -}; +} __ec_align4; /* Read/write VbNvContext */ #define EC_CMD_VBNV_CONTEXT 0x0017 @@ -1600,20 +1722,20 @@ EC_VBNV_CONTEXT_OP_WRITE, }; -struct __ec_align4 ec_params_vbnvcontext { +struct ec_params_vbnvcontext { uint32_t op; uint8_t block[EC_VBNV_BLOCK_SIZE]; -}; +} __ec_align4; -struct __ec_align4 ec_response_vbnvcontext { +struct ec_response_vbnvcontext { uint8_t block[EC_VBNV_BLOCK_SIZE]; -}; +} __ec_align4; /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 -struct __ec_align1 ec_response_flash_spi_info { +struct ec_response_flash_spi_info { /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ uint8_t jedec[3]; @@ -1625,16 +1747,19 @@ /* Status registers from command 0x05 and 0x35 */ uint8_t sr1, sr2; -}; +} __ec_align1; /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 -struct __ec_align4 ec_params_flash_select { - /* 1 to select flash, 0 to deselect flash */ +/** + * struct ec_params_flash_select - Parameters for the flash select command. + * @select: 1 to select flash, 0 to deselect flash + */ +struct ec_params_flash_select { uint8_t select; -}; +} __ec_align4; /*****************************************************************************/ @@ -1643,54 +1768,54 @@ /* Get fan target RPM */ #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 -struct __ec_align4 ec_response_pwm_get_fan_rpm { +struct ec_response_pwm_get_fan_rpm { uint32_t rpm; -}; +} __ec_align4; /* Set target fan RPM */ #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 { +struct ec_params_pwm_set_fan_target_rpm_v0 { uint32_t rpm; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 { +struct ec_params_pwm_set_fan_target_rpm_v1 { uint32_t rpm; uint8_t fan_idx; -}; +} __ec_align_size1; /* Get keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 -struct __ec_align1 ec_response_pwm_get_keyboard_backlight { +struct ec_response_pwm_get_keyboard_backlight { uint8_t percent; uint8_t enabled; -}; +} __ec_align1; /* Set keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 -struct __ec_align1 ec_params_pwm_set_keyboard_backlight { +struct ec_params_pwm_set_keyboard_backlight { uint8_t percent; -}; +} __ec_align1; /* Set target fan PWM duty cycle */ #define EC_CMD_PWM_SET_FAN_DUTY 0x0024 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_duty_v0 { +struct ec_params_pwm_set_fan_duty_v0 { uint32_t percent; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 { +struct ec_params_pwm_set_fan_duty_v1 { uint32_t percent; uint8_t fan_idx; -}; +} __ec_align_size1; #define EC_CMD_PWM_SET_DUTY 0x0025 /* 16 bit duty cycle, 0xffff = 100% */ @@ -1706,22 +1831,22 @@ EC_PWM_TYPE_COUNT, }; -struct __ec_align4 ec_params_pwm_set_duty { +struct ec_params_pwm_set_duty { uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ uint8_t pwm_type; /* ec_pwm_type */ uint8_t index; /* Type-specific index, or 0 if unique */ -}; +} __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 -struct __ec_align1 ec_params_pwm_get_duty { +struct ec_params_pwm_get_duty { uint8_t pwm_type; /* ec_pwm_type */ uint8_t index; /* Type-specific index, or 0 if unique */ -}; +} __ec_align1; -struct __ec_align2 ec_response_pwm_get_duty { +struct ec_response_pwm_get_duty { uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ -}; +} __ec_align2; /*****************************************************************************/ /* @@ -1732,15 +1857,17 @@ */ #define EC_CMD_LIGHTBAR_CMD 0x0028 -struct __ec_todo_unpacked rgb_s { +struct rgb_s { uint8_t r, g, b; -}; +} __ec_todo_unpacked; #define LB_BATTERY_LEVELS 4 -/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a + +/* + * List of tweakable parameters. NOTE: It's __packed so it can be sent in a * host command, but the alignment is the same regardless. Keep it that way. */ -struct __ec_todo_packed lightbar_params_v0 { +struct lightbar_params_v0 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1772,9 +1899,9 @@ /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v1 { +struct lightbar_params_v1 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1821,7 +1948,7 @@ /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; /* Lightbar command params v2 * crbug.com/467716 @@ -1832,7 +1959,7 @@ * NOTE: Each of these groups must be less than 120 bytes. */ -struct __ec_todo_packed lightbar_params_v2_timing { +struct lightbar_params_v2_timing { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; @@ -1848,9 +1975,9 @@ int32_t tap_tick_delay; int32_t tap_gate_delay; int32_t tap_display_time; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_tap { +struct lightbar_params_v2_tap { /* Tap-for-battery params */ uint8_t tap_pct_red; uint8_t tap_pct_green; @@ -1858,28 +1985,28 @@ uint8_t tap_seg_max_on; uint8_t tap_seg_osc; uint8_t tap_idx[3]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_oscillation { +struct lightbar_params_v2_oscillation { /* Oscillation */ uint8_t osc_min[2]; /* AC=0/1 */ uint8_t osc_max[2]; /* AC=0/1 */ uint8_t w_ofs[2]; /* AC=0/1 */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_brightness { +struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ uint8_t bright_bl_on_min[2]; /* AC=0/1 */ uint8_t bright_bl_on_max[2]; /* AC=0/1 */ -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_thresholds { +struct lightbar_params_v2_thresholds { /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_colors { +struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ @@ -1889,16 +2016,16 @@ /* Color palette */ struct rgb_s color[8]; /* 0-3 are Google colors */ -}; +} __ec_todo_packed; /* Lightbyte program. */ #define EC_LB_PROG_LEN 192 -struct __ec_todo_unpacked lightbar_program { +struct lightbar_program { uint8_t size; uint8_t data[EC_LB_PROG_LEN]; -}; +} __ec_todo_unpacked; -struct __ec_todo_packed ec_params_lightbar { +struct ec_params_lightbar { uint8_t cmd; /* Command (see enum lightbar_command) */ union { /* @@ -1945,9 +2072,9 @@ struct lightbar_program set_program; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_lightbar { +struct ec_response_lightbar { union { struct __ec_todo_unpacked { struct __ec_todo_unpacked { @@ -1991,7 +2118,7 @@ * set_v2par_thlds, set_v2par_colors */ }; -}; +} __ec_todo_packed; /* Lightbar commands */ enum lightbar_command { @@ -2074,14 +2201,14 @@ EC_LED_COLOR_COUNT }; -struct __ec_align1 ec_params_led_control { +struct ec_params_led_control { uint8_t led_id; /* Which LED to control */ uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; -struct __ec_align1 ec_response_led_control { +struct ec_response_led_control { /* * Available brightness value range. * @@ -2090,7 +2217,7 @@ * Other values means the LED is control by PWM. */ uint8_t brightness_range[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; /*****************************************************************************/ /* Verified boot commands */ @@ -2103,7 +2230,7 @@ /* Verified boot hash command */ #define EC_CMD_VBOOT_HASH 0x002A -struct __ec_align4 ec_params_vboot_hash { +struct ec_params_vboot_hash { uint8_t cmd; /* enum ec_vboot_hash_cmd */ uint8_t hash_type; /* enum ec_vboot_hash_type */ uint8_t nonce_size; /* Nonce size; may be 0 */ @@ -2111,9 +2238,9 @@ uint32_t offset; /* Offset in flash to hash */ uint32_t size; /* Number of bytes to hash */ uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ -}; +} __ec_align4; -struct __ec_align4 ec_response_vboot_hash { +struct ec_response_vboot_hash { uint8_t status; /* enum ec_vboot_hash_status */ uint8_t hash_type; /* enum ec_vboot_hash_type */ uint8_t digest_size; /* Size of hash digest in bytes */ @@ -2121,7 +2248,7 @@ uint32_t offset; /* Offset in flash which was hashed */ uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ -}; +} __ec_align4; enum ec_vboot_hash_cmd { EC_VBOOT_HASH_GET = 0, /* Get current hash status */ @@ -2149,8 +2276,10 @@ #define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd #define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc -/* 'RW' is vague if there are multiple RW images; we mean the active one, - * so the old constant is deprecated */ +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ #define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE /*****************************************************************************/ @@ -2273,6 +2402,15 @@ */ MOTIONSENSE_CMD_SPOOF = 16, + /* Set lid angle for tablet mode detection. */ + MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, + + /* + * Sensor Scale command is a setter/getter command for the calibration + * scale. + */ + MOTIONSENSE_CMD_SENSOR_SCALE = 18, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2316,6 +2454,10 @@ MOTIONSENSE_CHIP_LIS2DH = 13, MOTIONSENSE_CHIP_LSM6DSM = 14, MOTIONSENSE_CHIP_LIS2DE = 15, + MOTIONSENSE_CHIP_LIS2MDL = 16, + MOTIONSENSE_CHIP_LSM6DS3 = 17, + MOTIONSENSE_CHIP_LSM6DSO = 18, + MOTIONSENSE_CHIP_LNG2DM = 19, MOTIONSENSE_CHIP_MAX, }; @@ -2328,7 +2470,7 @@ MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; -struct __ec_todo_packed ec_response_motion_sensor_data { +struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; /* sensor number the data comes from */ @@ -2346,10 +2488,10 @@ int16_t add_info[2]; }; }; -}; +} __ec_todo_packed; /* Note: used in ec_response_get_next_data */ -struct __ec_todo_packed ec_response_motion_sense_fifo_info { +struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ uint16_t size; /* Amount of space used in the fifo */ @@ -2362,12 +2504,12 @@ uint16_t total_lost; /* Lost events since the last fifo_info, per sensors */ uint16_t lost[0]; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sense_fifo_data { +struct ec_response_motion_sense_fifo_data { uint32_t number_data; struct ec_response_motion_sensor_data data[0]; -}; +} __ec_todo_packed; /* List supported activity recognition */ enum motionsensor_activity { @@ -2377,13 +2519,13 @@ MOTIONSENSE_ACTIVITY_ORIENTATION = 3, }; -struct __ec_todo_unpacked ec_motion_sense_activity { +struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; uint16_t parameters[3]; /* activity dependent parameters */ -}; +} __ec_todo_unpacked; /* Module flag masks used for the dump sub-command. */ #define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) @@ -2399,6 +2541,7 @@ #define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) #define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) #define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) +#define MOTIONSENSE_SENSOR_FLAG_ODR (1<<4) /* * Send this value for the data element to only perform a read. If you @@ -2411,7 +2554,10 @@ /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ /* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET 1 +#define MOTION_SENSE_SET_OFFSET (1 << 0) + +/* Default Scale value, factor 1. */ +#define MOTION_SENSE_DEFAULT_SCALE (1 << 15) #define LID_ANGLE_UNRELIABLE 500 @@ -2429,7 +2575,7 @@ MOTIONSENSE_SPOOF_MODE_QUERY, }; -struct __ec_todo_packed ec_params_motion_sense { +struct ec_params_motion_sense { uint8_t cmd; union { /* Used for MOTIONSENSE_CMD_DUMP */ @@ -2452,8 +2598,10 @@ int16_t data; } kb_wake_angle; - /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA - * and MOTIONSENSE_CMD_PERFORM_CALIB. */ + /* + * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + * and MOTIONSENSE_CMD_PERFORM_CALIB. + */ struct __ec_todo_unpacked { uint8_t sensor_num; } info, info_3, data, fifo_flush, perform_calib, @@ -2504,6 +2652,36 @@ int16_t offset[3]; } sensor_offset; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_packed { + uint8_t sensor_num; + + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Scale for calibration: + * By default scale is 1, it is encoded on 16bits: + * 1 = 1 << 15 + * ~2 = 0xFFFF + * ~0 = 0. + */ + uint16_t scale[3]; + } sensor_scale; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -2543,10 +2721,28 @@ /* Individual component values to spoof. */ int16_t components[3]; } spoof; - }; -}; -struct __ec_todo_packed ec_response_motion_sense { + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + int16_t lid_angle; + + /* + * Hysteresis degree to prevent fluctuations between + * clamshell and tablet mode if lid angle keeps + * changing around the threshold. Lid motion driver will + * use lid_angle + hys_degree to trigger tablet mode and + * lid_angle - hys_degree to trigger clamshell mode. + */ + int16_t hys_degree; + } tablet_mode_threshold; + }; +} __ec_todo_packed; + +struct ec_response_motion_sense { union { /* Used for MOTIONSENSE_CMD_DUMP */ struct __ec_todo_unpacked { @@ -2612,12 +2808,21 @@ } ec_rate, sensor_odr, sensor_range, kb_wake_angle, fifo_int_enable, spoof; - /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + /* + * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, + * PERFORM_CALIB. + */ struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_unpacked { + int16_t temp; + uint16_t scale[3]; + } sensor_scale; + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; struct ec_response_motion_sense_fifo_data fifo_read; @@ -2638,8 +2843,21 @@ */ uint16_t value; } lid_angle; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + uint16_t lid_angle; + + /* Hysteresis degree. */ + uint16_t hys_degree; + } tablet_mode_threshold; + }; -}; +} __ec_todo_packed; /*****************************************************************************/ /* Force lid open command */ @@ -2647,9 +2865,9 @@ /* Make lid event always open */ #define EC_CMD_FORCE_LID_OPEN 0x002C -struct __ec_align1 ec_params_force_lid_open { +struct ec_params_force_lid_open { uint8_t enabled; -}; +} __ec_align1; /*****************************************************************************/ /* Configure the behavior of the power button */ @@ -2660,10 +2878,10 @@ EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), }; -struct __ec_align1 ec_params_config_power_button { +struct ec_params_config_power_button { /* See enum ec_config_power_button_flags */ uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB charging control commands */ @@ -2671,10 +2889,11 @@ /* Set USB port charging mode */ #define EC_CMD_USB_CHARGE_SET_MODE 0x0030 -struct __ec_align1 ec_params_usb_charge_set_mode { +struct ec_params_usb_charge_set_mode { uint8_t usb_port_id; - uint8_t mode; -}; + uint8_t mode:7; + uint8_t inhibit_charge:1; +} __ec_align1; /*****************************************************************************/ /* Persistent storage for host */ @@ -2685,12 +2904,12 @@ /* Get persistent storage info */ #define EC_CMD_PSTORE_INFO 0x0040 -struct __ec_align4 ec_response_pstore_info { +struct ec_response_pstore_info { /* Persistent storage size, in bytes */ uint32_t pstore_size; /* Access size; read/write offset and size must be a multiple of this */ uint32_t access_size; -}; +} __ec_align4; /* * Read persistent storage @@ -2699,31 +2918,31 @@ */ #define EC_CMD_PSTORE_READ 0x0041 -struct __ec_align4 ec_params_pstore_read { +struct ec_params_pstore_read { uint32_t offset; /* Byte offset to read */ uint32_t size; /* Size to read in bytes */ -}; +} __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 -struct __ec_align4 ec_params_pstore_write { +struct ec_params_pstore_write { uint32_t offset; /* Byte offset to write */ uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; -}; +} __ec_align4; /*****************************************************************************/ /* Real-time clock */ /* RTC params and response structures */ -struct __ec_align4 ec_params_rtc { +struct ec_params_rtc { uint32_t time; -}; +} __ec_align4; -struct __ec_align4 ec_response_rtc { +struct ec_response_rtc { uint32_t time; -}; +} __ec_align4; /* These use ec_response_rtc */ #define EC_CMD_RTC_GET_VALUE 0x0044 @@ -2751,7 +2970,7 @@ EC_PORT80_READ_BUFFER, }; -struct __ec_todo_packed ec_params_port80_read { +struct ec_params_port80_read { uint16_t subcmd; union { struct __ec_todo_unpacked { @@ -2759,9 +2978,9 @@ uint32_t num_entries; } read_buffer; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_port80_read { +struct ec_response_port80_read { union { struct __ec_todo_unpacked { uint32_t writes; @@ -2772,11 +2991,11 @@ uint16_t codes[EC_PORT80_SIZE_MAX]; } data; }; -}; +} __ec_todo_packed; -struct __ec_align2 ec_response_port80_last_boot { +struct ec_response_port80_last_boot { uint16_t code; -}; +} __ec_align2; /*****************************************************************************/ /* Temporary secure storage for host verified boot use */ @@ -2789,12 +3008,12 @@ /* Get persistent storage info */ #define EC_CMD_VSTORE_INFO 0x0049 -struct __ec_align_size1 ec_response_vstore_info { +struct ec_response_vstore_info { /* Indicates which slots are locked */ uint32_t slot_locked; /* Total number of slots available */ uint8_t slot_count; -}; +} __ec_align_size1; /* * Read temporary secure storage @@ -2803,23 +3022,23 @@ */ #define EC_CMD_VSTORE_READ 0x004A -struct __ec_align1 ec_params_vstore_read { +struct ec_params_vstore_read { uint8_t slot; /* Slot to read from */ -}; +} __ec_align1; -struct __ec_align1 ec_response_vstore_read { +struct ec_response_vstore_read { uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /* * Write temporary secure storage and lock it. */ #define EC_CMD_VSTORE_WRITE 0x004B -struct __ec_align1 ec_params_vstore_write { +struct ec_params_vstore_write { uint8_t slot; /* Slot to write to */ uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /*****************************************************************************/ /* Thermal engine commands. Note that there are two implementations. We'll @@ -2836,21 +3055,21 @@ */ /* Version 0 - set */ -struct __ec_align2 ec_params_thermal_set_threshold { +struct ec_params_thermal_set_threshold { uint8_t sensor_type; uint8_t threshold_id; uint16_t value; -}; +} __ec_align2; /* Version 0 - get */ -struct __ec_align1 ec_params_thermal_get_threshold { +struct ec_params_thermal_get_threshold { uint8_t sensor_type; uint8_t threshold_id; -}; +} __ec_align1; -struct __ec_align2 ec_response_thermal_get_threshold { +struct ec_response_thermal_get_threshold { uint16_t value; -}; +} __ec_align2; /* The version 1 structs are visible. */ @@ -2884,25 +3103,25 @@ * Note that this structure is a sub-structure of * ec_params_thermal_set_threshold_v1, but maintains its alignment there. */ -struct __ec_align4 ec_thermal_config { +struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ uint32_t temp_fan_off; /* no active cooling needed */ uint32_t temp_fan_max; /* max active cooling needed */ -}; +} __ec_align4; /* Version 1 - get config for one sensor. */ -struct __ec_align4 ec_params_thermal_get_threshold_v1 { +struct ec_params_thermal_get_threshold_v1 { uint32_t sensor_num; -}; +} __ec_align4; /* This returns a struct ec_thermal_config */ /* Version 1 - set config for one sensor. * Use read-modify-write for best results! */ -struct __ec_align4 ec_params_thermal_set_threshold_v1 { +struct ec_params_thermal_set_threshold_v1 { uint32_t sensor_num; struct ec_thermal_config cfg; -}; +} __ec_align4; /* This returns no data */ /****************************************************************************/ @@ -2911,9 +3130,9 @@ #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 /* Version 1 of input params */ -struct __ec_align1 ec_params_auto_fan_ctrl_v1 { +struct ec_params_auto_fan_ctrl_v1 { uint8_t fan_idx; -}; +} __ec_align1; /* Get/Set TMP006 calibration data */ #define EC_CMD_TMP006_GET_CALIBRATION 0x0053 @@ -2929,55 +3148,55 @@ */ /* This is the same struct for both v0 and v1. */ -struct __ec_align1 ec_params_tmp006_get_calibration { +struct ec_params_tmp006_get_calibration { uint8_t index; -}; +} __ec_align1; /* Version 0 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v0 { +struct ec_response_tmp006_get_calibration_v0 { float s0; float b0; float b1; float b2; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v0 { +struct ec_params_tmp006_set_calibration_v0 { uint8_t index; uint8_t reserved[3]; float s0; float b0; float b1; float b2; -}; +} __ec_align4; /* Version 1 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v1 { +struct ec_response_tmp006_get_calibration_v1 { uint8_t algorithm; uint8_t num_params; uint8_t reserved[2]; float val[0]; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v1 { +struct ec_params_tmp006_set_calibration_v1 { uint8_t index; uint8_t algorithm; uint8_t num_params; uint8_t reserved; float val[0]; -}; +} __ec_align4; /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 -struct __ec_align1 ec_params_tmp006_get_raw { +struct ec_params_tmp006_get_raw { uint8_t index; -}; +} __ec_align1; -struct __ec_align4 ec_response_tmp006_get_raw { +struct ec_response_tmp006_get_raw { int32_t t; /* In 1/100 K */ int32_t v; /* In nV */ -}; +} __ec_align4; /*****************************************************************************/ /* MKBP - Matrix KeyBoard Protocol */ @@ -2999,17 +3218,17 @@ */ #define EC_CMD_MKBP_INFO 0x0061 -struct __ec_align_size1 ec_response_mkbp_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; /* Formerly "switches", which was 0. */ uint8_t reserved; -}; +} __ec_align_size1; -struct __ec_align1 ec_params_mkbp_info { +struct ec_params_mkbp_info { uint8_t info_type; uint8_t event_type; -}; +} __ec_align1; enum ec_mkbp_info_type { /* @@ -3053,17 +3272,17 @@ /* Simulate key press */ #define EC_CMD_MKBP_SIMULATE_KEY 0x0062 -struct __ec_align1 ec_params_mkbp_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; -}; +} __ec_align1; #define EC_CMD_GET_KEYBOARD_ID 0x0063 -struct __ec_align4 ec_response_keyboard_id { +struct ec_response_keyboard_id { uint32_t keyboard_id; -}; +} __ec_align4; enum keyboard_id { KEYBOARD_ID_UNSUPPORTED = 0, @@ -3095,7 +3314,7 @@ * Note that this is used as a sub-structure of * ec_{params/response}_mkbp_get_config. */ -struct __ec_align_size1 ec_mkbp_config { +struct ec_mkbp_config { uint32_t valid_mask; /* valid fields */ uint8_t flags; /* some flags (enum mkbp_config_flags) */ uint8_t valid_flags; /* which flags are valid */ @@ -3114,15 +3333,15 @@ uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_params_mkbp_set_config { +struct ec_params_mkbp_set_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_response_mkbp_get_config { +struct ec_response_mkbp_get_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; /* Run the key scan emulation */ #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 @@ -3143,11 +3362,11 @@ EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, }; -struct __ec_align1 ec_collect_item { +struct ec_collect_item { uint8_t flags; /* some flags (enum ec_collect_flags) */ -}; +} __ec_align1; -struct __ec_todo_packed ec_params_keyscan_seq_ctrl { +struct ec_params_keyscan_seq_ctrl { uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { @@ -3169,9 +3388,9 @@ uint8_t num_items; /* Number of items to return */ } collect; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_result_keyscan_seq_ctrl { +struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { uint8_t num_items; /* Number of items */ @@ -3179,7 +3398,7 @@ struct ec_collect_item item[0]; } collect; }; -}; +} __ec_todo_packed; /* * Get the next pending MKBP event. @@ -3188,6 +3407,17 @@ */ #define EC_CMD_GET_NEXT_EVENT 0x0067 +#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 + +/* + * We use the most significant bit of the event type to indicate to the host + * that the EC has more MKBP events available to provide. + */ +#define EC_MKBP_HAS_MORE_EVENTS (1 << EC_MKBP_HAS_MORE_EVENTS_SHIFT) + +/* The mask to apply to get the raw event type */ +#define EC_MKBP_EVENT_TYPE_MASK ((1 << EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) + enum ec_mkbp_event { /* Keyboard matrix changed. The event data is the new matrix state. */ EC_MKBP_EVENT_KEY_MATRIX = 0, @@ -3228,6 +3458,7 @@ /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; +BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); union __ec_align_offset1 ec_response_get_next_data { uint8_t key_matrix[13]; @@ -3280,18 +3511,19 @@ uint8_t cec_message[16]; }; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); -struct __ec_align1 ec_response_get_next_event { +struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data data; -}; +} __ec_align1; -struct __ec_align1 ec_response_get_next_event_v1 { +struct ec_response_get_next_event_v1 { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data_v1 data; -}; +} __ec_align1; /* Bit indices for buttons and switches.*/ /* Buttons */ @@ -3303,13 +3535,14 @@ /* Switches */ #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 -struct __ec_align2 ec_response_keyboard_factory_test { +struct ec_response_keyboard_factory_test { uint16_t shorted; /* Keyboard pins are shorted */ -}; +} __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) @@ -3337,6 +3570,7 @@ /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ #define EC_MKBP_FP_ERR_MATCH_NO 0 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 #define EC_MKBP_FP_ERR_MATCH_YES 1 @@ -3350,14 +3584,14 @@ /* Read temperature sensor info */ #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 -struct __ec_align1 ec_params_temp_sensor_get_info { +struct ec_params_temp_sensor_get_info { uint8_t id; -}; +} __ec_align1; -struct __ec_align1 ec_response_temp_sensor_get_info { +struct ec_response_temp_sensor_get_info { char sensor_name[32]; uint8_t sensor_type; -}; +} __ec_align1; /*****************************************************************************/ @@ -3376,13 +3610,13 @@ * Host event mask params and response structures, shared by all of the host * event commands below. */ -struct __ec_align4 ec_params_host_event_mask { +struct ec_params_host_event_mask { uint32_t mask; -}; +} __ec_align4; -struct __ec_align4 ec_response_host_event_mask { +struct ec_response_host_event_mask { uint32_t mask; -}; +} __ec_align4; /* These all use ec_response_host_event_mask */ #define EC_CMD_HOST_EVENT_GET_B 0x0087 @@ -3402,7 +3636,7 @@ * of BIOS/OS to program host events and masks */ -struct __ec_align4 ec_params_host_event { +struct ec_params_host_event { /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -3418,18 +3652,18 @@ /* Value to be used in case of set operations. */ uint64_t value; -}; +} __ec_align4; /* * Response structure returned by EC_CMD_HOST_EVENT. * Update the value on a GET request. Set to 0 on GET/CLEAR */ -struct __ec_align4 ec_response_host_event { +struct ec_response_host_event { /* Mask value in case of get operation */ uint64_t value; -}; +} __ec_align4; enum ec_host_event_action { /* @@ -3483,21 +3717,21 @@ /* Enable/disable LCD backlight */ #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 -struct __ec_align1 ec_params_switch_enable_backlight { +struct ec_params_switch_enable_backlight { uint8_t enabled; -}; +} __ec_align1; /* Enable/disable WLAN/Bluetooth */ #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 #define EC_VER_SWITCH_ENABLE_WIRELESS 1 /* Version 0 params; no response */ -struct __ec_align1 ec_params_switch_enable_wireless_v0 { +struct ec_params_switch_enable_wireless_v0 { uint8_t enabled; -}; +} __ec_align1; /* Version 1 params */ -struct __ec_align1 ec_params_switch_enable_wireless_v1 { +struct ec_params_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; @@ -3513,16 +3747,16 @@ /* Which flags to copy from suspend_flags */ uint8_t suspend_mask; -}; +} __ec_align1; /* Version 1 response */ -struct __ec_align1 ec_response_switch_enable_wireless_v1 { +struct ec_response_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; /* Flags to leave enabled in S3 */ uint8_t suspend_flags; -}; +} __ec_align1; /*****************************************************************************/ /* GPIO commands. Only available on EC if write protect has been disabled. */ @@ -3530,25 +3764,25 @@ /* Set GPIO output value */ #define EC_CMD_GPIO_SET 0x0092 -struct __ec_align1 ec_params_gpio_set { +struct ec_params_gpio_set { char name[32]; uint8_t val; -}; +} __ec_align1; /* Get GPIO value */ #define EC_CMD_GPIO_GET 0x0093 /* Version 0 of input params and response */ -struct __ec_align1 ec_params_gpio_get { +struct ec_params_gpio_get { char name[32]; -}; +} __ec_align1; -struct __ec_align1 ec_response_gpio_get { +struct ec_response_gpio_get { uint8_t val; -}; +} __ec_align1; /* Version 1 of input params and response */ -struct __ec_align1 ec_params_gpio_get_v1 { +struct ec_params_gpio_get_v1 { uint8_t subcmd; union { struct __ec_align1 { @@ -3558,9 +3792,9 @@ uint8_t index; } get_info; }; -}; +} __ec_align1; -struct __ec_todo_packed ec_response_gpio_get_v1 { +struct ec_response_gpio_get_v1 { union { struct __ec_align1 { uint8_t val; @@ -3571,7 +3805,7 @@ uint32_t flags; } get_info; }; -}; +} __ec_todo_packed; enum gpio_get_subcmd { EC_GPIO_GET_BY_NAME = 0, @@ -3592,27 +3826,27 @@ /* Read I2C bus */ #define EC_CMD_I2C_READ 0x0094 -struct __ec_align_size1 ec_params_i2c_read { +struct ec_params_i2c_read { uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; -struct __ec_align2 ec_response_i2c_read { +struct ec_response_i2c_read { uint16_t data; -}; +} __ec_align2; /* Write I2C bus */ #define EC_CMD_I2C_WRITE 0x0095 -struct __ec_align_size1 ec_params_i2c_write { +struct ec_params_i2c_write { uint16_t data; uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; /*****************************************************************************/ /* Charge state commands. Only available when flash write protect unlocked. */ @@ -3629,12 +3863,11 @@ CHARGE_CONTROL_DISCHARGE, }; -struct __ec_align4 ec_params_charge_control { +struct ec_params_charge_control { uint32_t mode; /* enum charge_control_mode */ -}; +} __ec_align4; /*****************************************************************************/ -/* Console commands. Only available when flash write protect is unlocked. */ /* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ #define EC_CMD_CONSOLE_SNAPSHOT 0x0097 @@ -3658,9 +3891,9 @@ CONSOLE_READ_RECENT }; -struct __ec_align1 ec_params_console_read_v1 { +struct ec_params_console_read_v1 { uint8_t subcmd; /* enum ec_console_read_subcmd */ -}; +} __ec_align1; /*****************************************************************************/ @@ -3675,9 +3908,9 @@ #define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) -struct __ec_align1 ec_params_battery_cutoff { +struct ec_params_battery_cutoff { uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB port mux control. */ @@ -3687,9 +3920,9 @@ */ #define EC_CMD_USB_MUX 0x009A -struct __ec_align1 ec_params_usb_mux { +struct ec_params_usb_mux { uint8_t mux; -}; +} __ec_align1; /*****************************************************************************/ /* LDOs / FETs control. */ @@ -3704,23 +3937,23 @@ */ #define EC_CMD_LDO_SET 0x009B -struct __ec_align1 ec_params_ldo_set { +struct ec_params_ldo_set { uint8_t index; uint8_t state; -}; +} __ec_align1; /* * Get LDO state. */ #define EC_CMD_LDO_GET 0x009C -struct __ec_align1 ec_params_ldo_get { +struct ec_params_ldo_get { uint8_t index; -}; +} __ec_align1; -struct __ec_align1 ec_response_ldo_get { +struct ec_response_ldo_get { uint8_t state; -}; +} __ec_align1; /*****************************************************************************/ /* Power info. */ @@ -3730,13 +3963,13 @@ */ #define EC_CMD_POWER_INFO 0x009D -struct __ec_align4 ec_response_power_info { +struct ec_response_power_info { uint32_t usb_dev_type; uint16_t voltage_ac; uint16_t voltage_system; uint16_t current_system; uint16_t usb_current_limit; -}; +} __ec_align4; /*****************************************************************************/ /* I2C passthru command */ @@ -3755,23 +3988,23 @@ /* Any error */ #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) -struct __ec_align2 ec_params_i2c_passthru_msg { +struct ec_params_i2c_passthru_msg { uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ uint16_t len; /* Number of bytes to read or write */ -}; +} __ec_align2; -struct __ec_align2 ec_params_i2c_passthru { +struct ec_params_i2c_passthru { uint8_t port; /* I2C port number */ uint8_t num_msgs; /* Number of messages */ struct ec_params_i2c_passthru_msg msg[]; /* Data to write for all messages is concatenated here */ -}; +} __ec_align2; -struct __ec_align1 ec_response_i2c_passthru { +struct ec_response_i2c_passthru { uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ uint8_t num_msgs; /* Number of messages processed */ uint8_t data[]; /* Data read by messages concatenated here */ -}; +} __ec_align1; /*****************************************************************************/ /* Power button hang detect */ @@ -3817,7 +4050,7 @@ */ #define EC_HANG_STOP_NOW (1 << 31) -struct __ec_align4 ec_params_hang_detect { +struct ec_params_hang_detect { /* Flags; see EC_HANG_* */ uint32_t flags; @@ -3826,7 +4059,7 @@ /* Timeout in msec before generating warm reboot, if enabled */ uint16_t warm_reboot_timeout_msec; -}; +} __ec_align4; /*****************************************************************************/ /* Commands for battery charging */ @@ -3881,7 +4114,7 @@ /* Other custom param ranges go here... */ }; -struct __ec_todo_packed ec_params_charge_state { +struct ec_params_charge_state { uint8_t cmd; /* enum charge_state_command */ union { /* get_state has no args */ @@ -3895,9 +4128,9 @@ uint32_t value; /* value to set */ } set_param; }; -}; +} __ec_todo_packed; -struct __ec_align4 ec_response_charge_state { +struct ec_response_charge_state { union { struct __ec_align4 { int ac; @@ -3913,7 +4146,7 @@ /* set_param returns no args */ }; -}; +} __ec_align4; /* @@ -3921,9 +4154,9 @@ */ #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 -struct __ec_align4 ec_params_current_limit { +struct ec_params_current_limit { uint32_t limit; /* in mA */ -}; +} __ec_align4; /* * Set maximum external voltage / current. @@ -3931,10 +4164,10 @@ #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 /* Command v0 is used only on Spring and is obsolete + unsupported */ -struct __ec_align2 ec_params_external_power_limit_v1 { +struct ec_params_external_power_limit_v1 { uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ -}; +} __ec_align2; #define EC_POWER_LIMIT_NONE 0xffff @@ -3943,10 +4176,10 @@ */ #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 -struct __ec_align2 ec_params_dedicated_charger_limit { +struct ec_params_dedicated_charger_limit { uint16_t current_lim; /* in mA */ uint16_t voltage_lim; /* in mV */ -}; +} __ec_align2; /*****************************************************************************/ /* Hibernate/Deep Sleep Commands */ @@ -3954,15 +4187,15 @@ /* Set the delay before going into hibernation. */ #define EC_CMD_HIBERNATION_DELAY 0x00A8 -struct __ec_align4 ec_params_hibernation_delay { +struct ec_params_hibernation_delay { /* * Seconds to wait in G3 before hibernate. Pass in 0 to read the * current settings without changing them. */ uint32_t seconds; -}; +} __ec_align4; -struct __ec_align4 ec_response_hibernation_delay { +struct ec_response_hibernation_delay { /* * The current time in seconds in which the system has been in the G3 * state. This value is reset if the EC transitions out of G3. @@ -3980,7 +4213,7 @@ * hibernating. */ uint32_t hibernate_delay; -}; +} __ec_align4; /* Inform the EC when entering a sleep state */ #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 @@ -3994,9 +4227,9 @@ HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; -struct __ec_align1 ec_params_host_sleep_event { +struct ec_params_host_sleep_event { uint8_t sleep_event; -}; +} __ec_align1; /*****************************************************************************/ /* Device events */ @@ -4019,14 +4252,14 @@ #define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) -struct __ec_align_size1 ec_params_device_event { +struct ec_params_device_event { uint32_t event_mask; uint8_t param; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_device_event { +struct ec_response_device_event { uint32_t event_mask; -}; +} __ec_align4; /*****************************************************************************/ /* Smart battery pass-through */ @@ -4041,27 +4274,27 @@ #define EC_CMD_SB_READ_BLOCK 0x00B2 #define EC_CMD_SB_WRITE_BLOCK 0x00B3 -struct __ec_align1 ec_params_sb_rd { +struct ec_params_sb_rd { uint8_t reg; -}; +} __ec_align1; -struct __ec_align2 ec_response_sb_rd_word { +struct ec_response_sb_rd_word { uint16_t value; -}; +} __ec_align2; -struct __ec_align1 ec_params_sb_wr_word { +struct ec_params_sb_wr_word { uint8_t reg; uint16_t value; -}; +} __ec_align1; -struct __ec_align1 ec_response_sb_rd_block { +struct ec_response_sb_rd_block { uint8_t data[32]; -}; +} __ec_align1; -struct __ec_align1 ec_params_sb_wr_block { +struct ec_params_sb_wr_block { uint8_t reg; uint16_t data[32]; -}; +} __ec_align1; /*****************************************************************************/ /* Battery vendor parameters @@ -4079,15 +4312,15 @@ BATTERY_VENDOR_PARAM_MODE_SET, }; -struct __ec_align_size1 ec_params_battery_vendor_param { +struct ec_params_battery_vendor_param { uint32_t param; uint32_t value; uint8_t mode; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_vendor_param { +struct ec_response_battery_vendor_param { uint32_t value; -}; +} __ec_align4; /*****************************************************************************/ /* @@ -4110,12 +4343,12 @@ #define SB_FW_UPDATE_CMD_STATUS_SIZE 2 #define SB_FW_UPDATE_CMD_INFO_SIZE 8 -struct __ec_align4 ec_sb_fw_update_header { +struct ec_sb_fw_update_header { uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ uint16_t fw_id; /* firmware id */ -}; +} __ec_align4; -struct __ec_align4 ec_params_sb_fw_update { +struct ec_params_sb_fw_update { struct ec_sb_fw_update_header hdr; union { /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ @@ -4131,9 +4364,9 @@ uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; } write; }; -}; +} __ec_align4; -struct __ec_align1 ec_response_sb_fw_update { +struct ec_response_sb_fw_update { union { /* EC_SB_FW_UPDATE_INFO = 0x1 */ struct __ec_align1 { @@ -4145,7 +4378,7 @@ uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; } status; }; -}; +} __ec_align1; /* * Entering Verified Boot Mode Command @@ -4154,9 +4387,9 @@ */ #define EC_CMD_ENTERING_MODE 0x00B6 -struct __ec_align4 ec_params_entering_mode { +struct ec_params_entering_mode { int vboot_mode; -}; +} __ec_align4; #define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 @@ -4174,19 +4407,19 @@ EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, }; -struct __ec_align1 ec_params_i2c_passthru_protect { +struct ec_params_i2c_passthru_protect { uint8_t subcmd; uint8_t port; /* I2C port number */ -}; +} __ec_align1; -struct __ec_align1 ec_response_i2c_passthru_protect { +struct ec_response_i2c_passthru_protect { uint8_t status; /* Status flags (0: unlocked, 1: locked) */ -}; +} __ec_align1; /*****************************************************************************/ /* - * HDMI CEC commands + * HDMI CEC commands * * These commands are for sending and receiving message via HDMI CEC */ @@ -4196,30 +4429,53 @@ /* CEC message from the AP to be written on the CEC bus */ #define EC_CMD_CEC_WRITE_MSG 0x00B8 -/* Message to write to the CEC bus */ -struct __ec_align1 ec_params_cec_write { +/** + * struct ec_params_cec_write - Message to write to the CEC bus + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write { uint8_t msg[MAX_CEC_MSG_LEN]; -}; +} __ec_align1; /* Set various CEC parameters */ #define EC_CMD_CEC_SET 0x00BA -struct __ec_align1 ec_params_cec_set { +/** + * struct ec_params_cec_set - CEC parameters set + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC + * or 1 to enable CEC functionality, in case cmd is + * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical + * address between 0 and 15 or 0xff to unregister + */ +struct ec_params_cec_set { uint8_t cmd; /* enum cec_command */ uint8_t val; -}; +} __ec_align1; /* Read various CEC parameters */ #define EC_CMD_CEC_GET 0x00BB -struct __ec_align1 ec_params_cec_get { +/** + * struct ec_params_cec_get - CEC parameters get + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + */ +struct ec_params_cec_get { uint8_t cmd; /* enum cec_command */ -}; +} __ec_align1; -struct __ec_align1 ec_response_cec_get { +/** + * struct ec_response_cec_get - CEC parameters get response + * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is + * disabled or 1 if CEC functionality is enabled, + * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the + * configured logical address between 0 and 15 or 0xff if unregistered + */ +struct ec_response_cec_get { uint8_t val; -}; +} __ec_align1; +/* CEC parameters command */ enum cec_command { /* CEC reading, writing and events enable */ CEC_CMD_ENABLE, @@ -4236,6 +4492,96 @@ }; /*****************************************************************************/ + +/* Commands for I2S recording on audio codec. */ + +#define EC_CMD_CODEC_I2S 0x00BC +#define EC_WOV_I2S_SAMPLE_RATE 48000 + +enum ec_codec_i2s_subcmd { + EC_CODEC_SET_SAMPLE_DEPTH = 0x0, + EC_CODEC_SET_GAIN = 0x1, + EC_CODEC_GET_GAIN = 0x2, + EC_CODEC_I2S_ENABLE = 0x3, + EC_CODEC_I2S_SET_CONFIG = 0x4, + EC_CODEC_I2S_SET_TDM_CONFIG = 0x5, + EC_CODEC_I2S_SET_BCLK = 0x6, + EC_CODEC_I2S_SUBCMD_COUNT = 0x7, +}; + +enum ec_sample_depth_value { + EC_CODEC_SAMPLE_DEPTH_16 = 0, + EC_CODEC_SAMPLE_DEPTH_24 = 1, +}; + +enum ec_i2s_config { + EC_DAI_FMT_I2S = 0, + EC_DAI_FMT_RIGHT_J = 1, + EC_DAI_FMT_LEFT_J = 2, + EC_DAI_FMT_PCM_A = 3, + EC_DAI_FMT_PCM_B = 4, + EC_DAI_FMT_PCM_TDM = 5, +}; + +/* + * For subcommand EC_CODEC_GET_GAIN. + */ +struct __ec_align1 ec_codec_i2s_gain { + uint8_t left; + uint8_t right; +}; + +struct __ec_todo_unpacked ec_param_codec_i2s_tdm { + int16_t ch0_delay; /* 0 to 496 */ + int16_t ch1_delay; /* -1 to 496 */ + uint8_t adjacent_to_ch0; + uint8_t adjacent_to_ch1; +}; + +struct __ec_todo_packed ec_param_codec_i2s { + /* enum ec_codec_i2s_subcmd */ + uint8_t cmd; + union { + /* + * EC_CODEC_SET_SAMPLE_DEPTH + * Value should be one of ec_sample_depth_value. + */ + uint8_t depth; + + /* + * EC_CODEC_SET_GAIN + * Value should be 0~43 for both channels. + */ + struct ec_codec_i2s_gain gain; + + /* + * EC_CODEC_I2S_ENABLE + * 1 to enable, 0 to disable. + */ + uint8_t i2s_enable; + + /* + * EC_CODEC_I2S_SET_CONFIG + * Value should be one of ec_i2s_config. + */ + uint8_t i2s_config; + + /* + * EC_CODEC_I2S_SET_TDM_CONFIG + * Value should be one of ec_i2s_config. + */ + struct ec_param_codec_i2s_tdm tdm_param; + + /* + * EC_CODEC_I2S_SET_BCLK + */ + uint32_t bclk; + }; +}; + + +/*****************************************************************************/ + /* System commands */ /* @@ -4261,10 +4607,10 @@ #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ #define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ -struct __ec_align1 ec_params_reboot_ec { +struct ec_params_reboot_ec { uint8_t cmd; /* enum ec_reboot_cmd */ uint8_t flags; /* See EC_REBOOT_FLAG_* */ -}; +} __ec_align1; /* * Get information on last EC panic. @@ -4335,11 +4681,11 @@ /* Status of EC being sent to PD */ #define EC_STATUS_HIBERNATING (1 << 0) -struct __ec_align1 ec_params_pd_status { +struct ec_params_pd_status { uint8_t status; /* EC status */ int8_t batt_soc; /* battery state of charge */ uint8_t charge_state; /* charging state (from enum pd_charge_state) */ -}; +} __ec_align1; /* Status of PD being sent back to EC */ #define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ @@ -4352,11 +4698,11 @@ #define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ PD_STATUS_TCPC_ALERT_1 | \ PD_STATUS_HOST_EVENT) -struct __ec_align_size1 ec_response_pd_status { +struct ec_response_pd_status { uint32_t curr_lim_ma; /* input current limit */ uint16_t status; /* PD MCU status */ int8_t active_charge_port; /* active charging port */ -}; +} __ec_align_size1; /* AP to PD MCU host event status command, cleared on read */ #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 @@ -4366,9 +4712,9 @@ #define PD_EVENT_POWER_CHANGE (1 << 1) #define PD_EVENT_IDENTITY_RECEIVED (1 << 2) #define PD_EVENT_DATA_SWAP (1 << 3) -struct __ec_align4 ec_response_host_event_status { +struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ -}; +} __ec_align4; /* Set USB type-C port role and muxes */ #define EC_CMD_USB_PD_CONTROL 0x0101 @@ -4401,12 +4747,12 @@ USB_PD_CTRL_SWAP_COUNT }; -struct __ec_align1 ec_params_usb_pd_control { +struct ec_params_usb_pd_control { uint8_t port; uint8_t role; uint8_t mux; uint8_t swap; -}; +} __ec_align1; #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ @@ -4420,35 +4766,51 @@ #define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ #define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ -struct __ec_align1 ec_response_usb_pd_control { +struct ec_response_usb_pd_control { uint8_t enabled; uint8_t role; uint8_t polarity; uint8_t state; -}; +} __ec_align1; -struct __ec_align1 ec_response_usb_pd_control_v1 { +struct ec_response_usb_pd_control_v1 { uint8_t enabled; uint8_t role; uint8_t polarity; char state[32]; -}; +} __ec_align1; + +/* Values representing usbc PD CC state */ +#define USBC_PD_CC_NONE 0 /* No accessory connected */ +#define USBC_PD_CC_NO_UFP 1 /* No UFP accessory connected */ +#define USBC_PD_CC_AUDIO_ACC 2 /* Audio accessory connected */ +#define USBC_PD_CC_DEBUG_ACC 3 /* Debug accessory connected */ +#define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */ +#define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */ + +struct ec_response_usb_pd_control_v2 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; + uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */ +} __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 /* Maximum number of PD ports on a device, num_ports will be <= this */ #define EC_USB_PD_MAX_PORTS 8 -struct __ec_align1 ec_response_usb_pd_ports { +struct ec_response_usb_pd_ports { uint8_t num_ports; -}; +} __ec_align1; #define EC_CMD_USB_PD_POWER_INFO 0x0103 #define PD_POWER_CHARGING_PORT 0xff -struct __ec_align1 ec_params_usb_pd_power_info { +struct ec_params_usb_pd_power_info { uint8_t port; -}; +} __ec_align1; enum usb_chg_type { USB_CHG_TYPE_NONE, @@ -4470,21 +4832,21 @@ USB_PD_PORT_POWER_SINK_NOT_CHARGING, }; -struct __ec_align2 usb_chg_measures { +struct usb_chg_measures { uint16_t voltage_max; uint16_t voltage_now; uint16_t current_max; uint16_t current_lim; -}; +} __ec_align2; -struct __ec_align4 ec_response_usb_pd_power_info { +struct ec_response_usb_pd_power_info { uint8_t role; uint8_t type; uint8_t dualrole; uint8_t reserved1; struct usb_chg_measures meas; uint32_t max_power; -}; +} __ec_align4; /* @@ -4493,9 +4855,9 @@ * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports */ #define EC_CMD_CHARGE_PORT_COUNT 0x0105 -struct __ec_align1 ec_response_charge_port_count { +struct ec_response_charge_port_count { uint8_t port_count; -}; +} __ec_align1; /* Write USB-PD device FW */ #define EC_CMD_USB_PD_FW_UPDATE 0x0110 @@ -4507,41 +4869,43 @@ USB_PD_FW_ERASE_SIG, }; -struct __ec_align4 ec_params_usb_pd_fw_update { +struct ec_params_usb_pd_fw_update { uint16_t dev_id; uint8_t cmd; uint8_t port; uint32_t size; /* Size to write in bytes */ /* Followed by data to write */ -}; +} __ec_align4; /* Write USB-PD Accessory RW_HASH table entry */ #define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 /* RW hash is first 20 bytes of SHA-256 of RW section */ #define PD_RW_HASH_SIZE 20 -struct __ec_align1 ec_params_usb_pd_rw_hash_entry { +struct ec_params_usb_pd_rw_hash_entry { uint16_t dev_id; uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* For alignment of current_image + uint8_t reserved; /* + * For alignment of current_image * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. */ + * Should have been reserved[2]. + */ uint32_t current_image; /* One of ec_current_image */ -}; +} __ec_align1; /* Read USB-PD Accessory info */ #define EC_CMD_USB_PD_DEV_INFO 0x0112 -struct __ec_align1 ec_params_usb_pd_info_request { +struct ec_params_usb_pd_info_request { uint8_t port; -}; +} __ec_align1; /* Read USB-PD Device discovery info */ #define EC_CMD_USB_PD_DISCOVERY 0x0113 -struct __ec_align_size1 ec_params_usb_pd_discovery_entry { +struct ec_params_usb_pd_discovery_entry { uint16_t vid; /* USB-IF VID */ uint16_t pid; /* USB-IF PID */ uint8_t ptype; /* product type (hub,periph,cable,ama) */ -}; +} __ec_align_size1; /* Override default charge behavior */ #define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 @@ -4553,9 +4917,9 @@ /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ }; -struct __ec_align2 ec_params_charge_port_override { +struct ec_params_charge_port_override { int16_t override_port; /* Override port# */ -}; +} __ec_align2; /* * Read (and delete) one entry of PD event log. @@ -4564,14 +4928,13 @@ */ #define EC_CMD_PD_GET_LOG_ENTRY 0x0115 -struct __ec_align4 ec_response_pd_log { +struct ec_response_pd_log { uint32_t timestamp; /* relative timestamp in milliseconds */ uint8_t type; /* event type : see PD_EVENT_xx below */ uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ -}; - +} __ec_align4; /* The timestamp is the microsecond counter shifted to get about a ms. */ #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ @@ -4633,18 +4996,18 @@ /* * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". */ -struct __ec_align4 mcdp_version { +struct mcdp_version { uint8_t major; uint8_t minor; uint16_t build; -}; +} __ec_align4; -struct __ec_align4 mcdp_info { +struct mcdp_info { uint8_t family[2]; uint8_t chipid[2]; struct mcdp_version irom; struct mcdp_version fw; -}; +} __ec_align4; /* struct mcdp_info field decoding */ #define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) @@ -4652,16 +5015,16 @@ /* Get/Set USB-PD Alternate mode info */ #define EC_CMD_USB_PD_GET_AMODE 0x0116 -struct __ec_align_size1 ec_params_usb_pd_get_mode_request { +struct ec_params_usb_pd_get_mode_request { uint16_t svid_idx; /* SVID index to get */ uint8_t port; /* port */ -}; +} __ec_align_size1; -struct __ec_align4 ec_params_usb_pd_get_mode_response { +struct ec_params_usb_pd_get_mode_response { uint16_t svid; /* SVID */ uint16_t opos; /* Object Position */ uint32_t vdo[6]; /* Mode VDOs */ -}; +} __ec_align4; #define EC_CMD_USB_PD_SET_AMODE 0x0117 @@ -4672,20 +5035,20 @@ PD_MODE_CMD_COUNT, }; -struct __ec_align4 ec_params_usb_pd_set_mode_request { +struct ec_params_usb_pd_set_mode_request { uint32_t cmd; /* enum pd_mode_cmd */ uint16_t svid; /* SVID to set */ uint8_t opos; /* Object Position */ uint8_t port; /* port */ -}; +} __ec_align4; /* Ask the PD MCU to record a log of a requested type */ #define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 -struct __ec_align1 ec_params_pd_write_log_entry { +struct ec_params_pd_write_log_entry { uint8_t type; /* event type : see PD_EVENT_xx above */ uint8_t port; /* port#, or 0 for events unrelated to a given port */ -}; +} __ec_align1; /* Control USB-PD chip */ @@ -4699,36 +5062,37 @@ PD_CHIP_ON, /* Power on the PD chip */ }; -struct __ec_align1 ec_params_pd_control { +struct ec_params_pd_control { uint8_t chip; /* chip id */ uint8_t subcmd; -}; +} __ec_align1; /* Get info about USB-C SS muxes */ #define EC_CMD_USB_PD_MUX_INFO 0x011A -struct __ec_align1 ec_params_usb_pd_mux_info { +struct ec_params_usb_pd_mux_info { uint8_t port; /* USB-C port number */ -}; +} __ec_align1; /* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED (1 << 0) -#define USB_PD_MUX_DP_ENABLED (1 << 1) -#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) -#define USB_PD_MUX_HPD_IRQ (1 << 3) +#define USB_PD_MUX_USB_ENABLED (1 << 0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED (1 << 1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ (1 << 3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_LVL (1 << 4) /* HPD level is asserted */ -struct __ec_align1 ec_response_usb_pd_mux_info { +struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ -}; +} __ec_align1; #define EC_CMD_PD_CHIP_INFO 0x011B -struct __ec_align1 ec_params_pd_chip_info { +struct ec_params_pd_chip_info { uint8_t port; /* USB-C port number */ uint8_t renew; /* Force renewal */ -}; +} __ec_align1; -struct __ec_align2 ec_response_pd_chip_info { +struct ec_response_pd_chip_info { uint16_t vendor_id; uint16_t product_id; uint16_t device_id; @@ -4736,14 +5100,28 @@ uint8_t fw_version_string[8]; uint64_t fw_version_number; }; -}; +} __ec_align2; + +struct ec_response_pd_chip_info_v1 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + }; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + }; +} __ec_align2; /* Run RW signature verification and get status */ #define EC_CMD_RWSIG_CHECK_STATUS 0x011C -struct __ec_align4 ec_response_rwsig_check_status { +struct ec_response_rwsig_check_status { uint32_t status; -}; +} __ec_align4; /* For controlling RWSIG task */ #define EC_CMD_RWSIG_ACTION 0x011D @@ -4753,16 +5131,16 @@ RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ }; -struct __ec_align4 ec_params_rwsig_action { +struct ec_params_rwsig_action { uint32_t action; -}; +} __ec_align4; /* Run verification on a slot */ #define EC_CMD_EFS_VERIFY 0x011E -struct __ec_align1 ec_params_efs_verify { +struct ec_params_efs_verify { uint8_t region; /* enum ec_flash_region */ -}; +} __ec_align1; /* * Retrieve info from Cros Board Info store. Response is based on the data @@ -4777,11 +5155,12 @@ #define EC_CMD_SET_CROS_BOARD_INFO 0x0120 enum cbi_data_tag { - CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */ - CBI_TAG_OEM_ID = 1, /* uint8_t */ - CBI_TAG_SKU_ID = 2, /* uint8_t */ + CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_COUNT, }; @@ -4793,10 +5172,10 @@ */ #define CBI_GET_RELOAD (1 << 0) -struct __ec_align4 ec_params_get_cbi { +struct ec_params_get_cbi { uint32_t tag; /* enum cbi_data_tag */ uint32_t flag; /* CBI_GET_* */ -}; +} __ec_align4; /* * Flags to control write behavior. @@ -4809,20 +5188,51 @@ #define CBI_SET_NO_SYNC (1 << 0) #define CBI_SET_INIT (1 << 1) -struct __ec_align1 ec_params_set_cbi { +struct ec_params_set_cbi { uint32_t tag; /* enum cbi_data_tag */ uint32_t flag; /* CBI_SET_* */ uint32_t size; /* Data size */ uint8_t data[]; /* For string and raw data */ -}; +} __ec_align1; /* * Information about resets of the AP by the EC and the EC's own uptime. */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -struct __ec_align4 ec_response_uptime_info { - /* Number of milliseconds since last EC reset */ +/* Reset causes */ +#define EC_RESET_FLAG_OTHER (1 << 0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN (1 << 1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT (1 << 2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON (1 << 3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG (1 << 4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT (1 << 5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE (1 << 6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM (1 << 7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN (1 << 8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY (1 << 9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP (1 << 10) /* Jumped directly to this image + */ +#define EC_RESET_FLAG_HARD (1 << 11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF (1 << 12) /* Do not power on AP */ +#define EC_RESET_FLAG_PRESERVED (1 << 13) /* Some reset flags preserved from + * previous boot */ +#define EC_RESET_FLAG_USB_RESUME (1 << 14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD (1 << 15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX (1 << 16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY (1 << 17) /* Security threat */ +#define EC_RESET_FLAG_AP_WATCHDOG (1 << 18) /* AP experienced a watchdog reset + */ + +struct ec_response_uptime_info { + /* + * Number of milliseconds since the last EC boot. Sysjump resets + * typically do not restart the EC's time_since_boot epoch. + * + * WARNING: The EC's sense of time is much less accurate than the AP's + * sense of time, in both phase and frequency. This timebase is similar + * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. + */ uint32_t time_since_ec_boot_ms; /* @@ -4834,23 +5244,84 @@ uint32_t ap_resets_since_ec_boot; /* - * The set of flags which describe the EC's most recent reset. See - * include/system.h RESET_FLAG_* for details. + * The set of flags which describe the EC's most recent reset. + * See EC_RESET_FLAG_* for details. */ uint32_t ec_reset_flags; /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* See include/chipset.h for details */ + /* + * See include/chipset.h: enum chipset_{reset,shutdown}_reason + * for details. + */ uint16_t reset_cause; + /* Reserved for protocol growth. */ + uint16_t reserved; + /* * The time of the reset's assertion, in milliseconds since the - * last EC reset. Set to zero if the log entry is empty. + * last EC boot, in the same epoch as time_since_ec_boot_ms. + * Set to zero if the log entry is empty. */ uint32_t reset_time_ms; } recent_ap_reset[4]; +} __ec_align4; + +/* + * Add entropy to the device secret (stored in the rollback region). + * + * Depending on the chip, the operation may take a long time (e.g. to erase + * flash), so the commands are asynchronous. + */ +#define EC_CMD_ADD_ENTROPY 0x0122 + +enum add_entropy_action { + /* Add entropy to the current secret. */ + ADD_ENTROPY_ASYNC = 0, + /* + * Add entropy, and also make sure that the previous secret is erased. + * (this can be implemented by adding entropy multiple times until + * all rolback blocks have been overwritten). + */ + ADD_ENTROPY_RESET_ASYNC = 1, + /* Read back result from the previous operation. */ + ADD_ENTROPY_GET_RESULT = 2, }; + +struct ec_params_rollback_add_entropy { + uint8_t action; +} __ec_align1; + +/* + * Perform a single read of a given ADC channel. + */ +#define EC_CMD_ADC_READ 0x0123 + +struct ec_params_adc_read { + uint8_t adc_channel; +} __ec_align1; + +struct ec_response_adc_read { + int32_t adc_value; +} __ec_align4; + +/* + * Read back rollback info + */ +#define EC_CMD_ROLLBACK_INFO 0x0124 + +struct ec_response_rollback_info { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; +} __ec_align4; + + +/* Issue AP reset */ +#define EC_CMD_AP_RESET 0x0125 + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -4869,79 +5340,85 @@ #define EC_FP_FLAG_NOT_COMPLETE 0x1 -struct __ec_align2 ec_params_fp_passthru { +struct ec_params_fp_passthru { uint16_t len; /* Number of bytes to write then read */ uint16_t flags; /* EC_FP_FLAG_xxx */ uint8_t data[]; /* Data to send */ -}; - -/* Fingerprint sensor configuration command: prototyping ONLY */ -#define EC_CMD_FP_SENSOR_CONFIG 0x0401 - -#define EC_FP_SENSOR_CONFIG_MAX_REGS 16 - -struct __ec_align2 ec_params_fp_sensor_config { - uint8_t count; /* Number of setup registers */ - /* - * the value to send to each of the 'count' setup registers - * is stored in the 'data' array for 'len' bytes just after - * the previous one. - */ - uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS]; - uint8_t data[]; -}; +} __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP (1<<0) +#define FP_MODE_DEEPSLEEP (1<<0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN (1<<1) +#define FP_MODE_FINGER_DOWN (1<<1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP (1<<2) +#define FP_MODE_FINGER_UP (1<<2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE (1<<3) -/* Capture types defined in bits [30..28] */ -#define FP_MODE_CAPTURE_TYPE_SHIFT 28 -#define FP_MODE_CAPTURE_TYPE_MASK 0x7 -/* Full blown vendor-defined capture (produces 'frame_size' bytes) */ -#define FP_CAPTURE_VENDOR_FORMAT 0 -/* Simple raw image capture (produces width x height x bpp bits) */ -#define FP_CAPTURE_SIMPLE_IMAGE 1 -/* Self test pattern (e.g. checkerboard) */ -#define FP_CAPTURE_PATTERN0 2 -/* Self test pattern (e.g. inverted checkerboard) */ -#define FP_CAPTURE_PATTERN1 3 -/* Capture for Quality test with fixed contrast */ -#define FP_CAPTURE_QUALITY_TEST 4 -/* Capture for pixel reset value test */ -#define FP_CAPTURE_RESET_TEST 5 -/* Extracts the capture type from the sensor 'mode' word */ -#define FP_CAPTURE_TYPE(mode) (((mode) >> FP_MODE_CAPTURE_TYPE_SHIFT) \ - & FP_MODE_CAPTURE_TYPE_MASK) +#define FP_MODE_CAPTURE (1<<3) /* Finger enrollment session on-going */ #define FP_MODE_ENROLL_SESSION (1<<4) /* Enroll the current finger image */ #define FP_MODE_ENROLL_IMAGE (1<<5) /* Try to match the current finger image */ #define FP_MODE_MATCH (1<<6) +/* Reset and re-initialize the sensor. */ +#define FP_MODE_RESET_SENSOR (1<<7) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE (1<<31) -struct __ec_align4 ec_params_fp_mode { - uint32_t mode; /* as defined by FP_MODE_ constants */ -}; +#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ + FP_MODE_FINGER_DOWN | \ + FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | \ + FP_MODE_ENROLL_SESSION | \ + FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | \ + FP_MODE_DONT_CHANGE) -struct __ec_align4 ec_response_fp_mode { - uint32_t mode; /* as defined by FP_MODE_ constants */ +/* Capture types defined in bits [30..28] */ +#define FP_MODE_CAPTURE_TYPE_SHIFT 28 +#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) +/* + * This enum must remain ordered, if you add new values you must ensure that + * FP_CAPTURE_TYPE_MAX is still the last one. + */ +enum fp_capture_type { + /* Full blown vendor-defined capture (produces 'frame_size' bytes) */ + FP_CAPTURE_VENDOR_FORMAT = 0, + /* Simple raw image capture (produces width x height x bpp bits) */ + FP_CAPTURE_SIMPLE_IMAGE = 1, + /* Self test pattern (e.g. checkerboard) */ + FP_CAPTURE_PATTERN0 = 2, + /* Self test pattern (e.g. inverted checkerboard) */ + FP_CAPTURE_PATTERN1 = 3, + /* Capture for Quality test with fixed contrast */ + FP_CAPTURE_QUALITY_TEST = 4, + /* Capture for pixel reset value test */ + FP_CAPTURE_RESET_TEST = 5, + FP_CAPTURE_TYPE_MAX, }; +/* Extracts the capture type from the sensor 'mode' word */ +#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ + >> FP_MODE_CAPTURE_TYPE_SHIFT) + +struct ec_params_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; + +struct ec_response_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; /* Retrieve Fingerprint sensor information */ #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) +/* Unknown number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ #define FP_ERROR_NO_IRQ (1 << 12) /* SPI communication error */ @@ -4951,7 +5428,7 @@ /* Sensor initialization failed */ #define FP_ERROR_INIT_FAIL (1 << 15) -struct __ec_align4 ec_response_fp_info_v0 { +struct ec_response_fp_info_v0 { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4964,9 +5441,9 @@ uint16_t height; uint16_t bpp; uint16_t errors; /* see FP_ERROR_ flags above */ -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_info { +struct ec_response_fp_info { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4984,18 +5461,48 @@ uint16_t template_max; /* maximum number of fingers/templates */ uint16_t template_valid; /* number of valid fingers/templates */ uint32_t template_dirty; /* bitmap of templates with MCU side changes */ -}; + uint32_t template_version; /* version of the template format */ +} __ec_align4; /* Get the last captured finger frame or a template content */ #define EC_CMD_FP_FRAME 0x0404 /* constants defining the 'offset' field which also contains the frame index */ #define FP_FRAME_INDEX_SHIFT 28 +/* Frame buffer where the captured image is stored */ #define FP_FRAME_INDEX_RAW_IMAGE 0 -#define FP_FRAME_TEMPLATE_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) +/* First frame buffer holding a template */ +#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) #define FP_FRAME_OFFSET_MASK 0x0FFFFFFF -struct __ec_align4 ec_params_fp_frame { +/* Version of the format of the encrypted templates. */ +#define FP_TEMPLATE_FORMAT_VERSION 3 + +/* Constants for encryption parameters */ +#define FP_CONTEXT_NONCE_BYTES 12 +#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) +#define FP_CONTEXT_TAG_BYTES 16 +#define FP_CONTEXT_SALT_BYTES 16 +#define FP_CONTEXT_TPM_BYTES 32 + +struct ec_fp_template_encryption_metadata { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; + uint8_t salt[FP_CONTEXT_SALT_BYTES]; + uint8_t tag[FP_CONTEXT_TAG_BYTES]; +}; + +struct ec_params_fp_frame { /* * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE * in the high nibble, and the real offset within the frame in @@ -5003,7 +5510,7 @@ */ uint32_t offset; uint32_t size; -}; +} __ec_align4; /* Load a template into the MCU */ #define EC_CMD_FP_TEMPLATE 0x0405 @@ -5011,27 +5518,47 @@ /* Flag in the 'size' field indicating that the full template has been sent */ #define FP_TEMPLATE_COMMIT 0x80000000 -struct __ec_align4 ec_params_fp_template { +struct ec_params_fp_template { uint32_t offset; uint32_t size; uint8_t data[]; -}; +} __ec_align4; /* Clear the current fingerprint user context and set a new one */ #define EC_CMD_FP_CONTEXT 0x0406 -#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) -#define FP_CONTEXT_NONCE_WORDS (32 / sizeof(uint32_t)) - -struct __ec_align4 ec_params_fp_context { +struct ec_params_fp_context { uint32_t userid[FP_CONTEXT_USERID_WORDS]; - /* TODO(b/73337313) mostly a placeholder, details to be implemented */ - uint32_t nonce[FP_CONTEXT_NONCE_WORDS]; -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_context { - uint32_t nonce[FP_CONTEXT_NONCE_WORDS]; -}; +#define EC_CMD_FP_STATS 0x0407 + +#define FPSTATS_CAPTURE_INV (1 << 0) +#define FPSTATS_MATCHING_INV (1 << 1) + +struct ec_response_fp_stats { + uint32_t capture_time_us; + uint32_t matching_time_us; + uint32_t overall_time_us; + struct { + uint32_t lo; + uint32_t hi; + } overall_t0; + uint8_t timestamps_invalid; + int8_t template_matched; +} __ec_align2; + +#define EC_CMD_FP_SEED 0x0408 +struct ec_params_fp_seed { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* Seed from the TPM. */ + uint8_t seed[FP_CONTEXT_TPM_BYTES]; +} __ec_align4; /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ @@ -5042,10 +5569,10 @@ /* Get number of frame types, and the size of each type */ #define EC_CMD_TP_FRAME_INFO 0x0501 -struct __ec_align4 ec_response_tp_frame_info { +struct ec_response_tp_frame_info { uint32_t n_frames; uint32_t frame_sizes[0]; -}; +} __ec_align4; /* Create a snapshot of current frame readings */ #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 @@ -5053,11 +5580,11 @@ /* Read the frame */ #define EC_CMD_TP_FRAME_GET 0x0503 -struct __ec_align4 ec_params_tp_frame_get { +struct ec_params_tp_frame_get { uint32_t frame_index; uint32_t offset; uint32_t size; -}; +} __ec_align4; /*****************************************************************************/ /* EC-EC communication commands: range 0x0600-0x06FF */ @@ -5070,20 +5597,34 @@ */ #define EC_CMD_BATTERY_GET_STATIC 0x0600 -struct __ec_align_size1 ec_params_battery_static_info { - uint8_t index; /* Battery index. */ -}; +/** + * struct ec_params_battery_static_info - Battery static info parameters + * @index: Battery index. + */ +struct ec_params_battery_static_info { + uint8_t index; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_static_info { - uint16_t design_capacity; /* Battery Design Capacity (mAh) */ - uint16_t design_voltage; /* Battery Design Voltage (mV) */ - char manufacturer[EC_COMM_TEXT_MAX]; /* Battery Manufacturer String */ - char model[EC_COMM_TEXT_MAX]; /* Battery Model Number String */ - char serial[EC_COMM_TEXT_MAX]; /* Battery Serial Number String */ - char type[EC_COMM_TEXT_MAX]; /* Battery Type String */ +/** + * struct ec_response_battery_static_info - Battery static info response + * @design_capacity: Battery Design Capacity (mAh) + * @design_voltage: Battery Design Voltage (mV) + * @manufacturer: Battery Manufacturer String + * @model: Battery Model Number String + * @serial: Battery Serial Number String + * @type: Battery Type String + * @cycle_count: Battery Cycle Count + */ +struct ec_response_battery_static_info { + uint16_t design_capacity; + uint16_t design_voltage; + char manufacturer[EC_COMM_TEXT_MAX]; + char model[EC_COMM_TEXT_MAX]; + char serial[EC_COMM_TEXT_MAX]; + char type[EC_COMM_TEXT_MAX]; /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ - uint32_t cycle_count; /* Battery Cycle Count */ -}; + uint32_t cycle_count; +} __ec_align4; /* * Get battery dynamic information, i.e. information that is likely to change @@ -5091,39 +5632,54 @@ */ #define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 -struct __ec_align_size1 ec_params_battery_dynamic_info { - uint8_t index; /* Battery index. */ -}; +/** + * struct ec_params_battery_dynamic_info - Battery dynamic info parameters + * @index: Battery index. + */ +struct ec_params_battery_dynamic_info { + uint8_t index; +} __ec_align_size1; -struct __ec_align2 ec_response_battery_dynamic_info { - int16_t actual_voltage; /* Battery voltage (mV) */ - int16_t actual_current; /* Battery current (mA); negative=discharging */ - int16_t remaining_capacity; /* Remaining capacity (mAh) */ - int16_t full_capacity; /* Capacity (mAh, might change occasionally) */ - int16_t flags; /* Flags, see EC_BATT_FLAG_* */ - int16_t desired_voltage; /* Charging voltage desired by battery (mV) */ - int16_t desired_current; /* Charging current desired by battery (mA) */ -}; +/** + * struct ec_response_battery_dynamic_info - Battery dynamic info response + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + */ +struct ec_response_battery_dynamic_info { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; +} __ec_align2; /* * Control charger chip. Used to control charger chip on the slave. */ #define EC_CMD_CHARGER_CONTROL 0x0602 -struct __ec_align_size1 ec_params_charger_control { - /* - * Charger current (mA). Positive to allow base to draw up to - * max_current and (possibly) charge battery, negative to request - * current from base (OTG). - */ +/** + * struct ec_params_charger_control - Charger control parameters + * @max_current: Charger current (mA). Positive to allow base to draw up to + * max_current and (possibly) charge battery, negative to request current + * from base (OTG). + * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is + * >= 0. + * @allow_charging: Allow base battery charging (only makes sense if + * max_current > 0). + */ +struct ec_params_charger_control { int16_t max_current; - - /* Voltage (mV) to use in OTG mode, ignored if max_current is >= 0. */ uint16_t otg_voltage; - - /* Allow base battery charging (only makes sense if max_current > 0). */ uint8_t allow_charging; -}; +} __ec_align_size1; /*****************************************************************************/ /* @@ -5201,4 +5757,8 @@ #endif /* !__ACPI__ */ +#ifdef __cplusplus +} +#endif + #endif /* __CROS_EC_EC_COMMANDS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d Gerrit-Change-Number: 31885 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

6 18

Change in ...coreboot[master]: soc/amd/common: Refactor S3 helpers
by Kyösti Mälkki (Code Review) 16 Aug '19

16 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31490 Change subject: soc/amd/common: Refactor S3 helpers ...................................................................... soc/amd/common: Refactor S3 helpers Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/s3_resume.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/s3/Makefile.inc M src/soc/amd/common/block/s3/s3_resume.c 4 files changed, 53 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31490/1 diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 13f8010..9323baf 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -17,10 +17,10 @@ #define __AMD_S3_RESUME_H__ #include <stdint.h> +#include <agesa_headers.h> -int save_s3_info(void *nv_base, size_t nv_size, - void *vol_base, size_t vol_size); -void get_s3nv_info(void **base, size_t *size); -void get_s3vol_info(void **base, size_t *size); +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); #endif /* __AMD_S3_RESUME_H__ */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index e769a45..1579b0b 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -313,10 +313,8 @@ Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, - RtbParams->S3DataBlock.NvStorageSize, - RtbParams->S3DataBlock.VolatileStorage, - RtbParams->S3DataBlock.VolatileStorageSize)) + Status = OemS3Save(&RtbParams->S3DataBlock); + if (Status != AGESA_SUCCESS) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); return Status; @@ -325,10 +323,8 @@ static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - size_t nv_size; - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); - InitResumeParams->S3DataBlock.NvStorageSize = nv_size; + OemInitResume(&InitResumeParams->S3DataBlock); timestamp_add_now(TS_AGESA_INIT_RESUME_START); status = amd_dispatch(InitResumeParams); @@ -340,12 +336,10 @@ static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - size_t vol_size; amd_initcpuio(); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); - S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3LateParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_LATE_START); Status = amd_dispatch(S3LateParams); @@ -357,10 +351,8 @@ static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - size_t vol_size; - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); - S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3FinalParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_FINAL_START); Status = amd_dispatch(S3FinalParams); diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc index 7d950b0..9efc6bc 100644 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ b/src/soc/amd/common/block/s3/Makefile.inc @@ -1,6 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c endif diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index eb0148f..818bde2 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -31,49 +31,66 @@ board_reset(); } -void get_s3nv_info(void **base, size_t *size) +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) { + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; struct region_device rdev; if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, &rdev)) reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - *base = rdev_mmap_full(&rdev); - *size = region_device_sz(&rdev); - if (!*base || !*size) + base = rdev_mmap_full(&rdev); + size = region_device_sz(&rdev); + if (!base || !size) reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); /* Read 16 bytes to infer if the NV has been erased from flash. */ - int i; - uint32_t erased = 0xffffffff; for (i = 0; i < 4; i++) - erased &= read32((uint32_t *)*base + i); - + erased &= read32((uint32_t *)base + i); if (erased == 0xffffffff) reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); - printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", *base, *size); + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + + return AGESA_SUCCESS; } -void get_s3vol_info(void **base, size_t *size) +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) { - stage_cache_get_raw(STAGE_S3_DATA, base, size); - if (!*base || !*size) + void *base; + size_t size; + + stage_cache_get_raw(STAGE_S3_DATA, &base, &size); + if (!base || !size) { printk(BIOS_ERR, "Error: S3 volatile data not found\n"); - else - printk(BIOS_SPEW, "S3 volatile data @0x%p 0x%0zx total bytes\n", - *base, *size); -} - -int save_s3_info(void *nv_base, size_t nv_size, void *vol_base, size_t vol_size) -{ - if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, - nv_base, nv_size) < 0) { - printk(BIOS_ERR, "Failed to stash MRC data\n"); - return -1; + return AGESA_FATAL; } - stage_cache_add_raw(STAGE_S3_DATA, vol_base, vol_size); - return 0; + dataBlock->VolatileStorage = base; + dataBlock->VolatileStorageSize = size; + printk(BIOS_SPEW, "S3 volatile data @0x%p, 0x%0zx bytes\n", + dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock) +{ + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } + + stage_cache_add_raw(STAGE_S3_DATA, dataBlock->VolatileStorage, + dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59 Gerrit-Change-Number: 31490 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in ...coreboot[master]: mediaek/mt8183: add dsi driver for mt8183
by jitao shi (Code Review) 15 Aug '19

15 Aug '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31591 Change subject: mediaek/mt8183: add dsi driver for mt8183 ...................................................................... mediaek/mt8183: add dsi driver for mt8183 BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/dsi.h 4 files changed, 957 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31591/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b7e2ca4..02eaf6b 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ddp.c +ramstage-y += dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c new file mode 100644 index 0000000..f96d847 --- /dev/null +++ b/src/soc/mediatek/mt8183/dsi.c @@ -0,0 +1,470 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +static void mipi_write32(void *a, uint32_t offset, uint32_t v) +{ + write32(a + offset, v); +} + +static void mipi_clrsetbits_le32(void *a, uint32_t offset, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a + offset, m, v); +} + +static void mipi_clrbits_le32(void *a, uint32_t offset, uint32_t m) +{ + clrbits_le32(a + offset, m); +} + +static void mipi_setbits_le32(void *a, uint32_t offset, uint32_t m) +{ + setbits_le32(a + offset, m); +} + +static void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +static void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +static void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits; + u64 total_bits; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + htotal = edid->mode.hbl + edid->mode.ha; + htotal_bits = htotal * bit_per_pixel; + + overhead_cycles = 2 * phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_trail + + phy_timing->da_hs_exit + 1; + + overhead_bits = overhead_cycles * 8U; + total_bits = htotal_bits + overhead_bits; + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * total_bits) / (htotal * lanes); + + printk(BIOS_ERR, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), and number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes); + return -1; + } + + mipi_clrbits_le32(mipi_tx, MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + mipi_setbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + mipi_clrbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)) << 24; + pcw /= 26; + + mipi_write32(mipi_tx, MIPITX_PLL_CON0, pcw); + mipi_clrsetbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + mipi_setbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + mipi_write32(mipi_tx, MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + mipi_write32(mipi_tx, MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + mipi_clrbits_le32(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + mipi_setbits_le32(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_phy_timconfig(u32 data_rate, struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); +} + +static void mtk_dsi_reset(void) +{ + dsi_setbits_le32(&dsi->dsi_con_ctrl, 3); + dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1); +} + +static void mtk_dsi_clk_hs_mode_enable(void) +{ + dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_clk_hs_mode_disable(void) +{ + dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_set_mode(u32 mode_flags) +{ + u32 tmp_reg1 = 0; + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); +} + +static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 ui, cycle_time, data_rate; + u32 bit_per_pixel; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(0x50, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((0x40 + 0x5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((0xc8 + 0x0a * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((0x4 * ui) + 0x50), cycle_time); + + if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare) + phy_timing->da_hs_zero -= phy_timing->da_hs_prepare; + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; +} + +static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); +} + +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, + const struct edid *edid) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + + dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; + + dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); +} + +static void mtk_dsi_start(void) +{ + dsi_write32(&dsi->dsi_start, 0); + dsi_write32(&dsi->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0; + + switch (len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < len; i++) + dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + + dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + dsi_write32(&dsi->dsi_intsta, 0); + mtk_dsi_start(); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi DONE INT Timeout\n"); + + dsi_write32(&dsi->dsi_start, 0); +} + +static void push_table(struct lcm_init_table *init_cmd, u32 count) +{ + u32 cmd, i; + + for (i = 0; i < count; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].cmd); + break; + + case END_OF_TABLE: + break; + + case INIT_CMD: + default: + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len); + break; + } + } +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd, u32 count) +{ + int data_rate; + struct mtk_phy_timing phy_timing; + + mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); + + data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid, &phy_timing); + + if (data_rate < 0) + return -1; + + mtk_dsi_reset(); + dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_phy_timconfig(data_rate, &phy_timing); + mtk_dsi_rxtx_control(mode_flags, lanes); + mtk_dsi_clk_hs_mode_disable(); + mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_clk_hs_mode_enable(); + mtk_dsi_set_mode(0); + push_table(init_cmd, count); + mtk_dsi_set_mode(mode_flags); + mtk_dsi_start(); + + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 88653eb..75202dd 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -47,6 +47,7 @@ IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, + MIPITX_BASE = IO_PHYS + 0x01E50000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000, @@ -64,6 +65,7 @@ DISP_AAL0_BASE = IO_PHYS + 0x04010000, DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DSI_BASE = IO_PHYS + 0x04014000, DISP_MUTEX_BASE = IO_PHYS + 0x04016000, SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h new file mode 100644 index 0000000..7b74478 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -0,0 +1,484 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DSI_REG_H_ +#define _DSI_REG_H_ + +#include <edid.h> +#include <types.h> + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565 +}; + +/* video mode */ +enum { + MIPI_DSI_MODE_VIDEO = BIT(0), + /* video burst mode */ + MIPI_DSI_MODE_VIDEO_BURST = BIT(1), + /* video pulse mode */ + MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), + /* enable auto vertical count mode */ + MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), + /* enable hsync-end packets in vsync-pulse and v-porch area */ + MIPI_DSI_MODE_VIDEO_HSE = BIT(4), + /* disable hfront-porch area */ + MIPI_DSI_MODE_VIDEO_HFP = BIT(5), + /* disable hback-porch area */ + MIPI_DSI_MODE_VIDEO_HBP = BIT(6), + /* disable hsync-active area */ + MIPI_DSI_MODE_VIDEO_HSA = BIT(7), + /* flush display FIFO on vsync pulse */ + MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), + /* disable EoT packets in HS mode */ + MIPI_DSI_MODE_EOT_PACKET = BIT(9), + /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ + MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), + /* transmit data in low power */ + MIPI_DSI_MODE_LPM = BIT(11) +}; + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; + u32 dsi_lfr_sta; + u32 dsi_size_con; + u32 dsi_vfp_early_stop; + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; + u8 reserved6[108]; + u32 dsi_cmdq0; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq0, 0x200); +static struct dsi_regs *const dsi = (void *)DSI_BASE; + +#define DELAY_CMD 0 +#define END_OF_TABLE 1 +#define INIT_CMD 2 + +struct lcm_init_table { + u32 cmd; + u32 len; + u8 data[64]; +}; + +struct mtk_phy_timing { + u8 lpx; + u8 da_hs_prepare; + u8 da_hs_zero; + u8 da_hs_trail; + + u8 ta_go; + u8 ta_sure; + u8 ta_get; + u8 da_hs_exit; + + u8 clk_hs_zero; + u8 clk_hs_trail; + + u8 clk_hs_prepare; + u8 clk_hs_post; + u8 clk_hs_exit; +}; + +/* DSI_INTSTA */ +enum { + LPRX_RD_RDY_INT_FLAG = BIT(0), + CMD_DONE_INT_FLAG = BIT(1), + TE_RDY_INT_FLAG = BIT(2), + VM_DONE_INT_FLAG = BIT(3), + EXT_TE_RDY_INT_FLAG = BIT(4), + DSI_BUSY = BIT(31), +}; + +/* DSI_CON_CTRL */ +enum { + DSI_RESET = BIT(0), + DSI_EN = BIT(1), + DSI_DUAL = BIT(4), +}; + +/* DSI_MODE_CTRL */ +enum { + MODE = 3, + CMD_MODE = 0, + SYNC_PULSE_MODE = 1, + SYNC_EVENT_MODE = 2, + BURST_MODE = 3, + FRM_MODE = BIT(16), + MIX_MODE = BIT(17) +}; + +/* DSI_PSCTRL */ +enum { + DSI_PS_WC = 0x3fff, + DSI_PS_SEL = (3 << 16), + PACKED_PS_16BIT_RGB565 = (0 << 16), + LOOSELY_PS_18BIT_RGB666 = (1 << 16), + PACKED_PS_18BIT_RGB666 = (2 << 16), + PACKED_PS_24BIT_RGB888 = (3 << 16) +}; + +/* DSI_CMDQ_SIZE */ +enum { + CMDQ_SIZE = 0x3f, +}; + +/* DSI_PHY_LCCON */ +enum { + LC_HS_TX_EN = BIT(0), + LC_ULPM_EN = BIT(1), + LC_WAKEUP_EN = BIT(2) +}; + +/*DSI_PHY_LD0CON */ +enum { + LD0_RM_TRIG_EN = BIT(0), + LD0_ULPM_EN = BIT(1), + LD0_WAKEUP_EN = BIT(2) +}; + +enum { + LPX = (0xff << 0), + HS_PRPR = (0xff << 8), + HS_ZERO = (0xff << 16), + HS_TRAIL = (0xff << 24) +}; + +enum { + TA_GO = (0xff << 0), + TA_SURE = (0xff << 8), + TA_GET = (0xff << 16), + DA_HS_EXIT = (0xff << 24) +}; + +enum { + CONT_DET = (0xff << 0), + CLK_ZERO = (0xf << 16), + CLK_TRAIL = (0xff << 24) +}; + +enum { + CLK_HS_PRPR = (0xff << 0), + CLK_HS_POST = (0xff << 8), + CLK_HS_EXIT = (0xf << 16) +}; + +/* DSI_VM_CMD_CON */ +enum { + VM_CMD_EN = BIT(0), + TS_VFP_EN = BIT(5), +}; + +/* DSI_CMDQ0 */ +enum { + CONFIG = (0xff << 0), + SHORT_PACKET = 0, + LONG_PACKET = 2, + BTA = BIT(2), + DATA_ID = (0xff << 8), + DATA_0 = (0xff << 16), + DATA_1 = (0xff << 24), +}; + +#define MIPITX_LANE_CON 0x000c +#define MIPITX_PLL_PWR 0x0028 +#define MIPITX_PLL_CON0 0x002c +#define MIPITX_PLL_CON1 0x0030 +#define MIPITX_PLL_CON2 0x0034 +#define MIPITX_PLL_CON3 0x0038 +#define MIPITX_PLL_CON4 0x003c +#define MIPITX_D2_SW_CTL_EN 0x0144 +#define MIPITX_D0_SW_CTL_EN 0x0244 +#define MIPITX_CK_CKMODE_EN 0x0328 +#define DSI_CK_CKMODE_EN BIT(0) +#define MIPITX_CK_SW_CTL_EN 0x0344 +#define MIPITX_D1_SW_CTL_EN 0x0444 +#define MIPITX_D3_SW_CTL_EN 0x0544 +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 dsi_con; + u32 dsi_clock_lane; + u32 dsi_data_lane[4]; + u8 reserved0[40]; + u32 dsi_top_con; + u32 dsi_bg_con; + u8 reserved1[8]; + u32 dsi_pll_con0; + u32 dsi_pll_con1; + u32 dsi_pll_con2; + u32 dsi_pll_con3; + u32 dsi_pll_chg; + u32 dsi_pll_top; + u32 dsi_pll_pwr; + u8 reserved2[4]; + u32 dsi_rgs; + u32 dsi_gpi_en; + u32 dsi_gpi_pull; + u32 dsi_phy_sel; + u32 dsi_sw_ctrl_en; + u32 dsi_sw_ctrl_con0; + u32 dsi_sw_ctrl_con1; + u32 dsi_sw_ctrl_con2; + u32 dsi_dbg_con; + u32 dsi_dbg_out; + u32 dsi_apb_async_sta; +}; + +check_member(mipi_tx_regs, dsi_top_con, 0x40); +check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); + +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* MIPITX_DSI_CON */ +enum { + RG_DSI_LDOCORE_EN = BIT(0), + RG_DSI_CKG_LDOOUT_EN = BIT(1), + RG_DSI_BCLK_SEL = (3 << 2), + RG_DSI_LD_IDX_SEL = (7 << 4), + RG_DSI_PHYCLK_SEL = (2 << 8), + RG_DSI_DSICLK_FREQ_SEL = BIT(10), + RG_DSI_LPTX_CLMP_EN = BIT(11) +}; + +/* MIPITX_DSI_CLOCK_LANE */ +enum { + LDOOUT_EN = BIT(0), + CKLANE_EN = BIT(1), + IPLUS1 = BIT(2), + LPTX_IPLUS2 = BIT(3), + LPTX_IMINUS = BIT(4), + LPCD_IPLUS = BIT(5), + LPCD_IMLUS = BIT(6), + RT_CODE = (0xf << 8) +}; + +/* MIPITX_DSI_TOP_CON */ +enum { + RG_DSI_LNT_INTR_EN = BIT(0), + RG_DSI_LNT_HS_BIAS_EN = BIT(1), + RG_DSI_LNT_IMP_CAL_EN = BIT(2), + RG_DSI_LNT_TESTMODE_EN = BIT(3), + RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), + RG_DSI_LNT_AIO_SEL = (7 << 8), + RG_DSI_PAD_TIE_LOW_EN = BIT(11), + RG_DSI_DEBUG_INPUT_EN = BIT(12), + RG_DSI_PRESERVE = (7 << 13) +}; + +/* MIPITX_DSI_BG_CON */ +enum { + RG_DSI_BG_CORE_EN = BIT(0), + RG_DSI_BG_CKEN = BIT(1), + RG_DSI_BG_DIV = (0x3 << 2), + RG_DSI_BG_FAST_CHARGE = BIT(4), + RG_DSI_V12_SEL = (7 << 5), + RG_DSI_V10_SEL = (7 << 8), + RG_DSI_V072_SEL = (7 << 11), + RG_DSI_V04_SEL = (7 << 14), + RG_DSI_V032_SEL = (7 << 17), + RG_DSI_V02_SEL = (7 << 20), + rsv_23 = BIT(23), + RG_DSI_BG_R1_TRIM = (0xf << 24), + RG_DSI_BG_R2_TRIM = (0xf << 28) +}; + +/* MIPITX_DSI_PLL_CON0 */ +enum { + RG_DSI_MPPLL_PLL_EN = BIT(0), + RG_DSI_MPPLL_PREDIV = (3 << 1), + RG_DSI_MPPLL_TXDIV0 = (3 << 3), + RG_DSI_MPPLL_TXDIV1 = (3 << 5), + RG_DSI_MPPLL_POSDIV = (7 << 7), + RG_DSI_MPPLL_MONVC_EN = BIT(10), + RG_DSI_MPPLL_MONREF_EN = BIT(11), + RG_DSI_MPPLL_VOD_EN = BIT(12) +}; + +/* MIPITX_DSI_PLL_CON1 */ +enum { + RG_DSI_MPPLL_SDM_FRA_EN = BIT(0), + RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1), + RG_DSI_MPPLL_SDM_SSC_EN = BIT(2), + RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16) +}; + +/* MIPITX_DSI_PLL_PWR */ +enum { + RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), + RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), + RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +#define MTK_DSI_HOST_IS_READ(type) \ + ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ + (type == MIPI_DSI_DCS_READ)) + +extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd, u32 count); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Gerrit-Change-Number: 31591 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

7 50

Change in ...coreboot[master]: mediatek/mt8183: Add display driver
by yongqiang niu (Code Review) 09 Aug '19

09 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31478 Change subject: mediatek/mt8183: Add display driver ...................................................................... mediatek/mt8183: Add display driver BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/ddp.h 5 files changed, 602 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31478/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..a089236 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,36 @@ setup_usb_host(); } +static void display_startup(void) +{ + int ret = 0; + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "start display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..225a969 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ddp.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c new file mode 100644 index 0000000..2e2c0d2 --- /dev/null +++ b/src/soc/mediatek/mt8183/ddp.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); + + write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0); + + write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L); + + write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR); + + write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0); + + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +static void ovl_layer_enable(u32 idx) +{ + write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void rdma_start(u32 idx) +{ + setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); +} + +static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh) +{ + u32 threshold; + u32 reg; + u32 fifo_size; + + /* Config width */ + clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); + + /* Config height */ + clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + + fifo_size = RDMA_FIFO_SIZE_0 * KiB; + + threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[idx]->fifo_con, reg); +} + +static void color_start(u32 width, u32 height) +{ + write32(&disp_color->width, width); + write32(&disp_color->height, height); + write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color->start, BIT(0)); +} + +static void aal_start(u32 width, u32 height) +{ + write32(&disp_aal->size, height << 16 | width); + write32(&disp_aal->en, PQ_EN); +} + +static void ccorr_start(u32 width, u32 height) +{ + write32(&disp_ccorr->size, height << 16 | width); + write32(&disp_ccorr->cfg, PQ_RELAY_MODE); + write32(&disp_ccorr->en, PQ_EN); +} + +static void dither_start(u32 width, u32 height) +{ + write32(&disp_dither->size, height << 16 | width); + write32(&disp_dither->cfg, PQ_RELAY_MODE); + write32(&disp_dither->en, PQ_EN); +} + +static void gamma_start(u32 width, u32 height) +{ + write32(&disp_gamma->size, height << 16 | width); + write32(&disp_gamma->en, PQ_EN); +} + +static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[idx]->layer[0].con, fmt << 12); + write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(idx); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + + /* Setup OVL */ + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + u32 color = 0; + + if (idx == 0) + color = 0xFF0000FF; + + ovl_set_roi(idx, width, height, color); + } + + /* Setup RDMA0 */ + idx = 0; + rdma_config(idx, width, height, vrefresh); + + /* Setup Color */ + color_start(width, height); + + /* Setup CCORR */ + ccorr_start(width, height); + + /* Setup AAL */ + aal_start(width, height); + + /* Setup GAMMA */ + gamma_start(width, height); + + /* Setup DITHER */ + dither_start(width, height); + + /* Setup main path connection */ + disp_config_main_path_connection(); + + /* Setup main path mutex */ + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); +} + +static void disp_m4u_port_off(void) +{ + write32((void *)(SMI_LARB0 + 0x380), 0); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + disp_m4u_port_off(); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 idx = 0; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + main_disp_path_setup(width, height, vrefresh); + + rdma_start(idx); + + ovl_layer_config(idx, fmt, bpp, width, height); + + ovl_bgclr_in_sel(idx+1); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..88653eb 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -53,6 +53,19 @@ IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h new file mode 100644 index 0000000..38f66e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -0,0 +1,326 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include <soc/addressmap.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[889]; /* 0x11C */ + u32 disp_ovl0_mout_en; /* 0xF00 */ + u32 disp_ovl0_2l_mout_en; /* 0xF04 */ + u32 disp_ovl1_2l_mout_en; /* 0xF08 */ + u32 disp_dither0_mout_en; /* 0xF0C */ + u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */ + u32 disp_path0_sel_in; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 dsi0_sel_in; /* 0xF2C */ + u32 dpi0_sel_in; /* 0xF30 */ + u32 reserved_0xF34; /* 0xF34 */ + u32 disp_ovl0_2l_sel_in; /* 0xF38 */ + u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */ + u32 disp_rdma0_sout_sel_in; /* 0xF50 */ + u32 disp_rdma1_sout_sel_in; /* 0xF54 */ + u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */ + u32 dpi0_sel_sout_sel_in; /* 0xF64 */ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, reserved_0x11C, 0x11C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF00); +check_member(mmsys_cfg_regs, reserved_0xF10, 0xF10); +check_member(mmsys_cfg_regs, disp_path0_sel_in, 0xF24); +check_member(mmsys_cfg_regs, disp_ovl0_2l_sel_in, 0xF38); +check_member(mmsys_cfg_regs, reserved_0xF3C, 0xF3C); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel_in, 0xF50); +check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_GALS_COMMON0 = BIT(3), + CG_CON0_GALS_COMMON1 = BIT(4), + CG_CON0_DISP_OVL0 = BIT(20), + CG_CON0_DISP_OVL0_2L = BIT(21), + CG_CON0_DISP_OVL1_2L = BIT(22), + CG_CON0_DISP_RDMA0 = BIT(23), + CG_CON0_DISP_RDMA1 = BIT(24), + CG_CON0_DISP_WDMA0 = BIT(25), + CG_CON0_DISP_COLOR0 = BIT(26), + CG_CON0_DISP_CCORR0 = BIT(27), + CG_CON0_DISP_AAL0 = BIT(28), + CG_CON0_DISP_GAMMA0 = BIT(29), + CG_CON0_DISP_DITHER0 = BIT(30), + CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_GALS_COMMON0 | + CG_CON0_GALS_COMMON1 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_DSI0 = BIT(0), + CG_CON1_DISP_DSI0_INTERFACE = BIT(1), + CG_CON1_DISP_26M = BIT(7), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_RDMA0 = BIT(0), + OVL0_MOUT_EN_OVL0_2L = BIT(4), + OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0), + OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4), + DITHER0_MOUT_EN_DISP_DSI0 = BIT(0), +}; + +enum { + DISP_PATH0_SEL_IN_OVL0 = 0, + DISP_PATH0_SEL_IN_OVL0_2L = 1, + DSI0_SEL_IN_DITHER0_MOUT = 0, + DSI0_SEL_IN_RDMA0 = 1, + RDMA0_SOUT_SEL_IN_DSI0 = 0, + RDMA0_SOUT_SEL_IN_COLOR = 1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_RDMA0 = BIT(0), + MUTEX_MOD_DISP_RDMA1 = BIT(1), + MUTEX_MOD_DISP_OVL0 = BIT(9), + MUTEX_MOD_DISP_OVL0_2L = BIT(10), + MUTEX_MOD_DISP_OVL1_2L = BIT(11), + MUTEX_MOD_DISP_WDMA0 = BIT(12), + MUTEX_MOD_DISP_COLOR0 = BIT(13), + MUTEX_MOD_DISP_CCORR0 = BIT(14), + MUTEX_MOD_DISP_AAL0 = BIT(15), + MUTEX_MOD_DISP_GAMMA0 = BIT(16), + MUTEX_MOD_DISP_DITHER0 = BIT(17), + MUTEX_MOD_DISP_PWM0 = BIT(28), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0| MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u32 reserved_0x018[2]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u32 reserved_0x0B0[4]; + struct { + u32 ctrl; + u32 reserved0; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u32 reserved1[3]; + } rdma[4]; + u32 reserved_0x140[880]; + u32 reserved_0xF00[16]; + u32 l0_addr; + u32 reserved_0xF44[7]; + u32 l1_addr; + u32 reserved_0xF64[7]; + u32 l2_addr; + u32 reserved_0xF84[7]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, reserved_0x018, 0x018); +check_member(disp_ovl_regs, roi_size, 0x020); +check_member(disp_ovl_regs, reserved_0x0B0, 0x0B0); +check_member(disp_ovl_regs, reserved_0x140, 0x140); +check_member(disp_ovl_regs, reserved_0xF00, 0xF00); +check_member(disp_ovl_regs, l0_addr, 0xF40); +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u32 reserved0[2]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u32 reserved1; + u32 mem_con; + u32 reserved2; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_gmc_setting_1; + u32 mem_slow_con; + u32 mem_gmc_setting_2; + u32 fifo_con; + u32 reserved3[4]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_FIFO_SIZE_0 = 5, /* 5K */ + RDMA_VREFRESH = 60, /* vrefresh 60HZ */ + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma[2] = { + (void *)DISP_RDMA0_BASE, + (void *)DISP_RDMA1_BASE, +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +struct disp_pq_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), +}; + +static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Gerrit-Change-Number: 31478 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

9 61

Change in ...coreboot[master]: WIP: riscv: Implement FIT for RISC-V
by Philipp Hug (Code Review) 08 Aug '19

08 Aug '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31215 Change subject: WIP: riscv: Implement FIT for RISC-V ...................................................................... WIP: riscv: Implement FIT for RISC-V Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 --- M payloads/Kconfig M src/arch/riscv/Makefile.inc A src/arch/riscv/fit_payload.c M src/soc/sifive/fu540/Kconfig 4 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31215/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index c7a7ba6..0c5ce8f 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 + depends on ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..12609d4 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -139,6 +139,7 @@ ramstage-y += tables.c ramstage-y += payload.S ramstage-$(ARCH_RISCV_PMP) += pmp.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c new file mode 100644 index 0000000..2176095 --- /dev/null +++ b/src/arch/riscv/fit_payload.c @@ -0,0 +1,166 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootmem.h> +#include <stdlib.h> +#include <program_loading.h> +#include <string.h> +#include <commonlib/compression.h> +#include <commonlib/cbfs_serialized.h> +#include <lib.h> +#include <fit.h> +#include <endian.h> + +#define MAX_KERNEL_SIZE (64*MiB) + +static bool fit_place_kernel(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /** + * The Image must be placed text_offset bytes from a 2MB aligned base + * address anywhere in usable system RAM and called there. The region + * between the 2 MB aligned base address and the start of the image has + * no special significance to the kernel, and may be used for other + * purposes. + * + * If the reserved memory (BL31 for example) is smaller than text_offset + * we can use the 2 MiB base address, otherwise use the next 2 MiB page. + * It's not mandatory, but wastes less memory below the kernel. + */ + start = ALIGN_DOWN(range_entry_base(r), 2 * MiB); + + if (start < range_entry_base(r)) + start += 2 * MiB; + /** + * At least image_size bytes from the start of the image must be free + * for use by the kernel. + */ + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + * The region->offset is usually 0 on kernel >v4.6 and kernel_base + kernel_size + * on kernel <v4.6. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + bool place_anywhere; + void *arg = NULL; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot an RISCV kernel!\n"); + return false; + } + + /* Update kernel size from image header, if possible */ + kernel->size = 0x2000000; //get_kernel_size(config->kernel_node); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + + if (!bootmem_walk(fit_place_kernel, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * NOTE: versions prior to v4.6 cannot make use of memory below the + * physical offset of the Image so it is recommended that the Image be + * placed as close as possible to the start of system RAM. + * + * For kernel <v4.6 the INITRD and FDT can't be placed below the kernel. + * In that case set region offset to an address on top of kernel. + */ + + place_anywhere = false; + printk(BIOS_DEBUG, "FIT: Placing FDT and INITRD %s\n", + place_anywhere ? "anywhere" : "on top of kernel"); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = 0; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + if (place_anywhere) + fdt->offset = 0; + else + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..20645da 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,7 @@ int default 0 +config HEAP_SIZE + default 0x10000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 Gerrit-Change-Number: 31215 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: kukui/mainboard: Add mt8183 display usecase
by yongqiang niu (Code Review) 07 Aug '19

07 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31517 Change subject: kukui/mainboard: Add mt8183 display usecase ...................................................................... kukui/mainboard: Add mt8183 display usecase BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31517/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..950dca4 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,31 @@ setup_usb_host(); } +static void display_startup(void) +{ + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "Starting display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Gerrit-Change-Number: 31517 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019