New subject: Change in ...coreboot[master]: mediatek/mt8183: add dsi driver for mt8183

23 Feb 2019

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31591
Change subject: mediaek/mt8183: add dsi driver for mt8183
......................................................................
mediaek/mt8183: add dsi driver for mt8183
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
---
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/dsi.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/dsi.h
4 files changed, 957 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31591/1

diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index b7e2ca4..02eaf6b 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -41,6 +41,7 @@
 ramstage-y += auxadc.c
 ramstage-y += ../common/cbmem.c emi.c
 ramstage-y += ddp.c
+ramstage-y += dsi.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
new file mode 100644
index 0000000..f96d847
--- /dev/null
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -0,0 +1,470 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/dsi.h>
+#include <timer.h>
+
+static void mipi_write32(void *a, uint32_t offset, uint32_t v)
+{
+	write32(a + offset, v);
+}
+
+static void mipi_clrsetbits_le32(void *a, uint32_t offset, uint32_t m, uint32_t v)
+{
+	clrsetbits_le32(a + offset, m, v);
+}
+
+static void mipi_clrbits_le32(void *a, uint32_t offset, uint32_t m)
+{
+	clrbits_le32(a + offset, m);
+}
+
+static void mipi_setbits_le32(void *a, uint32_t offset, uint32_t m)
+{
+	setbits_le32(a + offset, m);
+}
+
+static void dsi_write32(void *a, uint32_t v)
+{
+	write32(a, v);
+}
+
+static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
+{
+	clrsetbits_le32(a, m, v);
+}
+
+static void dsi_clrbits_le32(void *a, uint32_t m)
+{
+	clrbits_le32(a, m);
+}
+
+static void dsi_setbits_le32(void *a, uint32_t m)
+{
+	setbits_le32(a, m);
+}
+
+static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
+				   const struct edid *edid, struct mtk_phy_timing *phy_timing)
+{
+	unsigned int txdiv, txdiv0, txdiv1;
+	u64 pcw;
+	int data_rate;
+	u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
+	u64 total_bits;
+
+	switch (format) {
+	case MIPI_DSI_FMT_RGB565:
+		bit_per_pixel = 16;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		bit_per_pixel = 18;
+		break;
+	case MIPI_DSI_FMT_RGB888:
+	default:
+		bit_per_pixel = 24;
+		break;
+	}
+
+	htotal = edid->mode.hbl + edid->mode.ha;
+	htotal_bits = htotal * bit_per_pixel;
+
+	overhead_cycles = 2 * phy_timing->lpx + phy_timing->da_hs_prepare +
+			  phy_timing->da_hs_zero + phy_timing->da_hs_trail +
+			  phy_timing->da_hs_exit + 1;
+
+	overhead_bits = overhead_cycles * 8U;
+	total_bits = htotal_bits + overhead_bits;
+
+	data_rate = (u64)(edid->mode.pixel_clock * 1000 * total_bits) / (htotal * lanes);
+
+	printk(BIOS_ERR, "data_rate: %u bps\n", data_rate);
+
+	if (data_rate >= 2000000000) {
+		txdiv = 1;
+		txdiv0 = 0;
+		txdiv1 = 0;
+	} else if (data_rate >= 1000000000) {
+		txdiv = 2;
+		txdiv0 = 1;
+		txdiv1 = 0;
+	} else if (data_rate >= 500000000) {
+		txdiv = 4;
+		txdiv0 = 2;
+		txdiv1 = 0;
+	} else if (data_rate > 250000000) {
+		txdiv = 8;
+		txdiv0 = 3;
+		txdiv1 = 0;
+	} else if (data_rate >= 125000000) {
+		txdiv = 16;
+		txdiv0 = 4;
+		txdiv1 = 0;
+	} else {
+		printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "
+		       "pixel clock (%u), bpp (%u), and number of lanes (%u)\n",
+		       data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes);
+		return -1;
+	}
+
+	mipi_clrbits_le32(mipi_tx, MIPITX_PLL_CON4, BIT(11) | BIT(10));
+
+	mipi_setbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+	udelay(30);
+	mipi_clrbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+
+	pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)) << 24;
+	pcw /= 26;
+
+	mipi_write32(mipi_tx, MIPITX_PLL_CON0, pcw);
+	mipi_clrsetbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
+				txdiv0 << 8);
+	udelay(30);
+	mipi_setbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+	/* BG_LPF_EN / BG_CORE_EN */
+	mipi_write32(mipi_tx, MIPITX_LANE_CON, 0x3FFF0180);
+	udelay(40);
+	mipi_write32(mipi_tx,  MIPITX_LANE_CON, 0x3FFF00c0);
+
+	/* Switch OFF each Lane */
+	mipi_clrbits_le32(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+	mipi_clrbits_le32(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+	mipi_clrbits_le32(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+	mipi_clrbits_le32(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+	mipi_clrbits_le32(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+	mipi_setbits_le32(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+
+	return data_rate;
+}
+
+static void mtk_dsi_phy_timconfig(u32 data_rate, struct mtk_phy_timing *phy_timing)
+{
+	u32 timcon0, timcon1, timcon2, timcon3;
+
+	timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |
+		  phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;
+	timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 |
+		  phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24;
+	timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 |
+		  phy_timing->clk_hs_trail << 24;
+	timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 |
+		  phy_timing->clk_hs_exit << 16;
+
+	dsi_write32(&dsi->dsi_phy_timecon0, timcon0);
+	dsi_write32(&dsi->dsi_phy_timecon1, timcon1);
+	dsi_write32(&dsi->dsi_phy_timecon2, timcon2);
+	dsi_write32(&dsi->dsi_phy_timecon3, timcon3);
+}
+
+static void mtk_dsi_reset(void)
+{
+	dsi_setbits_le32(&dsi->dsi_con_ctrl, 3);
+	dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1);
+}
+
+static void mtk_dsi_clk_hs_mode_enable(void)
+{
+	dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN);
+}
+
+static void mtk_dsi_clk_hs_mode_disable(void)
+{
+	dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN);
+}
+
+static void mtk_dsi_set_mode(u32 mode_flags)
+{
+	u32 tmp_reg1 = 0;
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+		tmp_reg1 = SYNC_PULSE_MODE;
+
+		if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+			tmp_reg1 = BURST_MODE;
+
+		if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+			tmp_reg1 = SYNC_PULSE_MODE;
+	}
+
+	dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1);
+}
+
+static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes,
+				   const struct edid *edid, struct mtk_phy_timing *phy_timing)
+{
+	u32 ui, cycle_time, data_rate;
+	u32 bit_per_pixel;
+
+	switch (format) {
+	case MIPI_DSI_FMT_RGB565:
+		bit_per_pixel = 16;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		bit_per_pixel = 18;
+		break;
+	case MIPI_DSI_FMT_RGB888:
+	default:
+		bit_per_pixel = 24;
+		break;
+	}
+
+	data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes;
+
+	ui = 1000 / (data_rate / 1000) + 1U;
+	cycle_time = 8000 / (data_rate / 1000) + 1U;
+
+	phy_timing->lpx = DIV_ROUND_UP(0x50, cycle_time);
+	phy_timing->da_hs_prepare = DIV_ROUND_UP((0x40 + 0x5 * ui), cycle_time);
+	phy_timing->da_hs_zero = DIV_ROUND_UP((0xc8 + 0x0a * ui), cycle_time);
+	phy_timing->da_hs_trail = DIV_ROUND_UP(((0x4 * ui) + 0x50), cycle_time);
+
+	if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare)
+		phy_timing->da_hs_zero -= phy_timing->da_hs_prepare;
+
+	phy_timing->ta_go = 4U * phy_timing->lpx;
+	phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;
+	phy_timing->ta_get = 5U * phy_timing->lpx;
+	phy_timing->da_hs_exit = 2U * phy_timing->lpx;
+
+	phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time);
+	phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU;
+
+	phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time);
+	phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time);
+	phy_timing->clk_hs_exit = 2U * phy_timing->lpx;
+}
+
+static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
+{
+	u32 tmp_reg = 0;
+
+	switch (lanes) {
+	case 1:
+		tmp_reg = 1 << 2;
+		break;
+	case 2:
+		tmp_reg = 3 << 2;
+		break;
+	case 3:
+		tmp_reg = 7 << 2;
+		break;
+	case 4:
+	default:
+		tmp_reg = 0xf << 2;
+		break;
+	}
+
+	tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+	tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
+	dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg);
+}
+
+static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
+				      const struct edid *edid)
+{
+	u32 hsync_active_byte;
+	u32 hbp_byte;
+	u32 hfp_byte;
+	u32 vbp_byte;
+	u32 vfp_byte;
+	u32 bpp;
+	u32 packet_fmt;
+	u32 hactive;
+
+	if (format == MIPI_DSI_FMT_RGB565)
+		bpp = 2;
+	else
+		bpp = 3;
+
+	vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
+		   edid->mode.vborder;
+	vfp_byte = edid->mode.vso - edid->mode.vborder;
+
+
+	dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw);
+	dsi_write32(&dsi->dsi_vbp_nl, vbp_byte);
+	dsi_write32(&dsi->dsi_vfp_nl, vfp_byte);
+	dsi_write32(&dsi->dsi_vact_nl, edid->mode.va);
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+		hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+			    edid->mode.hborder) * bpp - 10;
+	else
+		hbp_byte = (edid->mode.hbl - edid->mode.hso -
+			    edid->mode.hborder) * bpp - 10;
+
+	hsync_active_byte = edid->mode.hspw * bpp - 10;
+	hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12;
+
+	dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte);
+	dsi_write32(&dsi->dsi_hbp_wc, hbp_byte);
+	dsi_write32(&dsi->dsi_hfp_wc, hfp_byte);
+
+	switch (format) {
+	case MIPI_DSI_FMT_RGB888:
+		packet_fmt = PACKED_PS_24BIT_RGB888;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		packet_fmt = LOOSELY_PS_18BIT_RGB666;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		packet_fmt = PACKED_PS_18BIT_RGB666;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		packet_fmt = PACKED_PS_16BIT_RGB565;
+		break;
+	default:
+		packet_fmt = PACKED_PS_24BIT_RGB888;
+		break;
+	}
+
+	hactive = edid->mode.ha;
+	packet_fmt |= (hactive * bpp) & DSI_PS_WC;
+
+	dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt);
+	dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive);
+}
+
+static void mtk_dsi_start(void)
+{
+	dsi_write32(&dsi->dsi_start, 0);
+	dsi_write32(&dsi->dsi_start, 1);
+}
+
+static void mtk_dsi_cmdq(u8 *data, u8 len)
+{
+	struct stopwatch sw;
+	u8 *tx_buf = data;
+	u8 cmdq_size;
+	u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0;
+
+	switch (len) {
+	case 0:
+		return;
+
+	case 1:
+		type = MIPI_DSI_DCS_SHORT_WRITE;
+		break;
+
+	case 2:
+		type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+		break;
+
+	default:
+		type = MIPI_DSI_DCS_LONG_WRITE;
+		break;
+	}
+
+	if (MTK_DSI_HOST_IS_READ(type))
+		config = BTA;
+	else
+		config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+	if (len > 2) {
+		cmdq_size = 1 + (len + 3) / 4;
+		cmdq_off = 4;
+		cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+		reg_val = (len << 16) | (type << 8) | config;
+	} else {
+		cmdq_size = 1;
+		cmdq_off = 2;
+		cmdq_mask = CONFIG | DATA_ID;
+		reg_val = (type << 8) | config;
+	}
+
+	for (i = 0; i < len; i++)
+		dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)),
+			     (0xff << (((i + cmdq_off) & 3) * 8)),
+			     tx_buf[i] << (((i + cmdq_off) & 3) * 8));
+
+	dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val);
+	dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size);
+	dsi_write32(&dsi->dsi_intsta, 0);
+	mtk_dsi_start();
+
+	stopwatch_init_usecs_expire(&sw, 400);
+	do {
+		intsta_0 = read32(&dsi->dsi_intsta);
+		if (intsta_0 & CMD_DONE_INT_FLAG)
+			break;
+		udelay(4);
+	} while (!stopwatch_expired(&sw));
+
+	if (!(intsta_0 & CMD_DONE_INT_FLAG))
+		printk(BIOS_ERR, "dsi DONE INT Timeout\n");
+
+	dsi_write32(&dsi->dsi_start, 0);
+}
+
+static void push_table(struct lcm_init_table *init_cmd, u32 count)
+{
+	u32 cmd, i;
+
+	for (i = 0; i  < count; i++) {
+		cmd = init_cmd[i].cmd;
+
+		switch (cmd) {
+		case DELAY_CMD:
+			mdelay(init_cmd[i].cmd);
+			break;
+
+		case END_OF_TABLE:
+			break;
+
+		case INIT_CMD:
+		default:
+			mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len);
+			break;
+		}
+	}
+}
+
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+		 const struct edid *edid, struct lcm_init_table *init_cmd, u32 count)
+{
+	int data_rate;
+	struct mtk_phy_timing phy_timing;
+
+	mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing);
+
+	data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid, &phy_timing);
+
+	if (data_rate < 0)
+		return -1;
+
+	mtk_dsi_reset();
+	dsi_write32(&dsi->dsi_force_commit, 3);
+	mtk_dsi_phy_timconfig(data_rate, &phy_timing);
+	mtk_dsi_rxtx_control(mode_flags, lanes);
+	mtk_dsi_clk_hs_mode_disable();
+	mtk_dsi_config_vdo_timing(mode_flags, format, edid);
+	mtk_dsi_clk_hs_mode_enable();
+	mtk_dsi_set_mode(0);
+	push_table(init_cmd, count);
+	mtk_dsi_set_mode(mode_flags);
+	mtk_dsi_start();
+
+	return 0;
+}
+
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index 88653eb..75202dd 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -47,6 +47,7 @@
    IOCFG_RT_BASE		= IO_PHYS + 0x01C50000,
    IOCFG_RM_BASE		= IO_PHYS + 0x01D20000,
    IOCFG_RB_BASE		= IO_PHYS + 0x01D30000,
+	MIPITX_BASE		= IO_PHYS + 0x01E50000,
    IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
    IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
    IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,
@@ -64,6 +65,7 @@
    DISP_AAL0_BASE          = IO_PHYS + 0x04010000,
    DISP_GAMMA0_BASE        = IO_PHYS + 0x04011000,
    DISP_DITHER0_BASE       = IO_PHYS + 0x04012000,
+	DSI_BASE		= IO_PHYS + 0x04014000,
    DISP_MUTEX_BASE         = IO_PHYS + 0x04016000,
    SMI_LARB0               = IO_PHYS + 0x04017000,
    SMI_BASE		= IO_PHYS + 0x04019000,
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000..7b74478
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,484 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_REG_H_
+#define _DSI_REG_H_
+
+#include <edid.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+	MIPI_DSI_FMT_RGB888,
+	MIPI_DSI_FMT_RGB666,
+	MIPI_DSI_FMT_RGB666_PACKED,
+	MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+	MIPI_DSI_MODE_VIDEO = BIT(0),
+	/* video burst mode */
+	MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+	/* video pulse mode */
+	MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+	/* enable auto vertical count mode */
+	MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+	/* enable hsync-end packets in vsync-pulse and v-porch area */
+	MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+	/* disable hfront-porch area */
+	MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+	/* disable hback-porch area */
+	MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+	/* disable hsync-active area */
+	MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+	/* flush display FIFO on vsync pulse */
+	MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+	/* disable EoT packets in HS mode */
+	MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+	/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+	MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+	/* transmit data in low power */
+	MIPI_DSI_MODE_LPM = BIT(11)
+};
+
+struct dsi_regs {
+	u32 dsi_start;
+	u8 reserved0[4];
+	u32 dsi_inten;
+	u32 dsi_intsta;
+	u32 dsi_con_ctrl;
+	u32 dsi_mode_ctrl;
+	u32 dsi_txrx_ctrl;
+	u32 dsi_psctrl;
+	u32 dsi_vsa_nl;
+	u32 dsi_vbp_nl;
+	u32 dsi_vfp_nl;
+	u32 dsi_vact_nl;
+	u32 dsi_lfr_con;
+	u32 dsi_lfr_sta;
+	u32 dsi_size_con;
+	u32 dsi_vfp_early_stop;
+	u32 reserved1[4];
+	u32 dsi_hsa_wc;
+	u32 dsi_hbp_wc;
+	u32 dsi_hfp_wc;
+	u32 dsi_bllp_wc;
+	u32 dsi_cmdq_size;
+	u32 dsi_hstx_cklp_wc;
+	u8 reserved2[156];
+	u32 dsi_phy_lccon;
+	u32 dsi_phy_ld0con;
+	u8 reserved3[4];
+	u32 dsi_phy_timecon0;
+	u32 dsi_phy_timecon1;
+	u32 dsi_phy_timecon2;
+	u32 dsi_phy_timecon3;
+	u8 reserved4[16];
+	u32 dsi_vm_cmd_con;
+	u8 reserved5[92];
+	u32 dsi_force_commit;
+	u8 reserved6[108];
+	u32 dsi_cmdq0;
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq0, 0x200);
+static struct dsi_regs *const dsi = (void *)DSI_BASE;
+
+#define DELAY_CMD 0
+#define END_OF_TABLE 1
+#define INIT_CMD 2
+
+struct lcm_init_table {
+	u32 cmd;
+	u32 len;
+	u8 data[64];
+};
+
+struct mtk_phy_timing {
+	u8 lpx;
+	u8 da_hs_prepare;
+	u8 da_hs_zero;
+	u8 da_hs_trail;
+
+	u8 ta_go;
+	u8 ta_sure;
+	u8 ta_get;
+	u8 da_hs_exit;
+
+	u8 clk_hs_zero;
+	u8 clk_hs_trail;
+
+	u8 clk_hs_prepare;
+	u8 clk_hs_post;
+	u8 clk_hs_exit;
+};
+
+/* DSI_INTSTA */
+enum {
+	LPRX_RD_RDY_INT_FLAG = BIT(0),
+	CMD_DONE_INT_FLAG    = BIT(1),
+	TE_RDY_INT_FLAG      = BIT(2),
+	VM_DONE_INT_FLAG     = BIT(3),
+	EXT_TE_RDY_INT_FLAG  = BIT(4),
+	DSI_BUSY             = BIT(31),
+};
+
+/* DSI_CON_CTRL */
+enum {
+	DSI_RESET = BIT(0),
+	DSI_EN = BIT(1),
+	DSI_DUAL = BIT(4),
+};
+
+/* DSI_MODE_CTRL */
+enum {
+	MODE = 3,
+	CMD_MODE = 0,
+	SYNC_PULSE_MODE = 1,
+	SYNC_EVENT_MODE = 2,
+	BURST_MODE = 3,
+	FRM_MODE = BIT(16),
+	MIX_MODE = BIT(17)
+};
+
+/* DSI_PSCTRL */
+enum {
+	DSI_PS_WC = 0x3fff,
+	DSI_PS_SEL = (3 << 16),
+	PACKED_PS_16BIT_RGB565 = (0 << 16),
+	LOOSELY_PS_18BIT_RGB666 = (1 << 16),
+	PACKED_PS_18BIT_RGB666 = (2 << 16),
+	PACKED_PS_24BIT_RGB888 = (3 << 16)
+};
+
+/* DSI_CMDQ_SIZE */
+enum {
+	CMDQ_SIZE = 0x3f,
+};
+
+/* DSI_PHY_LCCON */
+enum {
+	LC_HS_TX_EN = BIT(0),
+	LC_ULPM_EN = BIT(1),
+	LC_WAKEUP_EN = BIT(2)
+};
+
+/*DSI_PHY_LD0CON */
+enum {
+	LD0_RM_TRIG_EN = BIT(0),
+	LD0_ULPM_EN = BIT(1),
+	LD0_WAKEUP_EN = BIT(2)
+};
+
+enum {
+	LPX = (0xff << 0),
+	HS_PRPR = (0xff << 8),
+	HS_ZERO = (0xff << 16),
+	HS_TRAIL = (0xff << 24)
+};
+
+enum {
+	TA_GO = (0xff << 0),
+	TA_SURE = (0xff << 8),
+	TA_GET = (0xff << 16),
+	DA_HS_EXIT = (0xff << 24)
+};
+
+enum {
+	CONT_DET = (0xff << 0),
+	CLK_ZERO = (0xf << 16),
+	CLK_TRAIL = (0xff << 24)
+};
+
+enum {
+	CLK_HS_PRPR = (0xff << 0),
+	CLK_HS_POST = (0xff << 8),
+	CLK_HS_EXIT = (0xf << 16)
+};
+
+/* DSI_VM_CMD_CON */
+enum {
+	VM_CMD_EN = BIT(0),
+	TS_VFP_EN = BIT(5),
+};
+
+/* DSI_CMDQ0 */
+enum {
+	CONFIG         = (0xff << 0),
+	SHORT_PACKET   = 0,
+	LONG_PACKET    = 2,
+	BTA            = BIT(2),
+	DATA_ID        = (0xff << 8),
+	DATA_0         = (0xff << 16),
+	DATA_1         = (0xff << 24),
+};
+
+#define MIPITX_LANE_CON		0x000c
+#define MIPITX_PLL_PWR		0x0028
+#define MIPITX_PLL_CON0		0x002c
+#define MIPITX_PLL_CON1		0x0030
+#define MIPITX_PLL_CON2		0x0034
+#define MIPITX_PLL_CON3		0x0038
+#define MIPITX_PLL_CON4		0x003c
+#define MIPITX_D2_SW_CTL_EN	0x0144
+#define MIPITX_D0_SW_CTL_EN	0x0244
+#define MIPITX_CK_CKMODE_EN	0x0328
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define MIPITX_CK_SW_CTL_EN	0x0344
+#define MIPITX_D1_SW_CTL_EN	0x0444
+#define MIPITX_D3_SW_CTL_EN	0x0544
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
+
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 dsi_con;
+	u32 dsi_clock_lane;
+	u32 dsi_data_lane[4];
+	u8 reserved0[40];
+	u32 dsi_top_con;
+	u32 dsi_bg_con;
+	u8 reserved1[8];
+	u32 dsi_pll_con0;
+	u32 dsi_pll_con1;
+	u32 dsi_pll_con2;
+	u32 dsi_pll_con3;
+	u32 dsi_pll_chg;
+	u32 dsi_pll_top;
+	u32 dsi_pll_pwr;
+	u8 reserved2[4];
+	u32 dsi_rgs;
+	u32 dsi_gpi_en;
+	u32 dsi_gpi_pull;
+	u32 dsi_phy_sel;
+	u32 dsi_sw_ctrl_en;
+	u32 dsi_sw_ctrl_con0;
+	u32 dsi_sw_ctrl_con1;
+	u32 dsi_sw_ctrl_con2;
+	u32 dsi_dbg_con;
+	u32 dsi_dbg_out;
+	u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
+
+/* MIPITX_DSI_CON */
+enum {
+	RG_DSI_LDOCORE_EN = BIT(0),
+	RG_DSI_CKG_LDOOUT_EN = BIT(1),
+	RG_DSI_BCLK_SEL = (3 << 2),
+	RG_DSI_LD_IDX_SEL = (7 << 4),
+	RG_DSI_PHYCLK_SEL = (2 << 8),
+	RG_DSI_DSICLK_FREQ_SEL = BIT(10),
+	RG_DSI_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI_CLOCK_LANE */
+enum {
+	LDOOUT_EN = BIT(0),
+	CKLANE_EN = BIT(1),
+	IPLUS1 = BIT(2),
+	LPTX_IPLUS2 = BIT(3),
+	LPTX_IMINUS = BIT(4),
+	LPCD_IPLUS = BIT(5),
+	LPCD_IMLUS = BIT(6),
+	RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+	RG_DSI_LNT_INTR_EN = BIT(0),
+	RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+	RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+	RG_DSI_LNT_TESTMODE_EN = BIT(3),
+	RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+	RG_DSI_LNT_AIO_SEL = (7 << 8),
+	RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+	RG_DSI_DEBUG_INPUT_EN = BIT(12),
+	RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+	RG_DSI_BG_CORE_EN = BIT(0),
+	RG_DSI_BG_CKEN = BIT(1),
+	RG_DSI_BG_DIV = (0x3 << 2),
+	RG_DSI_BG_FAST_CHARGE = BIT(4),
+	RG_DSI_V12_SEL = (7 << 5),
+	RG_DSI_V10_SEL = (7 << 8),
+	RG_DSI_V072_SEL = (7 << 11),
+	RG_DSI_V04_SEL = (7 << 14),
+	RG_DSI_V032_SEL = (7 << 17),
+	RG_DSI_V02_SEL = (7 << 20),
+	rsv_23 = BIT(23),
+	RG_DSI_BG_R1_TRIM = (0xf << 24),
+	RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+	RG_DSI_MPPLL_PLL_EN = BIT(0),
+	RG_DSI_MPPLL_PREDIV = (3 << 1),
+	RG_DSI_MPPLL_TXDIV0 = (3 << 3),
+	RG_DSI_MPPLL_TXDIV1 = (3 << 5),
+	RG_DSI_MPPLL_POSDIV = (7 << 7),
+	RG_DSI_MPPLL_MONVC_EN = BIT(10),
+	RG_DSI_MPPLL_MONREF_EN = BIT(11),
+	RG_DSI_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+	RG_DSI_MPPLL_SDM_FRA_EN = BIT(0),
+	RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+	RG_DSI_MPPLL_SDM_SSC_EN = BIT(2),
+	RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+	RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+	RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+	MIPI_DSI_V_SYNC_START				= 0x01,
+	MIPI_DSI_V_SYNC_END				= 0x11,
+	MIPI_DSI_H_SYNC_START				= 0x21,
+	MIPI_DSI_H_SYNC_END				= 0x31,
+
+	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
+	MIPI_DSI_COLOR_MODE_ON				= 0x12,
+	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
+	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
+
+	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
+	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
+	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
+
+	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
+	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
+	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
+
+	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
+	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
+
+	MIPI_DSI_DCS_READ				= 0x06,
+
+	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
+
+	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
+
+	MIPI_DSI_NULL_PACKET				= 0x09,
+	MIPI_DSI_BLANKING_PACKET			= 0x19,
+	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
+	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
+
+	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
+	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+	MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT	= 0x02,
+	MIPI_DSI_RX_END_OF_TRANSMISSION			= 0x08,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE	= 0x11,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE	= 0x12,
+	MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE		= 0x1a,
+	MIPI_DSI_RX_DCS_LONG_READ_RESPONSE		= 0x1c,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE	= 0x21,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE	= 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+	MIPI_DCS_NOP			= 0x00,
+	MIPI_DCS_SOFT_RESET		= 0x01,
+	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
+	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
+	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
+	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
+	MIPI_DCS_GET_DISPLAY_STATUS	= 0x09,
+	MIPI_DCS_GET_POWER_MODE		= 0x0A,
+	MIPI_DCS_GET_ADDRESS_MODE	= 0x0B,
+	MIPI_DCS_GET_PIXEL_FORMAT	= 0x0C,
+	MIPI_DCS_GET_DISPLAY_MODE	= 0x0D,
+	MIPI_DCS_GET_SIGNAL_MODE	= 0x0E,
+	MIPI_DCS_GET_DIAGNOSTIC_RESULT	= 0x0F,
+	MIPI_DCS_ENTER_SLEEP_MODE	= 0x10,
+	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
+	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
+	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
+	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
+	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
+	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
+	MIPI_DCS_SET_DISPLAY_OFF	= 0x28,
+	MIPI_DCS_SET_DISPLAY_ON		= 0x29,
+	MIPI_DCS_SET_COLUMN_ADDRESS	= 0x2A,
+	MIPI_DCS_SET_PAGE_ADDRESS	= 0x2B,
+	MIPI_DCS_WRITE_MEMORY_START	= 0x2C,
+	MIPI_DCS_WRITE_LUT		= 0x2D,
+	MIPI_DCS_READ_MEMORY_START	= 0x2E,
+	MIPI_DCS_SET_PARTIAL_AREA	= 0x30,
+	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
+	MIPI_DCS_SET_TEAR_OFF		= 0x34,
+	MIPI_DCS_SET_TEAR_ON		= 0x35,
+	MIPI_DCS_SET_ADDRESS_MODE	= 0x36,
+	MIPI_DCS_SET_SCROLL_START	= 0x37,
+	MIPI_DCS_EXIT_IDLE_MODE		= 0x38,
+	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
+	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
+	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
+	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
+	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
+	MIPI_DCS_GET_SCANLINE		= 0x45,
+	MIPI_DCS_READ_DDB_START		= 0xA1,
+	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
+};
+
+#define MTK_DSI_HOST_IS_READ(type) \
+	((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+	(type == MIPI_DSI_DCS_READ))
+
+extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+		 const struct edid *edid, struct lcm_init_table *init_cmd, u32 count);
+
+#endif
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Gerrit-Change-Number: 31591
Gerrit-PatchSet: 1
Gerrit-Owner: jitao shi jitao.shi@mediatek.com
Gerrit-Reviewer: Julius Werner jwerner@chromium.org
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: jitao shi jitao.shi@mediatek.com
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: mediaek/mt8183: add dsi driver for mt8183