Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29563
to look at the new patch set (#65).
Change subject: security/tpm: Fix TCPA log feature
......................................................................
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
A Documentation/security/index.md
M Documentation/security/vboot/measured_boot.md
M src/arch/x86/car.ld
M src/commonlib/include/commonlib/tcpa_log_serialized.h
M src/include/memlayout.h
M src/security/tpm/tspi.h
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/symbols.h
M src/security/vboot/vboot_crtm.c
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/imgtec/pistachio/include/soc/memlayout.ld
M src/soc/mediatek/mt8173/include/soc/memlayout.ld
M src/soc/mediatek/mt8183/include/soc/memlayout.ld
M src/soc/nvidia/tegra124/include/soc/memlayout.ld
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/samsung/exynos5250/include/soc/memlayout.ld
M util/cbmem/cbmem.c
19 files changed, 356 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/65
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Gerrit-Change-Number: 29563
Gerrit-PatchSet: 65
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Patrick Rudolph
Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newpatchset
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31748 )
Change subject: sb/amd: Use simple PCI IO config access
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/31748/1/src/southbridge/amd/rs780/rs780.c
File src/southbridge/amd/rs780/rs780.c:
https://review.coreboot.org/#/c/31748/1/src/southbridge/amd/rs780/rs780.c@39
PS1, Line 39: d0f1
this variable name threw me for a loop. i thought it was a literal
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4aa0669179d6b01ab0713fd2a8b3cf4baf6e572f
Gerrit-Change-Number: 31748
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Tue, 05 Mar 2019 15:22:43 +0000
Gerrit-HasComments: Yes
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Gerrit-MessageType: comment