coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: SMBIOS: Update Processor Information structure to v3.2.0
by HAOUAS Elyes (Code Review) 05 Mar '19

05 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31420 Change subject: SMBIOS: Update Processor Information structure to v3.2.0 ...................................................................... SMBIOS: Update Processor Information structure to v3.2.0 Change-Id: I1861615eff904f13029b8d038ffcf3de2d2bfc2a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31420/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 6498e64..2efd5f0 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -374,6 +374,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/31420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1861615eff904f13029b8d038ffcf3de2d2bfc2a Gerrit-Change-Number: 31420 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 05 Mar '19

05 Mar '19

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#5). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/acpi/jack_board.asl A src/mainboard/google/cyan/acpi/jack_detect.asl A src/mainboard/google/cyan/ssdtlpe.asl A src/mainboard/google/cyan/variants/banon/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/celes/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/kefka/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/relm/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/setzer/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/terra/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/ultima/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/lpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 23 files changed, 392 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Use new memory clearing API
by Paul Menzel (Code Review) 05 Mar '19

05 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31551 ) Change subject: drivers/intel/fsp1_0: Use new memory clearing API ...................................................................... Patch Set 8: (5 comments) https://review.coreboot.org/#/c/31551/8//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31551/8//COMMIT_MSG@10 PS8, Line 10: requested by security framework. Please add a blank line below. https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/Makefile.i… File src/drivers/intel/fsp1_0/Makefile.inc: https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/Makefile.i… PS8, Line 52: romstage-y += $(call strip_quotes,$(CONFIG_FSP_SRC_PATH)) Order it before ramstage? https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/fsp_util.c File src/drivers/intel/fsp1_0/fsp_util.c: https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/fsp_util.c… PS8, Line 84: STACK stack? https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/fsp_util.c… PS8, Line 89: int64_t Why not size_t? https://review.coreboot.org/#/c/31551/8/src/drivers/intel/fsp1_0/fsp_util.c… PS8, Line 92: free free_range so it doesn’t collide with the keyword? -- To view, visit https://review.coreboot.org/c/coreboot/+/31551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Gerrit-Change-Number: 31551 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 10:51:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Paul Menzel (Code Review) 05 Mar '19

05 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... Patch Set 7: (6 comments) Can you run your added code through clang-format? https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md File Documentation/arch/x86/pae.md: https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md@6 PS7, Line 6: ## Memory clearing helper functions Squash that into the commit before? https://review.coreboot.org/#/c/31550/7/Documentation/arch/x86/pae.md@17 PS7, Line 17: 4GiB Space after 4? https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… File src/arch/x86/include/arch/memory_clear.h: https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… PS7, Line 2: * This file is part of the coreboot project. : * : * Copyright (C) 2019 9elements Agency GmbH : * Copyright (C) 2019 Facebook Inc. : * : * Redistribution and use in source and binary forms, with or without : * modification, are permitted provided that the following conditions : * are met: : * 1. Redistributions of source code must retain the above copyright : * notice, this list of conditions and the following disclaimer. : * 2. Redistributions in binary form must reproduce the above copyright : * notice, this list of conditions and the following disclaimer in the : * documentation and/or other materials provided with the distribution. : * 3. The name of the author may not be used to endorse or promote products : * derived from this software without specific prior written permission. : * : * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND : * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE : * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE : * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT : * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY : * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF : * SUCH DAMAGE. Document in the commit message, why BSD(?) is used? https://review.coreboot.org/#/c/31550/7/src/arch/x86/include/arch/memory_cl… PS7, Line 29: * Remove this line? https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@35 PS7, Line 35: * Return 0 on success, 1 on error Use CB_SUCCESS, and CB_ERROR (`src/include/types.h`)? Error should be -1. https://review.coreboot.org/#/c/31550/7/src/arch/x86/memory_clear.c@75 PS7, Line 75: to too -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 10:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Paul Menzel (Code Review) 05 Mar '19

05 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... Patch Set 7: (10 comments) What about Rudolf’s suggestion on the mailing list? https://review.coreboot.org/#/c/31549/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31549/7//COMMIT_MSG@12 PS7, Line 12: Add Documentation. : Tested on wedge100s. : Takes less than 2 seconds to clear 8GiB of DRAM. Please format this as a list. Dots/periods can be removed from the first two items. https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md File Documentation/arch/x86/pae.md: https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md@4 PS7, Line 4: ``src/cpu/x86/pae/`` Isn’t one ` enough? https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md@13 PS7, Line 13: uint64_t Can’t this bee offset_t or size_t? https://review.coreboot.org/#/c/31549/7/Documentation/arch/x86/pae.md@18 PS7, Line 18: the *scratch memory* doesn't overlap with the range to be cleared. Please add a blank line below. https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c File src/cpu/x86/pae/pgtbl.c: https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@116 PS7, Line 116: are is https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@118 PS7, Line 118: are is https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@123 PS7, Line 123: * Document the return value? Use CB_SUCCESS macro? https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@128 PS7, Line 128: ssize_t offset; Why not `offset_t`? https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@132 PS7, Line 132: page-tables Above you spell it *pagetables*. I’d prefer *page tables* though. ;-) https://review.coreboot.org/#/c/31549/7/src/cpu/x86/pae/pgtbl.c@148 PS7, Line 148: * Point the page directory pointers at the page : * directories. Dosen’t this fit on one line? -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 10:43:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security: Add memory subfolder
by Paul Menzel (Code Review) 05 Mar '19

05 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 5: (8 comments) https://review.coreboot.org/#/c/31548/5//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31548/5//COMMIT_MSG@10 PS5, Line 10: Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by : platforms, that are able to clear all DRAM. : : Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user : selectable to always clear DRAM on non S3 boot. : : The function security_clear_dram_request tells the calling platform when : to wipe all DRAM. Will be extended by TEE frameworks. : : Add Documentation for the new security API. Enumerate these items? https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… File Documentation/security/memory_clearing.md: https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 14: bringup bring-up? https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 15: SoC device? https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 22: 4. All DRAM is cleared with zeros Can you elaborate, why 0 is the way to go and not something random? https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 26: platforms singular https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear… PS5, Line 27: call calls https://review.coreboot.org/#/c/31548/5/src/security/memory/Kconfig File src/security/memory/Kconfig: https://review.coreboot.org/#/c/31548/5/src/security/memory/Kconfig@30 PS5, Line 30: of additional security implementations in use. Please add a blank line below. https://review.coreboot.org/#/c/31548/5/src/security/memory/memory.c File src/security/memory/memory.c: https://review.coreboot.org/#/c/31548/5/src/security/memory/memory.c@28 PS5, Line 28: return 1; : : /* TODO: Add TEE environments here */ : : return 0; Use `true` and `false` as the type is `bool`? The macros are defined in `stdint.h`. -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 10:33:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by Paul Menzel (Code Review) 05 Mar '19

05 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31713 ) Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 10:25:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/lpe.c: Fix typo
by Frans Hendriks (Code Review) 05 Mar '19

05 Mar '19

Frans Hendriks has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30274 ) Change subject: src/soc/intel/braswell/lpe.c: Fix typo ...................................................................... Abandoned Incorrect correction of typo -- To view, visit https://review.coreboot.org/c/coreboot/+/30274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37d31932b75a42deedd8587905054818081d1634 Gerrit-Change-Number: 30274 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/intel/apollolake: Fix wrong IS_ENABLED test
by HAOUAS Elyes (Code Review) 05 Mar '19

05 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31760 Change subject: soc/intel/apollolake: Fix wrong IS_ENABLED test ...................................................................... soc/intel/apollolake: Fix wrong IS_ENABLED test Add missing "CONFIG_" to SOC_INTEL_COMMON_BLOCK_SGX. Change-Id: Id9b70e9552af282f4f378929987150e936a22487 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31760/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index d1c5f6f..a08f1f0 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -73,7 +73,7 @@ /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (IS_ENABLED(SOC_INTEL_COMMON_BLOCK_SGX) || + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) mca_configure(NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/31760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9b70e9552af282f4f378929987150e936a22487 Gerrit-Change-Number: 31760 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by David Guckian (Code Review) 05 Mar '19

05 Mar '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31713 ) Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 09:58:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2019