coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Use new memory clearing API
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Patrick Rudolph, Aaron Durbin, build bot (Jenkins), Patrick Georgi, Roy Wen, Huang Jin, York Yang, David Hendricks, Philipp Deppenwiese, David Guckian, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31551 to look at the new patch set (#8). Change subject: drivers/intel/fsp1_0: Use new memory clearing API ...................................................................... drivers/intel/fsp1_0: Use new memory clearing API Select PLATFORM_HAS_DRAM_CLEAR and clear all DRAM after FSP-M if requested by security framework. Preserve FSP below TSEG and STACK which resides at 16MiB. Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_0/Makefile.inc M src/drivers/intel/fsp1_0/fsp_util.c M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig M src/soc/intel/fsp_broadwell_de/fsp/Kconfig 5 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31551/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Gerrit-Change-Number: 31551 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by Werner Zeh (Code Review) 05 Mar '19

05 Mar '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31713 ) Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 08:56:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 62: (8 comments) https://review.coreboot.org/#/c/29563/62/Documentation/security/vboot/measu… File Documentation/security/vboot/measured_boot.md: https://review.coreboot.org/#/c/29563/62/Documentation/security/vboot/measu… PS62, Line 46: The second column is the hash of the raw data. The third column contains that seems important. Add a custom section what is measured. Answer the following questions: * Is compressed or uncompressed data measured? * which part of the CBFS file is measured? ** is the header measured, too? https://review.coreboot.org/#/c/29563/62/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/#/c/29563/62/src/arch/x86/car.ld@34 PS62, Line 34: /* Vboot measured boot TCPA log measurements . https://review.coreboot.org/#/c/29563/62/src/arch/x86/car.ld@35 PS62, Line 35: * needs to be transferred until CBMEM is available Needs https://review.coreboot.org/#/c/29563/62/src/arch/x86/car.ld@37 PS62, Line 37: #if IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY) why is it guarded by IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY) but the other linker script doesn't contain it? https://review.coreboot.org/#/c/29563/62/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/62/src/security/tpm/tspi/log.c@94 PS62, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, > line over 80 characters use new line for const uint8_t *digest https://review.coreboot.org/#/c/29563/62/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29563/62/src/security/vboot/vboot_crtm.c@20 PS62, Line 20: short description what it does https://review.coreboot.org/#/c/29563/62/src/security/vboot/vboot_crtm.c@25 PS62, Line 25: use an array and loop over fmap names https://review.coreboot.org/#/c/29563/62/src/security/vboot/vboot_crtm.c@78 PS62, Line 78: /* Clear TCPA PRERAM log */ better: Initialize TCPE PRERAM log. That it's cleared can be deviated from the function name. -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 62 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 08:47:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: UPSTREAM: mb/google/sarien/variants/arcada: Add GPIO H15 to enable BT
by Casper Chang (Code Review) 05 Mar '19

05 Mar '19

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31705 Change subject: UPSTREAM: mb/google/sarien/variants/arcada: Add GPIO H15 to enable BT ...................................................................... UPSTREAM: mb/google/sarien/variants/arcada: Add GPIO H15 to enable BT Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#). BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5 --- M 3rdparty/vboot M src/mainboard/google/sarien/variants/arcada/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31705/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 1e17774..a32c930 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 1e177741c3a9bfb8bd69a92b6d3bf4b25655a71f +Subproject commit a32c930e8c46424a3bba3c296fd78b3e60f50aeb diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index a29fd06..cfd35b9 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -214,7 +214,7 @@ /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), /* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), /* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5 Gerrit-Change-Number: 31705 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31713 ) Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/31713/1/src/drivers/intel/fsp1_0/fsp_util.c File src/drivers/intel/fsp1_0/fsp_util.c: https://review.coreboot.org/#/c/31713/1/src/drivers/intel/fsp1_0/fsp_util.c… PS1, Line 109: oid ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) > Once there is no external caller more for this function should we make it static and remove it from […] Done https://review.coreboot.org/#/c/31713/1/src/drivers/intel/fsp1_0/fsp_util.c… PS1, Line 113: if (Status == 0xFFFFFFFF) { > braces {} are not necessary for single statement blocks Done https://review.coreboot.org/#/c/31713/1/src/soc/intel/fsp_baytrail/fsp/chip… File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: https://review.coreboot.org/#/c/31713/1/src/soc/intel/fsp_baytrail/fsp/chip… PS1, Line 22: > This is still needed here (in chipset_fsp_early_init()), just add it back again. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 08:13:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security: Add memory subfolder
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 5: (7 comments) https://review.coreboot.org/#/c/31548/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31548/3//COMMIT_MSG@17 PS3, Line 17: TEE > What is that? explained https://review.coreboot.org/#/c/31548/3/Documentation/security/memory_clear… File Documentation/security/memory_clearing.md: https://review.coreboot.org/#/c/31548/3/Documentation/security/memory_clear… PS3, Line 19: 2. Code that is placed in DRAM might be skipped (FSP1.0) : 3. Stack that is placed in DRAM might be skipped (FSP1.0) > Maybe highlight that these are workarounds instead of […] Done https://review.coreboot.org/#/c/31548/3/Documentation/security/memory_clear… PS3, Line 37: As those regions are written on early boot and marked reserved from : OS point of view, it is unlikely that they contain secrets. : > Maybe keep it to technical/implementation details. I don't […] Done https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig File src/security/memory/Kconfig: https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@3 PS3, Line 3: ## Copyright (C) 2019 Facebook Inc. : ## Copyright (C) 2019 9elements Agency GmbH > Would be nice to split this into two patches to make […] That's difficult as I've split the original proof of concept code into smaller patches, not taking care of the authors. If you don't beat me to I'd leave it as is. https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.h File src/security/memory/memory.h: https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.h@4 PS3, Line 4: * Copyright (C) 2019 9elements Agency GmbH : * Copyright (C) 2019 Facebook Inc. > This might be a little hard to differentiate. See other copyright comment https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.h@17 PS3, Line 17: #include <stddef.h> > <stdbool.h> maybe? But we don't have it. This is covered […] Done https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.c File src/security/memory/memory.c: https://review.coreboot.org/#/c/31548/3/src/security/memory/memory.c@22 PS3, Line 22: USER > why all caps? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 08:12:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_0: Deduplicate code
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Werner Zeh, Patrick Rudolph, Huang Jin, York Yang, Jay Talbott, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31713 to look at the new patch set (#2). Change subject: drivers/intel/fsp1_0: Deduplicate code ...................................................................... drivers/intel/fsp1_0: Deduplicate code Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/include/soc/romstage.h M src/southbridge/intel/fsp_rangeley/romstage.h 8 files changed, 15 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31713/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Gerrit-Change-Number: 31713 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Kyösti Mälkki, Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31549 to look at the new patch set (#7). Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation. Tested on wedge100s. Takes less than 2 seconds to clear 8GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/pae.md M Documentation/security/memory_clearing.md M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 5 files changed, 148 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31549/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security: Add memory subfolder
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31548 to look at the new patch set (#5). Change subject: security: Add memory subfolder ...................................................................... security: Add memory subfolder Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/index.md A Documentation/security/index.md A Documentation/security/memory_clearing.md M src/security/Kconfig M src/security/Makefile.inc A src/security/memory/Kconfig A src/security/memory/Makefile.inc A src/security/memory/memory.c A src/security/memory/memory.h 9 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31548/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Kyösti Mälkki (Code Review) 05 Mar '19

05 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 2: Code-Review-2 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 07:08:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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2020

2019

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2013

coreboot-gerrit March 2019