coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: qcs405: Add Timer support
by Name of user not set (Code Review) 06 Mar '19

06 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29952 to look at the new patch set (#13). Change subject: qcs405: Add Timer support ...................................................................... qcs405: Add Timer support Init frequency to 19.2 MHz TEST=build Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/timer.c 2 files changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29952/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/29952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Gerrit-Change-Number: 29952 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by Name of user not set (Code Review) 06 Mar '19

06 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29950 to look at the new patch set (#13). Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... soc/qualcomm/qcs405: Add MMU support Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/symbols.h A src/soc/qualcomm/qcs405/mmu.c 5 files changed, 85 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29950/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Name of user not set (Code Review) 06 Mar '19

06 Mar '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29949 to look at the new patch set (#12). Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... mainboard/google/mistral: Add support for Mistral Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/Kconfig.name A src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/board_info.txt A src/mainboard/google/mistral/bootblock.c A src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/chromeos.fmd A src/mainboard/google/mistral/devicetree.cb A src/mainboard/google/mistral/mainboard.c A src/mainboard/google/mistral/memlayout.ld 10 files changed, 231 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29949/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Patrick Rudolph (Code Review) 06 Mar '19

06 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23178 ) Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/23178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Gerrit-Change-Number: 23178 Gerrit-PatchSet: 27 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Mar 2019 16:27:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Remove DEFAULT_PCIEXBAR alias
by Patrick Rudolph (Code Review) 06 Mar '19

06 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31758 ) Change subject: Remove DEFAULT_PCIEXBAR alias ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Gerrit-Change-Number: 31758 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 16:21:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/io.h: Drop includes in fam10 romstages
by Patrick Georgi (Code Review) 06 Mar '19

06 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31696 ) Change subject: arch/io.h: Drop includes in fam10 romstages ...................................................................... arch/io.h: Drop includes in fam10 romstages These files suffer from .c includes. Change-Id: Id836595290922fcbd108a5ed576fc640b2530711 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31696 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/southbridge/amd/amd8111/amd8111_smbus.h M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/amd8111/early_smbus.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/broadcom/bcm5785/early_smbus.c M src/southbridge/broadcom/bcm5785/smbus.h M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/ck804/smbus.h M src/southbridge/nvidia/mcp55/early_setup_car.c M src/southbridge/nvidia/mcp55/smbus.h 29 files changed, 12 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index bb830b2..92002a6 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 217e292..67b90a4 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index d4a9fe3..a90bac6 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index ae778f2..f6faf17 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -21,7 +21,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index db81a93..ffe283c 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index a9117f7..3246bdd 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 0fe961f..899814f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 8e9fedb..f415038 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 9745895..63a4509 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 19b6022..497acaa 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9119041..a974422 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 77f85d9..734679d 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 95ac19e..588203c 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0b073ed..ab9b0a4 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <arch/cpu.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 49fec53..d688cc9 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 3e09da0..bf3528d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <arch/cpu.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 7ca47b4..30241a0 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 589e06d..084fc48 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 33856b3..7386965 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/smbus_def.h> #define SMBGSTATUS 0xe0 diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index 1754d23..8b12d83 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/pci_ids.h> #include <reset.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index 15a03f5..2e6781a 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/pci_ops.h> #include "amd8111_smbus.h" diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index d7a6b88..6a575e3 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -16,6 +16,7 @@ #ifndef _SB800_EARLY_SETUP_C_ #define _SB800_EARLY_SETUP_C_ +#include <arch/io.h> #include <reset.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/reset.h> diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index ee9967d..a8a38f2 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <reset.h> #include <southbridge/amd/common/reset.h> #include "bcm5785.h" diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 260f1fc..bcbfb12 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/pci_ops.h> #include "smbus.h" diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index 1c3c9d7..657d97d 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/smbus_def.h> #define SMBHSTSTAT 0x0 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 25faa35..bc1e781 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <southbridge/amd/common/reset.h> #include "ck804.h" diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 40b8cb7..cec62b3 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/smbus_def.h> #define SMBHSTSTAT 0x1 diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index cc5e539..582cb52 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include <arch/io.h> + #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 274ccfe..f270452 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -17,6 +17,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/smbus_def.h> #define SMBHSTSTAT 0x1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id836595290922fcbd108a5ed576fc640b2530711 Gerrit-Change-Number: 31696 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: arch/io.h: Drop includes in fam10 romstages
by Patrick Georgi (Code Review) 06 Mar '19

06 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31696 ) Change subject: arch/io.h: Drop includes in fam10 romstages ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id836595290922fcbd108a5ed576fc640b2530711 Gerrit-Change-Number: 31696 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 16:19:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Makefile: Reduce scope of oprom include paths
by Patrick Georgi (Code Review) 06 Mar '19

06 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31694 ) Change subject: Makefile: Reduce scope of oprom include paths ...................................................................... Makefile: Reduce scope of oprom include paths Change-Id: Ibaa5428df1832d3f18946d456fb0b6d2fff65c32 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31694 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/Makefile.inc b/Makefile.inc index 6ae3e76..36c05db 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -382,7 +382,6 @@ endif CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj) -CPPFLAGS_common += -Isrc/device/oprom/include VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h @@ -391,6 +390,10 @@ CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" +ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL)$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y) +CPPFLAGS_ramstage += -Isrc/device/oprom/include +endif + CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -- To view, visit https://review.coreboot.org/c/coreboot/+/31694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa5428df1832d3f18946d456fb0b6d2fff65c32 Gerrit-Change-Number: 31694 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: Makefile: Reduce scope of oprom include paths
by Patrick Georgi (Code Review) 06 Mar '19

06 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31694 ) Change subject: Makefile: Reduce scope of oprom include paths ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa5428df1832d3f18946d456fb0b6d2fff65c32 Gerrit-Change-Number: 31694 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Mar 2019 16:18:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: device/pci: Place MMCONF_BASE_ADDRESS in const variable
by Aaron Durbin (Code Review) 06 Mar '19

06 Mar '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Place MMCONF_BASE_ADDRESS in const variable ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/31752/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31752/2//COMMIT_MSG@10 PS2, Line 10: optimisation, specially when multiple registers on In what way? Such that register is loaded once? Isn't the constant folding already done? This feels like it's just trying to fight against the compiler. https://review.coreboot.org/#/c/31752/2/src/include/device/pci_mmio_cfg.h File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/#/c/31752/2/src/include/device/pci_mmio_cfg.h@24 PS2, Line 24: extern const uintptr_t var_mmconf_base; What's the point of this? If it's const it can't be changed, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Mar 2019 16:06:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019