Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 )
Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster…
File src/soc/intel/braswell/southcluster.c:
https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster…
PS6, Line 621:
> Matt, can you test if serirq is enabled by the Google blob?
easiest way to test/verify this?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 )
Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
......................................................................
Patch Set 6:
(1 comment)
Please makes this a `chip.h` setting, as this doesn't
make much sense as a Kconfig option (I'm about to
update older platforms regarding this). cf. CB:31596
AIUI, it should be enabled for the Google boards as
they use it for their EC. Which makes me wonder if
their FSP binary enables it.
https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster…
File src/soc/intel/braswell/southcluster.c:
https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster…
PS6, Line 621:
This was added and removed and added back on the cros firmware
branches. ^^
If serirq really isn't enabled, this shouldn't have made a
difference.... Matt, can you test if serirq is enabled by
the Google blob?
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31751 )
Change subject: device/pci_ops: Inline PCI config accessors for ramstage
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/31751/1/src/device/pci_ops.c
File src/device/pci_ops.c:
https://review.coreboot.org/#/c/31751/1/src/device/pci_ops.c@1
PS1, Line 1: /*
> Followups already add stuff in this file and the name seems fine for the purpose.
yes, i saw this as i walked the stack.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31751 )
Change subject: device/pci_ops: Inline PCI config accessors for ramstage
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31751/1/src/device/pci_ops.c
File src/device/pci_ops.c:
https://review.coreboot.org/#/c/31751/1/src/device/pci_ops.c@1
PS1, Line 1: /*
> Can we just remove this file?
Followups already add stuff in this file and the name seems fine for the purpose.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 )
Change subject: [WIP]arch/x86/postcar: Add x86_64 support
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S
File src/arch/x86/exit_car.S:
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@118
PS4, Line 118: pop %ebx /* Number to clear */
> It's fine like this. […]
Something like this might do it, if we want to:
pop_edx_eax
mov %al, %bl /* Number to clear */
mov %dl, %bh /* Number to set */
test %bl, %bl
jz 2f
...
dec %bl
jnz 1b
2:
test %bh, %bh
jz 2f
...
dec %bh
jnz 1b
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 )
Change subject: [WIP]arch/x86/postcar: Add x86_64 support
......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S
File src/arch/x86/exit_car.S:
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@32
PS4, Line 32: .macro pop_mtrr
Maybe pop_edx_eax ?
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@50
PS4, Line 50: /* Migrate GDT to this text segment */
Keep empty line above.
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@118
PS4, Line 118: pop %ebx /* Number to clear */
It's fine like this.
We could easily reduce the remaining #ifdef here though, if we used %bh/%bl for these loop counts (MTRR counts are < 255). But that's just my opinion of what makes asm less readable.
https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@165
PS4, Line 165: /* Align stack to 16 bytes at call instruction. */
Keep empty line?
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Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31468 )
Change subject: rmodule: Add support for R_X86_64_PLT32
......................................................................
rmodule: Add support for R_X86_64_PLT32
The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).
Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.
Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/cbfstool/rmodule.c
1 file changed, 8 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Aaron Durbin: Looks good to me, approved
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 817bc60..80e8911 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -50,12 +50,18 @@
type = ELF64_R_TYPE(rel->r_info);
- /* Only these 5 relocations are expected to be found. */
+ /* Only these 6 relocations are expected to be found. */
return (type == R_AMD64_64 ||
type == R_AMD64_PC64 ||
type == R_AMD64_32S ||
type == R_AMD64_32 ||
- type == R_AMD64_PC32);
+ type == R_AMD64_PC32 ||
+ /*
+ * binutils 2.31 introduced R_AMD64_PLT32 for non local
+ * functions. As we don't care about procedure linkage
+ * table entries handle it as R_X86_64_PC32.
+ */
+ type == R_AMD64_PLT32);
}
static int should_emit_amd64(Elf64_Rela *rel)
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31769 )
Change subject: arch/x86: Prepare GDT for x86_64
......................................................................
Patch Set 1: Code-Review+2
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