coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Patrick Georgi (Code Review) 06 Mar '19

06 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31767 ) Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/31767/1/src/soc/qualcomm/qcs405/Kconfig File src/soc/qualcomm/qcs405/Kconfig: https://review.coreboot.org/#/c/31767/1/src/soc/qualcomm/qcs405/Kconfig@19 PS1, Line 19: VBOOT_OPROM_MATTERS That is normally used for devices with an "option rom" for graphics initialization. qcs405 sounds very much not like such a device. What is this for here? -- To view, visit https://review.coreboot.org/c/coreboot/+/31767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1078b23921f02e505b374ad515ab92260a6dda Gerrit-Change-Number: 31767 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Wed, 06 Mar 2019 11:07:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Michał Żygowski (Code Review) 06 Mar '19

06 Mar '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 6: (1 comment) > Patch Set 6: > > (1 comment) https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster… PS6, Line 621: > > Matt, can you test if serirq is enabled by the Google blob? […] Checking the bits on addresses (ilb_base + ILB_OIC) and (ilb_base + SCNT)? If Chromebooks have any hardware component utilizing SERIRQ, there should be interrupts reported in /proc/interrupts for that device. Example, SuperIO serial port: - with disabled SERIRQ no interrupts reported from serial port - SERIRQ in continuous mode, interrupts from serial appear on all cores through IOAPIC irq4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 06 Mar 2019 10:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init
by Michał Żygowski (Code Review) 06 Mar '19

06 Mar '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 2: Code-Review+2 > Patch Set 2: Code-Review-1 > > Hi Frans, > This patch doesn't appear to do anything to the UART. Perhaps you forgot to add a file when you committed the patch? > > Also, since this seems specific to the board you're working on (since you're using an external UART) can you enable/disable the internal UART in mainboard-specific code? I'm thinking mainboard_romstage_entry() or similar function. That will avoid the need to add the weak symbol to the generic codepath that will be taken on other boards. Yes, it is mainboard specific, thus the weak hook function. Braswell processors have internal legacy UART which uses IO base 0x3f8 and IRQ4 and this is the UART which is enabled by FSP memory init phase. In case the mainbaord has a SuperIO with UART for example, the serial port LDN on SuperIO must be reinitialized and internal UART disabled. Otherwise no serial output on headless systems. The hook will provide such possibility on mainboard level, while empty weak implementation won't impact any other mainboards. On the other hand, leaving the internal serial port enabled, while the port is not used, may have serious boot time impact on higher debug levels. Another issue here is that Your offer to disable the port in mainboard_romstage_entry or any other function executed later will lead to a loss of very important debug messages, when debugging with serial port. I mean we will loose the returned status code of memory init, which is very important. Thus the weak function has to be executed right after memory init. In all aspects the change will bring only benefits. -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Mar 2019 10:03:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Configure IO APIC
by Frans Hendriks (Code Review) 06 Mar '19

06 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29423 ) Change subject: soc/intel/braswell: Configure IO APIC ...................................................................... Patch Set 8: > Patch Set 7: > > Are we sure FSP doesn't do this already? It seems unlikely > that all the in tree Braswell devices don't use the APIC. > Maybe we only have to reserve the resources? I noticed that FSP is configuring some registers also. Will perform some tests, to reduce tasks of coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Mar 2019 08:53:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel: Use simple PCI config access
by Werner Zeh (Code Review) 06 Mar '19

06 Mar '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31749 ) Change subject: soc/intel: Use simple PCI config access ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c6712d836924b01c33a8435292be1ac2e530472 Gerrit-Change-Number: 31749 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Mar 2019 05:24:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Kyösti Mälkki (Code Review) 06 Mar '19

06 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/#/c/30500/4/src/arch/x86/exit_car.S@62 PS4, Line 62: mov %eax, %cr0 IA manual also says MOV r64, CR0-CR7 here. This %eax fails with GAS 2.32 (yesterdays toolchain). -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Mar 2019 05:11:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Mistral: QCS405: Added RPM support
by Sricharan Ramabadhran (Code Review) 06 Mar '19

06 Mar '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 ) Change subject: Mistral: QCS405: Added RPM support ...................................................................... Patch Set 14: Will fix the Jenkins issue here -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Mar 2019 02:37:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_
by Julius Werner (Code Review) 06 Mar '19

06 Mar '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31746 Change subject: lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_ ...................................................................... lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_ This is a great check, but unfortunately it's currently not effective because most uses of IS_ENABLED() do not have whitespace in front of them (they're mostly used as part of an if (IS_ENABLED(...)) condition). This patch makes the linter a little more generous in what it considers in scope to avoid these false negatives in the future. Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M util/lint/kconfig_lint 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31746/1 diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index eddd8de..e2d462f6 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -236,11 +236,11 @@ my @collected_is_enabled; if ($dont_use_git_grep) { @collected_is_enabled = - `grep -Irn -- "[[:space:]]IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; + `grep -Irn -- "IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; } else { @collected_is_enabled = - `git grep -In -- "[[:space:]]IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; + `git grep -In -- "IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; } while ( my $line = shift @collected_is_enabled ) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9 Gerrit-Change-Number: 31746 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/apollolake: Fix incorrect config usage
by Julius Werner (Code Review) 06 Mar '19

06 Mar '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31745 Change subject: intel/apollolake: Fix incorrect config usage ...................................................................... intel/apollolake: Fix incorrect config usage This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX). This patch can fix that. However, I don't have (and don't plan to acquire) an affected system to test, so approve at your own risk (or let me know if I should just remove that check instead). Change-Id: I79a0fca65853798ee45c3779b437864ba3cf2b1e Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/intel/apollolake/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31745/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index d1c5f6f..a08f1f0 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -73,7 +73,7 @@ /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (IS_ENABLED(SOC_INTEL_COMMON_BLOCK_SGX) || + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) mca_configure(NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/31745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a0fca65853798ee45c3779b437864ba3cf2b1e Gerrit-Change-Number: 31745 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/car: Fix incorrect config usage
by Julius Werner (Code Review) 06 Mar '19

06 Mar '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31744 Change subject: x86/car: Fix incorrect config usage ...................................................................... x86/car: Fix incorrect config usage This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX). This patch can fix that. However, I don't have (and don't plan to acquire) an affected system to test, so approve at your own risk (or let me know if I should just remove that check instead). Change-Id: I74e0ed4d04471ee521ff5c69a74a6f4c949e5847 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/cpu/x86/car.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31744/1 diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 1b02f8b..1a99c36 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -142,7 +142,7 @@ static void car_migrate_variables(int is_recovery) { - if (!IS_ENABLED(PLATFORM_USES_FSP1_0)) + if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)) do_car_migrate_variables(); } ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) -- To view, visit https://review.coreboot.org/c/coreboot/+/31744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74e0ed4d04471ee521ff5c69a74a6f4c949e5847 Gerrit-Change-Number: 31744 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019