coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: HACK trogdor: prevent system from building bl31 HACK
by mturney mturney (Code Review) 07 Aug '23

07 Aug '23

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35507 ) Change subject: HACK trogdor: prevent system from building bl31 HACK ...................................................................... HACK trogdor: prevent system from building bl31 HACK Change-Id: I04cbc09ebef3c2e58b6f7c6aa98d65ce5b83b003 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/arch/arm64/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35507/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 1aee6b8..1c2e72e 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -152,6 +152,7 @@ # Build ARM Trusted Firmware (BL31) ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_SC7180),y) ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") @@ -231,6 +232,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif #CONFIG_SOC_QUALCOMM_SC7180 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 -- To view, visit https://review.coreboot.org/c/coreboot/+/35507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04cbc09ebef3c2e58b6f7c6aa98d65ce5b83b003 Gerrit-Change-Number: 35507 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [TESTME]nb/intel/pineview: Use regular udelay over hpet_udelay
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35759 ) Change subject: [TESTME]nb/intel/pineview: Use regular udelay over hpet_udelay ...................................................................... [TESTME]nb/intel/pineview: Use regular udelay over hpet_udelay There is no need for high precision udelays here. Change-Id: I619e2f215f94858e53ac1369b2f6d995303aa3cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 7 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35759/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..db13b2a 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -547,20 +547,6 @@ } } -#define HPET_BASE 0xfed00000 -#define HPET32(x) *((volatile u32 *)(HPET_BASE + x)) -static void enable_hpet(void) -{ - u32 reg32; - reg32 = RCBA32(HPTC); - reg32 &= ~0x3; - reg32 |= (1 << 7); - RCBA32(HPTC) = reg32; - /* On NM10 this only works if read back */ - RCBA32(HPTC); - HPET32(0x10) = HPET32(0x10) | 1; -} - static void sdram_clk_crossing(struct sysinfo *s) { u8 clk_idx, fsb_idx; @@ -1525,29 +1511,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegmb[s->dimm_config[0]]); } -#if 1 -static void hpet_udelay(u32 del) -{ - u32 start, finish, now; - - del *= 15; /* now in usec */ - - start = HPET32(0xf0); - finish = start + del; - while (1) { - now = HPET32(0xf0); - if (finish > start) { - if (now >= finish) - break; - } else { - if ((now < start) && (now >= finish)) { - break; - } - } - } -} -#endif - static u8 sdram_checkrcompoverride(void) { u32 xcomp; @@ -1588,7 +1551,7 @@ MCHBAR8(0x130) = MCHBAR8(0x130) & ~(1 << 7); for (i = 0; i < 3; i++) { MCHBAR8(0x130) = MCHBAR8(0x130) | 1; - hpet_udelay(1000); + udelay(1000); while ((MCHBAR8(0x130) & 0x1) != 0); ok |= sdram_checkrcompoverride(); } @@ -1600,7 +1563,7 @@ MCHBAR32(0x140) = reg32a; } MCHBAR8(0x130) = MCHBAR8(0x130) | 1; - hpet_udelay(1000); + udelay(1000); while ((MCHBAR8(0x130) & 0x1) != 0); } @@ -1614,7 +1577,7 @@ MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | jmode; read32((void *)reg32); barrier(); - hpet_udelay(1); // 1us + udelay(1); // 1us } static void sdram_zqcl(struct sysinfo *s) @@ -1660,7 +1623,7 @@ rttnom |= (1 << 6); } - hpet_udelay(200); // 200us + udelay(200); // 200us reg16 = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (i = 0; i < 12; i++) { @@ -1815,13 +1778,13 @@ u8 dqsmatches = 1; while (count--) { MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; - hpet_udelay(1); + udelay(1); MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; - hpet_udelay(1); + udelay(1); barrier(); read32((void *)strobeaddr); barrier(); - hpet_udelay(1); + udelay(1); if (((MCHBAR8(dqshighaddr) & 0x40) >> 6) != highlow) { dqsmatches = 0; @@ -2515,9 +2478,6 @@ /* Determine smallest common tRAS, tRP, tRCD, etc */ sdram_detect_smallest_params(&si); - /* Enable HPET */ - enable_hpet(); - MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); sdram_clk_crossing(&si); -- To view, visit https://review.coreboot.org/c/coreboot/+/35759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I619e2f215f94858e53ac1369b2f6d995303aa3cf Gerrit-Change-Number: 35759 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] Documentation/basics: Add Super I/O section
by Christoph Pomaska (Code Review) 07 Aug '23

07 Aug '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35912 ) Change subject: [WIP] Documentation/basics: Add Super I/O section ...................................................................... [WIP] Documentation/basics: Add Super I/O section This file contains and is supposed to contain basic information about what a Super I/O is and what it does. Change-Id: If288dcd79c4622a712868229b18f8b38e71d4af9 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A Documentation/basics/superio.md 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35912/1 diff --git a/Documentation/basics/superio.md b/Documentation/basics/superio.md new file mode 100644 index 0000000..5f17a4c --- /dev/null +++ b/Documentation/basics/superio.md @@ -0,0 +1,29 @@ +# What is super I/O? + +Super I/O chips are a component that exist in PCs since the 1980s +and are usually connected via ISA/LPC. They are specific to x86 based platforms. + +Super I/O components have a wide range of tasks, from which the most widely known are: +- serial (e.g. RS232) +- PS/2 +- parallel (IEEE 1284) +- floppy-disk-controller +- PECI (Platform Enviroment Controller Interface) + +They can also act as an EC (Embedded Controller) managing things like: +- fancontrol +- battery charge controlling (on laptops) +- LED control + +BMC (Board Management Controller) and manage IPMI (Intelligent Platform Management Interface). +Very most x86 mainboards have at least one Super I/O chip. + +In case of the Supermicro [X10SLM+-F](https://www.supermicro.com/en/products/motherboard/x10slm+-f) there is a Nuvoton NCT6776 and an Aspeed AST2400 used. +The Nuvoton chip manages serial, PS/2 and hardware monitoring while the Aspeed chip manages the BMC functionality. +As another example does the Supermicro X11SSH-TF board solely use the same Aspeed chip as BMC, but also for serial. + + +## Super I/O and coreboot +The registers that need to be configured to make a Super I/O work are mostly vendor-specific, but sometimes also chip-specific. +coreboot ships a tool called [superiotool](../util.md) that reads out the most commonly used registers to determine which chip could be used on the board. +Conveniently it also prints out the registers and their contents in case a superio is detected. -- To view, visit https://review.coreboot.org/c/coreboot/+/35912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If288dcd79c4622a712868229b18f8b38e71d4af9 Gerrit-Change-Number: 35912 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/baytrail: Use common sb code for SPI lockdown configuration
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36009 ) Change subject: soc/intel/baytrail: Use common sb code for SPI lockdown configuration ...................................................................... soc/intel/baytrail: Use common sb code for SPI lockdown configuration This removes the weakly linked function to configure the SPI lockdown. Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/w25q64.c M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/southcluster.c 3 files changed, 16 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36009/1 diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c index a9ed8ac..114c8c7 100644 --- a/src/mainboard/google/rambi/w25q64.c +++ b/src/mainboard/google/rambi/w25q64.c @@ -17,52 +17,16 @@ #include <soc/spi.h> /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 063dd7f..61e430b 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -54,17 +54,14 @@ # define BCR_WPD (0x1 << 0) /* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; + struct vscc_config { + uint32_t lvscc; + uint32_t uvscc; + }; /* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg); #endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 139d2be..f5bbda6 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -42,6 +42,7 @@ #include <soc/spi.h> #include "chip.h" #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h> static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, @@ -540,11 +541,6 @@ .device = LPC_DEVID, }; -int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - return -1; -} - static void finalize_chipset(void *unused) { u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); @@ -552,7 +548,7 @@ u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); u8 *spi = (u8 *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg; /* Set the lock enable on the BIOS control register. */ write32(bcr, read32(bcr) | BCR_LE); @@ -566,14 +562,12 @@ /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK); - if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10c00f6c8a0928210faa7c91a32a745d282088e9 Gerrit-Change-Number: 36009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: add Gigabyte P34G v2
by Daniel Maslowski (Code Review) 07 Aug '23

07 Aug '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36010 ) Change subject: Documentation: add Gigabyte P34G v2 ...................................................................... Documentation: add Gigabyte P34G v2 Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- A Documentation/mainboard/gigabyte/p34g-v2.md A Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg M Documentation/mainboard/index.md 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36010/1 diff --git a/Documentation/mainboard/gigabyte/p34g-v2.md b/Documentation/mainboard/gigabyte/p34g-v2.md new file mode 100644 index 0000000..4dfcf79 --- /dev/null +++ b/Documentation/mainboard/gigabyte/p34g-v2.md @@ -0,0 +1,88 @@ +# Gigabyte P34G v2 + +This page describes how to run coreboot on the [Gigabyte P34G v2 gaming +laptop](https://www.gigabyte.com/Laptop/P34G-v2). + +Original board name: GA-R3456R + +Rebrands: +- Schenker XMG C404 + +## Technology + +```eval_rst ++------------------+----------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/haswell/index` | ++------------------+----------------------------------------------+ +| Southbridge | Lynx Point | ++------------------+----------------------------------------------+ +| CPU | i7-4710HQ | ++------------------+----------------------------------------------+ +| EC / SuperIO | ITE IT8587E | ++------------------+----------------------------------------------+ +| Coprocessor | Intel ME, `me_cleaner` untested | ++------------------+----------------------------------------------+ +| TPM | None, but socket exists (see photo below) | ++------------------+----------------------------------------------+ +``` + +## Required proprietary blobs + +```eval_rst +Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. +``` + +## Flash chip + +![SPI chip and TPM location](p34g-v2_tpm_socket_spi_chip.jpg) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | No | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| In circuit flashing | Yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Internal flashing | Untested | ++---------------------+------------+ +``` + +## Flash layout + +```txt +00000000:00000fff fd +00400000:007fffff bios +00001000:003fffff me +``` + +## EC firmware + +There is an additional 128KiB EC firmware blob within the BIOS region at +`0x700000`. The EC has its own internal EPROM though, for which Gigabyte offers +updates in a bundle with the UEFI firmware updates based on AMI Aptio. The EC +firmware can be updated via AFU. An unmodified EC firmware version F005 seems +to work fine with coreboot even without the extra 128KiB part. It could be +extracted from a firmware update through `dd` etc and reinserted though. Other +version have not been tested. + +## Known issues + +- EC / ACPI + * no suspend on LID close + * eject, sleep, backlight up/down, external screen buttons do not work + * Bluetooth LED shows inverted state, does not turn on on first press + * battery state can not be queried +- CPU overheats on high load leading to force poweroff + +```eval_rst +Please also see :doc:`../../northbridge/intel/haswell/known-issues`. +``` diff --git a/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg new file mode 100644 index 0000000..9835a8a --- /dev/null +++ b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 83189757..f0f8f8e 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -40,6 +40,7 @@ ## Gigabyte - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) +- [P34G v2](gigabyte/p34g-v2.md) ## Google -- To view, visit https://review.coreboot.org/c/coreboot/+/36010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb Gerrit-Change-Number: 36010 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: inteltool: gemini lake gpio support + UHD 605 graphics detection
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

coreboot(a)s.paape.io has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36033 ) Change subject: inteltool: gemini lake gpio support + UHD 605 graphics detection ...................................................................... inteltool: gemini lake gpio support + UHD 605 graphics detection Signed-off-by: lead4good <coreboot(a)s.paape.io> Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 5 files changed, 317 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36033/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..da4eadd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1035,6 +1035,7 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_GLK: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..cc1d99e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -45,6 +45,310 @@ * (if it's the first column, GPIO is the default, no matter the name) */ +static const char *const glk_group_northwest_names[] = { + "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a", + "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a", + "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a", + "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a", + "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a", + "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a", + "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a", + "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a", + "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a", + "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a", + "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a", + "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a", + "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a", + "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a", + "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a", + "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a", + "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a", + "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a", + "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a", + "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a", + "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a", + "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a", + "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a", + "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a", + "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a", + "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK", + "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI", + "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a", + "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a", + "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a", + "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a", + "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a", + "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a", + "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a", + "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a", + "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a", + "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a", + "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a", + "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a", + "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a", + "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "------- GPIO Group NorthWest -------", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_northwest_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "----- GPIO Community NorthWest -----", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const char *const glk_group_north_names[] = { + "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a", + "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a", + "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a", + "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a", + "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a", + "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a", + "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a", + "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a", + "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a", + "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a", + "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a", + "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a", + "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a", + "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a", + "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a", + "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a", + "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a", + "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a", + "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a", + "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a", + "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a", + "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a", + "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a", + "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a", + "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a", + "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a", + "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a", + "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0", + "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1", + "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN", + "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a", + "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a", + "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a", + "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a", + "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a", + "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a", + "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a", + "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a", + "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a", + "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a", + "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a", + "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_north = { + .display = "----- GPIO Group North -----", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "--- GPIO Community North ---", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const char *const glk_group_audio_names[] = { + "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a", + "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a", + "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a", + "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a", + "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a", + "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a", + "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK", + "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC", + "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI", + "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO", + "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a", + "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a", + "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a", + "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a", + "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a", + "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a", + "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a", + "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a", + "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a", + "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_audio = { + .display = "----- GPIO Group Audio -----", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "--- GPIO Community Audio ---", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const char *const glk_group_scc_names[] = { + "GPIO_176", "SMB_ALERT_N", "n/a", "n/a", + "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a", + "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a", + "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a", + "GPIO_179", "SDCARD_CLK", "n/a", "n/a", + "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a", + "GPIO_181", "SDCARD_D0", "n/a", "n/a", + "GPIO_182", "SDCARD_D1", "n/a", "n/a", + "GPIO_183", "SDCARD_D2", "n/a", "n/a", + "GPIO_184", "SDCARD_D3", "n/a", "n/a", + "GPIO_185", "SDCARD_CMD", "n/a", "n/a", + "GPIO_186", "SDCARD_CD_N", "n/a", "n/a", + "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a", + "GPIO_210", "n/a", "n/a", "n/a", + "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a", + "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a", + "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N", + "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD", + "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD", + "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N", + "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC", + "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO", + "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a", + "GPIO_198", "EMMC_CLK", "n/a", "n/a", + "GPIO_199", "EMMC_D0", "n/a", "n/a", + "GPIO_200", "EMMC_D1", "n/a", "n/a", + "GPIO_201", "EMMC_D2", "n/a", "n/a", + "GPIO_202", "EMMC_D3", "n/a", "n/a", + "GPIO_203", "EMMC_D4", "n/a", "n/a", + "GPIO_204", "EMMC_D5", "n/a", "n/a", + "GPIO_205", "EMMC_D6", "n/a", "n/a", + "GPIO_206", "EMMC_D7", "n/a", "n/a", + "GPIO_207", "EMMC_CMD", "n/a", "n/a", + "GPIO_208", "EMMC_RCLK", "n/a", "n/a", + "GPIO_209", "EMMC_RST_N", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_scc = { + .display = "----- GPIO Group SCC -----", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "--- GPIO Community SCC ---", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const glk_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + static const char *const apl_group_north_names[] = { "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -2284,6 +2588,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_GLK: + community_count = ARRAY_SIZE(glk_communities); + communities = glk_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..5aa4592 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -300,6 +300,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ @@ -395,6 +396,8 @@ "Intel(R) HD Graphics 530" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2, "Intel(R) HD Graphics 530" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605, + "Intel(R) UHD Graphics 605" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1, "Intel(R) UHD Graphics 615" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..9ad1a5f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -264,6 +264,7 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc @@ -340,6 +341,7 @@ #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 +#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..fec7457 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -120,6 +120,7 @@ p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: + case PCI_DEVICE_ID_INTEL_GLK: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; case PCI_DEVICE_ID_INTEL_H310: -- To view, visit https://review.coreboot.org/c/coreboot/+/36033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401 Gerrit-Change-Number: 36033 Gerrit-PatchSet: 1 Gerrit-Owner: coreboot(a)s.paape.io Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: superio: IT8587E (WIP)
by Daniel Maslowski (Code Review) 07 Aug '23

07 Aug '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36071 ) Change subject: superio: IT8587E (WIP) ...................................................................... superio: IT8587E (WIP) Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- A src/superio/ite/it8587e/Kconfig A src/superio/ite/it8587e/Makefile.inc A src/superio/ite/it8587e/it8587e.h A src/superio/ite/it8587e/superio.c 4 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36071/1 diff --git a/src/superio/ite/it8587e/Kconfig b/src/superio/ite/it8587e/Kconfig new file mode 100644 index 0000000..438bd3e --- /dev/null +++ b/src/superio/ite/it8587e/Kconfig @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8587E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8587e/Makefile.inc b/src/superio/ite/it8587e/Makefile.inc new file mode 100644 index 0000000..dbde0b7 --- /dev/null +++ b/src/superio/ite/it8587e/Makefile.inc @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8587E) += superio.c diff --git a/src/superio/ite/it8587e/it8587e.h b/src/superio/ite/it8587e/it8587e.h new file mode 100644 index 0000000..eab3527 --- /dev/null +++ b/src/superio/ite/it8587e/it8587e.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8587E_H +#define SUPERIO_ITE_IT8587E_H + +#define IT8528E_SP1 0x01 /* Com1 */ +#define IT8528E_SP2 0x02 /* Com2 */ +#define IT8587E_SWUC 0x04 /* System Wake-Up */ +#define IT8587E_KBCM 0x05 /* PS/2 mouse */ +#define IT8587E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8587E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8587E_RTCT 0x10 /* RTC-like Timer */ +#define IT8587E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8587E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8587E_SSPI 0x13 /* Serial Periphial Interface */ +#define IT8587E_PECI 0x14 /* Platform EC Interface */ +#define IT8587E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8587E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8587E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8587E_H */ diff --git a/src/superio/ite/it8587e/superio.c b/src/superio/ite/it8587e/superio.c new file mode 100644 index 0000000..cdb97e6 --- /dev/null +++ b/src/superio/ite/it8587e/superio.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * Copyright (C) 2019 9Elements GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "it8587e.h" + +static void it8587e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8587e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8587E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8587E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8587E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Unused */ + { NULL, IT8587E_KBCM, PNP_IRQ0, }, + /* Documentation: Program io0 = 0x60 and io1 = 0x64 */ + { NULL, IT8587E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8587E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Program io0 = 0x70-0x73 */ + { NULL, IT8587E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + /* Documentation: Program io0 = 0x62 and io1 = 0x66 */ + { NULL, IT8587E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + /* Documentation: Program io0 = 0x68 and io1 = 0x6c */ + { NULL, IT8587E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07fc, 0x07fc }, + /* Documentation: Program io0 = 0x6a and io1 = 0x6e */ + { NULL, IT8587E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8587E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8528E_PECI, PNP_IO0, 0xfff8 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8587e_ops = { + CHIP_NAME("ITE IT8587E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5 Gerrit-Change-Number: 36071 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2
by Philipp Hug (Code Review) 07 Aug '23

07 Aug '23

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36487 ) Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 Instead of loading coreboot in the RAM, newer Qemu version support providing it as flash using the -pflash option. Currently qemu limits the flash size to 2*16MiB. This will hopefully be changed to 2*32MiB before release of 4.2. Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c 5 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36487/1 diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index 3aad816..faae1e5 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -2,7 +2,11 @@ ## Building coreboot and running it in Qemu +### Qemu >= 4.2 - Configure coreboot and run `make` as usual +- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -pflash build/coreboot.rom` + +### Qemu < 4.2 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to convert coreboot to an ELF that Qemu can load - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..7d6fe48 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -12,11 +12,6 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -# To execute, do: -# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf -# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf - - if BOARD_EMULATION_QEMU_RISCV_RV64 config BOARD_EMULATION_QEMU_RISCV @@ -65,19 +60,6 @@ # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80000000 endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index fd8c136..4bb5e98 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -17,4 +17,5 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14..46f360f 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -17,26 +17,24 @@ #include <arch/header.ld> #include <mainboard/addressmap.h> -// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) +#define FLASH_START(addr) SYMBOL(flash, addr) +#define FLASH_END(addr) SYMBOL(eflash, addr) SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + FLASH_START(QEMU_VIRT_FLASH) + BOOTBLOCK(QEMU_VIRT_FLASH, 64K) + FLASH_END(QEMU_VIRT_FLASH + 64K) -#if ENV_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif + DRAM_START(QEMU_VIRT_DRAM) #if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) + REGION(opensbi, QEMU_VIRT_DRAM, 128K, 4K) #endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) +#if ENV_ROMSTAGE + ROMSTAGE(QEMU_VIRT_DRAM + 128K, 128K) +#endif + // TODO, drop the 15M hack + RAMSTAGE(QEMU_VIRT_DRAM + 256K, 15M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 256K + 15M, 8K) + STACK(QEMU_VIRT_DRAM + 256K + 15M + 8K, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 79e5ca8..7349ecb 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -15,11 +15,10 @@ */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h> -/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019