Change in coreboot[master]: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34994 ) Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API ...................................................................... arch/x86: Add postcar_frame_setup_top_of_dram_usage() API This patch adds new API for intermediate caching top_of_ram and setting up required MTRR for next stage. Change-Id: I28d0507083d84e10eef6e1e5482a805067e23847 Signed-off-by: Subrata Banik <subrata.banik@intel.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/34994/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 42c8a97..efee12d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -332,6 +332,15 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf); /* + * This API performs below operations: + * 1. Add variable MTRR covering the Top of DRAM with given MTRR type + * 2. Enable intermediate caching of Top of DRAM with given size to speed up + * next stage loading and decompression. + */ +void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* * Push used MTRR and Max MTRRs on to the stack * and return pointer to stack top. */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 94fde20..f308298 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> @@ -138,6 +139,36 @@ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } +/* + * Make sure we are enabling intermediate caching to speed up next stage + * (postcar/romstage) loading and decompression as we are still in romstage + * and CAR tear down will be handled by next stage at its entry. + */ +static void enable_top_of_dram_cache(uintptr_t base, size_t size, int type) +{ + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + /* FIXME: setting up type = WB causing hang while loading next stage */ + set_var_mtrr(mtrr, base, size, type); +} + +void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type) +{ + /* + * Enable intermediate caching for Top of DRAM to speed up + * next stage loading. No need to enable intermediate caching in S3 + * resume path as next stage will be fetched from stage cache + * without any additional locate/decompression logic as normal boot. + */ + if (!acpi_is_wakeup_s3()) + enable_top_of_dram_cache(addr, size, type); + postcar_frame_add_mtrr(pcf, addr, size, type); +} + void *postcar_commit_mtrrs(struct postcar_frame *pcf) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/34994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d0507083d84e10eef6e1e5482a805067e23847 Gerrit-Change-Number: 34994 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> Gerrit-MessageType: newchange
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34994 ) Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/34994/2/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c: https://review.coreboot.org/c/coreboot/+/34994/2/src/arch/x86/postcar_loader... PS2, Line 155: set_var_mtrr(mtrr, base, size, type); base is not checked if it's aligned to size. https://review.coreboot.org/c/coreboot/+/34994/2/src/arch/x86/postcar_loader... PS2, Line 163: No need to enable intermediate caching in S3 That's not true for multiple reasons: - It depends on CONFIG_NO_STAGE_CACHE - even if the stage is cached it still needs to be copied where it will be executed. -- To view, visit https://review.coreboot.org/c/coreboot/+/34994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d0507083d84e10eef6e1e5482a805067e23847 Gerrit-Change-Number: 34994 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Arthur Heymans <arthur@aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Fri, 22 Nov 2019 13:31:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34994?usp=email ) Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API ...................................................................... Abandoned This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/34994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d0507083d84e10eef6e1e5482a805067e23847 Gerrit-Change-Number: 34994 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Arthur Heymans <arthur@aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-MessageType: abandon
participants (3)
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Arthur Heymans (Code Review) -
Martin L Roth (Code Review)
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Subrata Banik (Code Review)