coreboot-gerrit October 2019

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Change in coreboot[master]: mb/facebook/fbg1701: Add logo to the menu
by Wim Vervoorn (Code Review) 04 Nov '19

04 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36506 ) Change subject: mb/facebook/fbg1701: Add logo to the menu ...................................................................... mb/facebook/fbg1701: Add logo to the menu Allow the user to enable and disable the logo from make menuconfig. The file can ve selected as well. BUG=N/A TEST=build Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36506/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index a6c2846..3ade727 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -69,9 +69,14 @@ default 0xfff9c000 config FSP1_1_DISPLAY_LOGO - bool + bool "Enable logo" default n +config FSP1_1_LOGO_FILE_NAME + string "Logo file" + depends on FSP1_1_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + config VENDORCODE_ELTAN_OEM_MANIFEST_LOC hex default 0xFFFE9000 -- To view, visit https://review.coreboot.org/c/coreboot/+/36506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c Gerrit-Change-Number: 36506 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: vendorcode/eltan: cleanup of Kconfig files
by Wim Vervoorn (Code Review) 04 Nov '19

04 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36479 ) Change subject: vendorcode/eltan: cleanup of Kconfig files ...................................................................... vendorcode/eltan: cleanup of Kconfig files The vendorcode/eltan and vendorcode/eltan/security directories were both adding the mboot and verified_boot Kconfigs. BUG=N/A TEST=build Change-Id: I6b5f19b4660d60345391b7320ce42466fd2cc769 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/vendorcode/eltan/Kconfig M src/vendorcode/eltan/security/Kconfig 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36479/1 diff --git a/src/vendorcode/eltan/Kconfig b/src/vendorcode/eltan/Kconfig index dc756ab..319e90a 100644 --- a/src/vendorcode/eltan/Kconfig +++ b/src/vendorcode/eltan/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014-2018 Eltan B.V. +## Copyright (C) 2014-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,6 +17,5 @@ bool if USE_VENDORCODE_ELTAN -source src/vendorcode/eltan/security/mboot/Kconfig -source src/vendorcode/eltan/security/verified_boot/Kconfig +source src/vendorcode/eltan/security/Kconfig endif diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 2af5808..6b93d2a 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -1,6 +1,6 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Eltan B.V. +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -12,5 +12,7 @@ ## GNU General Public License for more details. ## +menu "Eltan Security Settings" source src/vendorcode/eltan/security/mboot/Kconfig source src/vendorcode/eltan/security/verified_boot/Kconfig +endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/36479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b5f19b4660d60345391b7320ce42466fd2cc769 Gerrit-Change-Number: 36479 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: [RFC,POC]arch/arm: Pass cbmem_top to ramstage via calling argument
by Arthur Heymans (Code Review) 03 Nov '19

03 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36145 ) Change subject: [RFC,POC]arch/arm: Pass cbmem_top to ramstage via calling argument ...................................................................... [RFC,POC]arch/arm: Pass cbmem_top to ramstage via calling argument This solution is very generic and can in principle be implemented on all arch/soc. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/include/arch/stages.h M src/arch/arm/stages.c M src/mainboard/emulation/qemu-armv7/Makefile.inc 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36145/1 diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 3841265..16cfbbc 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -16,6 +16,6 @@ #include <main_decl.h> -void stage_entry(void); +void stage_entry(void *stage_arg); #endif diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index c9f5744..50526c4 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -22,13 +22,28 @@ * .text.stage_entry section created by -ffunction-sections). */ +#include <cbmem.h> #include <arch/stages.h> #include <arch/cache.h> /** * generic stage entry point. override this if board specific code is needed. */ -__weak void stage_entry(void) +#if ENV_RAMSTAGE +static uintptr_t cbmem_top_ptr; +#endif + +__weak void stage_entry(void *stage_arg) { +#if ENV_RAMSTAGE + cbmem_top_ptr = (uintptr_t)stage_arg; +#endif main(); } + +#if ENV_RAMSTAGE +void *cbmem_top(void) +{ + return (void *)cbmem_top_ptr; +} +#endif diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d5742e1..c62915b 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -15,7 +15,6 @@ romstage-y += romstage.c romstage-y += cbmem.c -ramstage-y += cbmem.c bootblock-y += media.c romstage-y += media.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Gerrit-Change-Number: 36145 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 27

Change in coreboot[master]: [RFC,POF] pass cbmem_top via the stack to ramstage
by Arthur Heymans (Code Review) 03 Nov '19

03 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36144 ) Change subject: [RFC,POF] pass cbmem_top via the stack to ramstage ...................................................................... [RFC,POF] pass cbmem_top via the stack to ramstage Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and using the top of lower memory if often passed via lower memory or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. TODO this can be done on all arch TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/c_start.S M src/arch/x86/cbmem.c M src/lib/prog_loaders.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/northbridge/intel/i945/memmap.c 5 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36144/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 32b848d..6177773 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -18,6 +18,7 @@ .section .bss, "aw", @nobits .global _stack .global _estack +.global _cbmem_top_ptr /* Stack alignment is not enforced with rmodule loader, reserve one * extra CPU such that alignment can be enforced on entry. */ @@ -30,6 +31,8 @@ thread_stacks: .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS #endif +_cbmem_top_ptr: + .long 0 .section ".text._start", "ax", @progbits #ifdef __x86_64__ @@ -59,6 +62,9 @@ cld + pop %eax + movl %eax, _cbmem_top_ptr + /** poison the stack. Code should not count on the * stack being full of zeros. This stack poisoning * recently uncovered a bug in the broadcast SIPI diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 16c35b5..6b1581c 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -13,6 +13,7 @@ #include <stdlib.h> #include <cbmem.h> +#include <console/console.h> #if CONFIG(CBMEM_TOP_BACKUP) @@ -34,3 +35,13 @@ } #endif /* CBMEM_TOP_BACKUP */ + +extern const uintptr_t _cbmem_top_ptr; + +#if ENV_RAMSTAGE +void *cbmem_top(void) +{ + printk(BIOS_DEBUG, "_cbmem_top_ptr: 0x%08x\n", (u32)_cbmem_top_ptr); + return (void *)_cbmem_top_ptr; +} +#endif diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 2ef6bdf..a806f41 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -142,6 +142,10 @@ timestamp_add_now(TS_END_COPYRAM); + ramstage.arg = cbmem_top(); + + printk(BIOS_DEBUG, "ramstage arg: 0x%08x\n", (u32)ramstage.arg); + prog_run(&ramstage); fail: diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 8209379..5ec6a9f 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -16,6 +16,7 @@ #include <cbmem.h> #include <arch/io.h> #include <arch/romstage.h> +#include <console/console.h> #include "memory.h" #include "fw_cfg.h" @@ -52,6 +53,7 @@ return tomk; } +#if !ENV_RAMSTAGE void *cbmem_top(void) { uintptr_t top = 0; @@ -60,8 +62,10 @@ if (!top) top = (uintptr_t)qemu_get_memory_size() * 1024; + printk(BIOS_DEBUG, "cbmem_top(): 0x%08x\n", (u32)top); return (void *)top; } +#endif /* Nothing to do, MTRRs are no-op on QEMU. */ void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 8207d06..c7e5d39 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -71,11 +71,14 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ + +#if !ENV_RAMSTAGE void *cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; } +#endif /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) -- To view, visit https://review.coreboot.org/c/coreboot/+/36144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Gerrit-Change-Number: 36144 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 19

Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP]sb/intel/common: Handle legacy save states properly
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35783 ) Change subject: [WIP]sb/intel/common: Handle legacy save states properly ...................................................................... [WIP]sb/intel/common: Handle legacy save states properly This moves southbridge_update_gnvs to a common place. Older 32bit only CPU's have a different SMM save state, requiring a different handling of those. Change-Id: I08391d4ee361ce75507c9de508cd75cc07249fd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/em64t101_save_state.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 9 files changed, 140 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35783/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 3eb869a..5350d1c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -168,6 +168,9 @@ if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); + /* This may not be be correct for older CPU's supported by this code, + but given that em64t101_smm_state_save_area_t is larger than the + save_state of these CPU's it works. */ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } @@ -191,6 +194,8 @@ { msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; + /* The em64t101 save state is sufficiently compatible with older + save states with regards of smbase, smm_revision. */ em64t101_smm_state_save_area_t *save_state; u32 smbase = staggered_smbase; u32 iedbase = relo_params->ied_base; @@ -208,7 +213,10 @@ save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); save_state->smbase = smbase; - save_state->iedbase = iedbase; + + printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision); + if (save_state->smm_revision == 0x00030101) + save_state->iedbase = iedbase; /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index b8bb2db..7493c85 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,6 +20,7 @@ /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: + * - Nehalem * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index ceac598..fe4f80e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -38,6 +37,11 @@ return gnvs; } +void smm_set_gnvs(uintptr_t gnvs_ptr) +{ + gnvs = (global_nvs_t *)gnvs_ptr; +} + int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -211,18 +215,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index cea5c82..b2f1dc4 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -18,7 +18,9 @@ #define INTEL_COMMON_PMUTIL_H #include <cpu/x86/smm.h> +#include <cpu/x86/legacy_save_state.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/em64t_save_state.h> #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -142,10 +144,11 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); +void smm_set_gnvs_ptr(uintptr_t gnvs); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); + +void *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index d61238c..731856a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -210,37 +210,77 @@ } } +enum save_state_type { + EM64T, + EM64T101, + LEGACY +}; + +static enum save_state_type get_save_state_type(void) +{ + /* Is geting this on node 0 fine??? */ + void *save_state = smm_get_save_state(0); + u32 smm_revision = ((em64t101_smm_state_save_area_t *)state)->smm_revision; + switch (smm_revision) { + case 0x00030002: + case 0x00030007: + return LEGACY; + case 0x00030100: + return EM64T; + default: + printk(BIOS_WARNING, "Unknown smm_revision...\n"); + /* Fallthrough */ + case 0x00030101: /* Nahalem, SandyBridge, IvyBridge, and Haswell */ + return EM64T101; + } +} + /* * Look for Synchronous IO SMI and use save state from that * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +void *smi_apmc_find_state_save(u8 cmd) { - em64t101_smm_state_save_area_t *state; int node; + enum save_state_type save_state_type = get_save_state_type(); - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); + if (save_state_type == EM64T || save_state_type == EM64T101) { + /* Check all nodes looking for the one that issued the IO. + TODO: Check against actual amount of CPUs!! */ + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + em64t101_smm_state_save_area_t *state = + (em64t101_smm_state_save_area_t *)smm_get_save_state(node); - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; - return state; + return state; + } + } + + if (save_state_type == LEGACY) { + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + legacy_smm_state_save_area_t *state = + (legacy_smm_state_save_area_t *)smm_get_save_state(node); + + /* Check AX against the requested command */ + if ((state->eax & 0xff) == cmd) + return state; + } } return NULL; @@ -272,23 +312,62 @@ static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); + void *state = smi_apmc_find_state_save(APM_CNT_SMMSTORE); uint32_t reg_ebx; - if (!io_smi) + if (!state) return; /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + switch (get_save_state_type()) { + case EM64T: + case EM64T101: + sub_command = ((u32)((em64t101_smm_state_save_area_t *)state)->rax >> 8) & 0xff; - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + reg_ebx = (u32)((em64t101_smm_state_save_area_t *)state)->rbx; + break; + case LEGACY: + sub_command = (((legacy_smm_state_save_area_t *)state)->eax >> 8) & 0xff; + reg_ebx = ((legacy_smm_state_save_area_t *)state)->ebx; + break; + } - /* drivers/smmstore/smi.c */ + /* drivers/smmstore/smi.c, parameter buffer in EBX */ ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); - io_smi->rax = ret; + + switch (get_save_state_type()) { + case EM64T: + case EM64T101: + ((em64t101_smm_state_save_area_t *)state)->rax = ret; + break; + case LEGACY: + ((legacy_smm_state_save_area_t *)state)->eax = ret; + break; + } } +static void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +{ + uintptr_t gnvs = 0; + void *state = smi_apmc_find_state_save(apm_cnt); + if (state) { + switch (get_save_state_type()) { + case EM64T: + case EM64T101: + /* EBX in the state save contains the GNVS pointer */ + gnvs = (u32)((em64t101_smm_state_save_area_t *)state)->rbx; + break; + case LEGACY: + gnvs = ((legacy_smm_state_save_area_t *)state)->ebx; + break; + } + *smm_done = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } + if (gnvs) + smm_set_gnvs_ptr(gnvs); +} + + static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13..fccc67d 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -41,12 +41,11 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void smm_set_gnvs_ptr(uintptr_t gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - *smm_done = 1; + gnvs = (global_nvs_t *)gnvs; } int southbridge_io_trap_handler(int smif) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8090a09..7135425 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -28,9 +28,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; int southbridge_io_trap_handler(int smif) { @@ -49,12 +47,9 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void smm_set_gnvs_ptr(uintptr_t gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; + gnvs = (global_nvs_t *)gnvs; } void southbridge_smi_monitor(void) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a853..d9e944d 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -35,9 +35,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; int southbridge_io_trap_handler(int smif) { @@ -56,12 +54,9 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void smm_set_gnvs_ptr(uintptr_t gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; + gnvs = (global_nvs_t *)gnvs; } void southbridge_smi_monitor(void) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..cc32127 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> @@ -44,11 +43,17 @@ * by coreboot. */ static global_nvs_t *gnvs; + global_nvs_t *smm_get_gnvs(void) { return gnvs; } +void smm_set_gnvs_ptr(uintptr_t gnvs_ptr) +{ + gnvs = (global_nvs_t *)gnvs; +} + int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -171,18 +176,6 @@ #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); -- To view, visit https://review.coreboot.org/c/coreboot/+/35783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08391d4ee361ce75507c9de508cd75cc07249fd7 Gerrit-Change-Number: 35783 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/x86: Add a prog_run hook to set up caching of XIP stages
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35993 ) Change subject: cpu/x86: Add a prog_run hook to set up caching of XIP stages ...................................................................... cpu/x86: Add a prog_run hook to set up caching of XIP stages Some platforms lack a non-eviction mode and therefore caching the whole ROM to speed up XIP stages can be dangerous as it could result in eviction if too much of the ROM is being accessed. The solution is to only cache a region, about the size of the stage that the bootblock is about to load: verstage and/or romstage. CR0.CD bits are not touched to do this, but this seems to work just fine on at least model_1067x and model_6ex. Change-Id: I94d5771a57ffd74d53db3e35fe169d77d7fbb8cd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/xip_cache.c 3 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35993/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a8cf54d..b316c1f 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -78,6 +78,16 @@ depends on !NO_FIXED_XIP_ROM_SIZE default 0x10000 +config SETUP_XIP_CACHE + bool + depends on C_ENVIRONMENT_BOOTBLOCK + depends on !NO_XIP_EARLY_STAGES + help + Select this option to set up an MTRR to cache XIP stages loaded + from the bootblock. This is useful on platforms lacking a + non-eviction mode and therefore need to be careful to avoid + eviction. + config CPU_ADDR_BITS int default 36 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..dc914de 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -7,3 +7,5 @@ romstage-y += debug.c postcar-y += debug.c ramstage-y += debug.c + +bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c new file mode 100644 index 0000000..a45944b --- /dev/null +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <program_loading.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> + +#define MAX_ROM_CACHE_SIZE (256 * KiB) + +void platform_prog_run(struct prog *prog) +{ + uint32_t base = region_device_offset(&prog->rdev); + uint32_t size = region_device_sz(&prog->rdev); + uint32_t end = base + size; + int mtrr_num = get_free_var_mtrr(); + uint32_t mtrr_mask_size = 4 * KiB; + struct cpuinfo_x86 cpu_info; + + get_fms(&cpu_info, cpuid_eax(1)); + if (cpu_info.x86 == 0xf) { + printk(BIOS_DEBUG, + "PROG_RUN: CPU does not support caching ROM\n" + "The next stage will run slowly\n"); + return; + } + + if (mtrr_num == -1) { + printk(BIOS_NOTICE, + "PROG_RUN: No MTRR available to cache ROM!\n" + "The next stage will run slowly!\n"); + return; + } + + while (ALIGN_DOWN(base, mtrr_mask_size) + mtrr_mask_size < end) + mtrr_mask_size *= 2; + base = ALIGN_DOWN(base, mtrr_mask_size); + if (mtrr_mask_size > MAX_ROM_CACHE_SIZE) { + printk(BIOS_WARNING, + "PROG_RUN: %dKiB XIP cache requested but limiting to %dKiB!", + mtrr_mask_size, MAX_ROM_CACHE_SIZE); + mtrr_mask_size = MAX_ROM_CACHE_SIZE; + } + + printk(BIOS_DEBUG, + "PROG_RUN: Setting MTRR to cache XIP stage. base: 0x%08x, size: 0x%08x\n", + base, mtrr_mask_size); + + set_var_mtrr(mtrr_num, base, mtrr_mask_size, MTRR_TYPE_WRPROT); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94d5771a57ffd74d53db3e35fe169d77d7fbb8cd Gerrit-Change-Number: 35993 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Add VBOOT support
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35997 ) Change subject: nb/intel/gm45: Add VBOOT support ...................................................................... nb/intel/gm45: Add VBOOT support Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35997/1 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 169dcac..1a6fe83 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,6 +29,10 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + config CBFS_SIZE hex default 0x100000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32 Gerrit-Change-Number: 35997 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: set FSP param to enable or skip GOP
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36350 ) Change subject: soc/intel/skylake: set FSP param to enable or skip GOP ...................................................................... soc/intel/skylake: set FSP param to enable or skip GOP Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36350/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 55fedd3..feb1339 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -501,6 +501,13 @@ params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } + /* Only initialize graphics if supported and enabled */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + soc_irq_settings(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7 Gerrit-Change-Number: 36350 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36355 ) Change subject: soc/intel/skylake: set LT_LOCK_MEMORY at end of POST ...................................................................... soc/intel/skylake: set LT_LOCK_MEMORY at end of POST Use the new common function to set LT_LOCK_MEMORY at end of POST to protect SMM in accordance to Intel BWG. Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/finalize.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36355/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 4cc9c83..58a8701 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -123,6 +124,9 @@ reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); } static void soc_finalize(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/36355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8 Gerrit-Change-Number: 36355 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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