Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36481 )
Change subject: mb/facebook/fbg1701: Remove confusing text boxes from menu
......................................................................
mb/facebook/fbg1701: Remove confusing text boxes from menu
The Kconfig contained some items that were only intended to
set a default and that now were displayed in two locations
in the menuconfig.
BUG=N/A
TEST=build
Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b
Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com>
---
M src/mainboard/facebook/fbg1701/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36481/1
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index a607705..e80b7fe 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -73,7 +73,7 @@
default n
config VENDORCODE_ELTAN_OEM_MANIFEST_LOC
- hex "OEM Manifest working dflt"
+ hex
default 0xFFFE9000
config SPI_FLASH_INCLUDE_ALL_DRIVERS
@@ -101,7 +101,7 @@
default "mainboard/facebook/fbg1701/manifest.h"
config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION
- hex "Key Location working dflt"
+ hex
default 0xFFFF9C00
endif # BOARD_FACEBOOK_FBG1701
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b
Gerrit-Change-Number: 36481
Gerrit-PatchSet: 1
Gerrit-Owner: Wim Vervoorn
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Wim Vervoorn
Gerrit-MessageType: newchange
EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36501 )
Change subject: mb/google/drallion: Add second touch pad support
......................................................................
mb/google/drallion: Add second touch pad support
Add second source touch pad with i2c address 0x15.
BUG=b:142629138
BRANCH=N/A
TEST=check new touch pad can work properly
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36501/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 1f628d6..0de2e94 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -373,6 +373,13 @@
register "probed" = "1"
device i2c 2c on end
end
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39
Gerrit-Change-Number: 36501
Gerrit-PatchSet: 1
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
......................................................................
soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and ask skl, cnl & icl soc code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/asrock/h110m/dsdt.asl
M src/mainboard/google/dragonegg/dsdt.asl
M src/mainboard/google/drallion/dsdt.asl
M src/mainboard/google/eve/dsdt.asl
M src/mainboard/google/fizz/dsdt.asl
M src/mainboard/google/glados/dsdt.asl
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/poppy/dsdt.asl
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/intel/cannonlake_rvp/dsdt.asl
M src/mainboard/intel/coffeelake_rvp/dsdt.asl
M src/mainboard/intel/icelake_rvp/dsdt.asl
M src/mainboard/intel/kblrvp/dsdt.asl
M src/mainboard/intel/kunimitsu/dsdt.asl
M src/mainboard/intel/saddlebrook/dsdt.asl
M src/mainboard/purism/librem_skl/dsdt.asl
M src/mainboard/razer/blade_stealth_kbl/dsdt.asl
M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
R src/soc/intel/common/block/acpi/acpi/sleepstates.asl
D src/soc/intel/icelake/acpi/sleepstates.asl
D src/soc/intel/skylake/acpi/sleepstates.asl
21 files changed, 21 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/1
diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl
index f3e216d..49919d8 100644
--- a/src/mainboard/asrock/h110m/dsdt.asl
+++ b/src/mainboard/asrock/h110m/dsdt.asl
@@ -48,7 +48,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
index 8a43784..65c7be2 100644
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ b/src/mainboard/google/dragonegg/dsdt.asl
@@ -49,7 +49,7 @@
#endif
// Chipset specific sleep states
- #include <soc/intel/icelake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index 5ffdf18..4d2c4bf 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -54,7 +54,7 @@
#endif
/* Chipset specific sleep states */
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl>
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
index a705457..bf207b7 100644
--- a/src/mainboard/google/eve/dsdt.asl
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -48,7 +48,7 @@
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl
index 03df2b9..112673c 100644
--- a/src/mainboard/google/fizz/dsdt.asl
+++ b/src/mainboard/google/fizz/dsdt.asl
@@ -48,7 +48,7 @@
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl
index af5f99d..6fe0cbd 100644
--- a/src/mainboard/google/glados/dsdt.asl
+++ b/src/mainboard/google/glados/dsdt.asl
@@ -49,7 +49,7 @@
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 344e4a7..fd3df6e 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -52,10 +52,10 @@
#endif
/* Chipset specific sleep states */
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
- /* Low power idle table */
- #include <soc/intel/cannonlake/acpi/lpit.asl>
+ /* Low power idle table */
+ #include <soc/intel/cannonlake/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index 34862df..dd02606 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -55,7 +55,7 @@
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 22e283f..5cfde62 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -54,7 +54,7 @@
#endif
/* Chipset specific sleep states */
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl>
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 5f4a349..4b7454c 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -45,6 +45,6 @@
#endif
// Chipset specific sleep states
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
}
diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
index c5f1136..952f345 100644
--- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
@@ -45,6 +45,6 @@
#endif
// Chipset specific sleep states
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
}
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 15890f1..c84e41a 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -60,7 +60,7 @@
#endif
// Chipset specific sleep states
- #include <soc/intel/icelake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl
index 8a16551..83db423 100644
--- a/src/mainboard/intel/kblrvp/dsdt.asl
+++ b/src/mainboard/intel/kblrvp/dsdt.asl
@@ -57,7 +57,7 @@
#endif
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl
index af5f99d..6fe0cbd 100644
--- a/src/mainboard/intel/kunimitsu/dsdt.asl
+++ b/src/mainboard/intel/kunimitsu/dsdt.asl
@@ -49,7 +49,7 @@
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl
index ac929a6..eb053b1 100644
--- a/src/mainboard/intel/saddlebrook/dsdt.asl
+++ b/src/mainboard/intel/saddlebrook/dsdt.asl
@@ -43,7 +43,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl
index 1bf202e..14525d7 100644
--- a/src/mainboard/purism/librem_skl/dsdt.asl
+++ b/src/mainboard/purism/librem_skl/dsdt.asl
@@ -44,7 +44,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl
index e110067..72184eb 100644
--- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl
+++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl
@@ -43,7 +43,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
#include "acpi/mainboard.asl"
}
diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
index ac929a6..eb053b1 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
+++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
@@ -43,7 +43,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl
similarity index 94%
rename from src/soc/intel/cannonlake/acpi/sleepstates.asl
rename to src/soc/intel/common/block/acpi/acpi/sleepstates.asl
index 2a351b6..1ab0e68 100644
--- a/src/soc/intel/cannonlake/acpi/sleepstates.asl
+++ b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017-2018 Intel Corp.
+ * Copyright (C) 2019 Intel Corp.
*
*
* This program is free software; you can redistribute it and/or modify
diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/soc/intel/icelake/acpi/sleepstates.asl
deleted file mode 100644
index 13cc358..0000000
--- a/src/soc/intel/icelake/acpi/sleepstates.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 })
-Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 })
-Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl
deleted file mode 100644
index 905a3e2..0000000
--- a/src/soc/intel/skylake/acpi/sleepstates.asl
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 })
-Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 })
-Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 })
-Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Gerrit-Change-Number: 36463
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange