Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 2:
> Patch Set 2:
>
> Hmmm, it doesn't have the anticipated effect :-/ I would have
> expected a Verified -1, because aspeed/ isn't fixed yet. But
> the error is only triggered with NO_GFX_INIT in the config and
> that's not the default... I guess there is nothing we can do?
I guess no (without adding some "CONFIG_JENKINS_TEST" or whatever) :S
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 )
Change subject: sdm845: Add SPI QUP driver
......................................................................
Patch Set 58:
(1 comment)
https://review.coreboot.org/c/coreboot/+/27483/42/src/soc/qualcomm/sdm845/s…
File src/soc/qualcomm/sdm845/spi_qup.c:
https://review.coreboot.org/c/coreboot/+/27483/42/src/soc/qualcomm/sdm845/s…
PS42, Line 229: write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq);
> Made changes in this driver to clear interrupt only after handling it, because recently we ran into […]
I see... sounds like your hardware works different than most I have seen. Normally, I would expect that the hardware takes the reading of the FIFO register itself (geni_rx_fifon) as a signal that there's space in the FIFO again now and it can start fetching more bytes. In that case you want to clear the interrupt before reading the FIFO register, because otherwise it may be possible that after you read the FIFO register but before you cleared the interrupt the hardware would already have fetched new data into the FIFO. It would not assert the interrupt again for that new data (because it is still set), then software advances to the point where it clears the interrupt, and then software doesn't know that there's still data stuck in the FIFO (because it won't assert another interrupt) and might get hung.
In this case, if the hardware really takes the clearing of the interrupt rather than the draining of the FIFO as the signal to start fetching more data, your previous code was correct (first drain FIFO, then clear interrupt). Sorry for leading you the wrong way. (Then again, this would be much easier for me if I had access to documentation describing these sorts of hardware behavior details...)
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 2:
Hmmm, it doesn't have the anticipated effect :-/ I would have
expected a Verified -1, because aspeed/ isn't fixed yet. But
the error is only triggered with NO_GFX_INIT in the config and
that's not the default... I guess there is nothing we can do?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 )
Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2: Code-Review+2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36515 )
Change subject: soc/intel: common,apl,skl: remove orphaned memory locking API
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/skylake: select the new SGX Kconfig option for LT_LOCK_MEMORY
......................................................................
Patch Set 1: Code-Review+2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36513 )
Change subject: soc/intel/common: sgx: add new Kconfig option for setting LT_LOCK_MEMORY
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35499
to look at the new patch set (#12).
Change subject: sc7180: Add QUPv3 FW load & config
......................................................................
sc7180: Add QUPv3 FW load & config
UART driver requires firmware loading
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25372/78https://review.coreboot.org/c/coreboot/+/27483/58
Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31
Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org>
---
M src/mainboard/google/trogdor/mainboard.c
M src/soc/qualcomm/sc7180/Makefile.inc
M src/soc/qualcomm/sc7180/bootblock.c
M src/soc/qualcomm/sc7180/include/soc/addressmap.h
A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h
A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h
A src/soc/qualcomm/sc7180/include/soc/qupv3_fw_config.h
A src/soc/qualcomm/sc7180/qcom_qup_se.c
A src/soc/qualcomm/sc7180/qupv3_config.c
A src/soc/qualcomm/sc7180/qupv3_fw_config.c
10 files changed, 1,057 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/12
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 )
Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2:
This change is ready for review.
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