coreboot-gerrit October 2019

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Change in coreboot[master]: soc/intel/sgx: make SGX a Kconfig option
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35799 ) Change subject: soc/intel/sgx: make SGX a Kconfig option ...................................................................... soc/intel/sgx: make SGX a Kconfig option This removes the devicetree parameter sgx_enable and add a Kconfig option instead, as the devictree is not made for user-choosable options. Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c 10 files changed, 19 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35799/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index d3d0b00..9277f08 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -97,8 +97,6 @@ # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" - register "sgx_enable" = "1" - # PRMRR size options # 0x02000000 - 32MiB # 0x04000000 - 64MiB diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index a5ff0c5..0c42edd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -17,8 +17,6 @@ register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" - # Disable SGX - register "sgx_enable" = "0" # SGX is broken in coreboot register "PrmrrSize" = "128 * MiB" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9..3fdc646 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -145,12 +145,6 @@ * 0x08000000 - 128MiB */ uint32_t PrmrrSize; - /* Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size */ - uint8_t sgx_enable; - /* Select PNP Settings. * (0) Performance, * (1) Power diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3349627..4ec714f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -293,11 +293,3 @@ /* Do nothing because MCHECK while loading microcode and enabling * IA untrusted mode takes care of necessary locking */ } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 77711eb..5cdd43b 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,11 +35,11 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) { + config = config_of_soc(); tolum -= config->PrmrrSize * 2; + } return tolum; } diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 502483f..693dd20 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -18,10 +18,6 @@ #include <soc/nvs.h> -struct sgx_param { - uint8_t enable; -}; - /* * Lock SGX memory. * CPU specific code needs to provide the implementation. @@ -40,10 +36,6 @@ */ void sgx_configure(void *unused); -/* SOC specific API to get SGX params. - * returns 0, if able to get SGX params; otherwise returns -1 */ -int soc_fill_sgx_param(struct sgx_param *sgx_param); - /* Fill GNVS data with SGX status, EPC base and length */ void sgx_fill_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 0852bfb..78284fb 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -2,6 +2,12 @@ bool default n help - Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU - instructions that can be used by applications to set aside private - regions of code and data. + Intel Processor common SGX support + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool + depends on SOC_INTEL_COMMON_BLOCK_SGX + default n + help + Software Guard eXtension (SGX) Feature. Intel SGX is a set of new CPU instructions + that can be used by applications to set aside private regions of code and data. diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 60714d9..4567e13 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -25,9 +25,6 @@ #include <soc/pci_devs.h> #include <string.h> -static bool sgx_param_valid; -static struct sgx_param g_sgx_param; - static inline uint64_t sgx_resource(uint32_t low, uint32_t high) { uint64_t val; @@ -36,28 +33,6 @@ return val; } -static const struct sgx_param *get_sgx_param(void) -{ - if (sgx_param_valid) - return &g_sgx_param; - - memset(&g_sgx_param, 0, sizeof(g_sgx_param)); - if (soc_fill_sgx_param(&g_sgx_param) < 0) { - printk(BIOS_ERR, "SGX : Failed to get soc sgx param\n"); - return NULL; - } - sgx_param_valid = true; - printk(BIOS_INFO, "SGX : param.enable = %d\n", g_sgx_param.enable); - - return &g_sgx_param; -} - -static int soc_sgx_enabled(void) -{ - const struct sgx_param *sgx_param = get_sgx_param(); - return sgx_param ? sgx_param->enable : 0; -} - static int is_sgx_supported(void) { struct cpuid_result cpuid_regs; @@ -79,7 +54,7 @@ } prmrr_base, prmrr_mask; msr_t msr; - if (!soc_sgx_enabled() || !is_sgx_supported()) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || !is_sgx_supported()) return; msr = rdmsr(MSR_PRMRR_PHYS_MASK); @@ -204,7 +179,7 @@ { const void *microcode_patch = intel_mp_current_microcode(); - if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || !is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; } @@ -234,7 +209,7 @@ { struct cpuid_result cpuid_regs; - if (!soc_sgx_enabled() || !is_sgx_supported()) { + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || !is_sgx_supported()) { printk(BIOS_DEBUG, "SGX: not enabled or not supported. skip gnvs fill\n"); return; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 944315b..626d36b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -576,9 +576,6 @@ u8 SlowSlewRateForGt; u8 SlowSlewRateForSa; - /* Enable SGX feature */ - u8 sgx_enable; - /* Enable/Disable EIST * 1b - Enabled * 0b - Disabled diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5424c91..26cc533 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -455,7 +455,8 @@ enable_turbo(); /* Configure Core PRMRR for SGX. */ - prmrr_core_configure(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + prmrr_core_configure(); } static void per_cpu_smm_trigger(void) @@ -493,7 +494,8 @@ ret |= mp_run_on_all_cpus(vmx_configure, NULL); - ret |= mp_run_on_all_cpus(sgx_configure, NULL); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); @@ -559,11 +561,3 @@ wrmsr(MSR_LT_LOCK_MEMORY, msr); } } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Gerrit-Change-Number: 35799 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to commo...
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36137 ) Change subject: soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to common code ...................................................................... soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to common code As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/ebda/ebda.c M src/soc/intel/common/block/include/intelblocks/ebda.h A src/soc/intel/common/block/memmap/Kconfig A src/soc/intel/common/block/memmap/Makefile.inc R src/soc/intel/common/block/memmap/memmap.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/Makefile.inc 11 files changed, 26 insertions(+), 323 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36137/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141..1588bde 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock/report_platform.c bootblock-y += gspi.c bootblock-y += i2c.c -bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += p2sb.c @@ -26,7 +25,6 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += lpc.c -romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -44,7 +42,6 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c ramstage-y += pmc.c @@ -66,7 +63,6 @@ smm-y += uart.c smm-y += xhci.c -postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c deleted file mode 100644 index 4973e8d..0000000 --- a/src/soc/intel/cannonlake/memmap.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <fsp/util.h> -#include <intelblocks/ebda.h> -#include <intelblocks/systemagent.h> -#include <stdlib.h> - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry fsp_mem; - struct range_entry tolum; - - /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - if (fsp_find_bootloader_tolum(&tolum)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); - - /* Locate the FSP reserved memory area */ - if (fsp_find_reserved_memory(&fsp_mem)) - die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - - cfg->tolum_end = range_entry_end(&tolum); - cfg->reserved_mem_size = range_entry_size(&fsp_mem); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_end; -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c index 6b0bd67..072023c 100644 --- a/src/soc/intel/common/block/ebda/ebda.c +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -17,34 +17,14 @@ #include <intelblocks/ebda.h> #include <string.h> -/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ - -/* Fill up EBDA structure inside Mainboard directory */ -__weak void create_mainboard_ebda(struct ebda_config *cfg) -{ - /* no-op */ -} - -static void create_soc_ebda(struct ebda_config *cfg) -{ - /* Create EBDA header */ - cfg->signature = EBDA_SIGNATURE; - /* Fill up memory layout information */ - fill_soc_memmap_ebda(cfg); -} - -void fill_ebda_area(void) +void initialize_ebda_area(void) { struct ebda_config ebda_cfg; /* Initialize EBDA area early during romstage. */ setup_default_ebda(); - create_soc_ebda(&ebda_cfg); - create_mainboard_ebda(&ebda_cfg); + ebda_cfg.signature = EBDA_SIGNATURE; + fill_memmap_ebda(&ebda_cfg); write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); } diff --git a/src/soc/intel/common/block/include/intelblocks/ebda.h b/src/soc/intel/common/block/include/intelblocks/ebda.h index 16124df..1770e8f 100644 --- a/src/soc/intel/common/block/include/intelblocks/ebda.h +++ b/src/soc/intel/common/block/include/intelblocks/ebda.h @@ -16,52 +16,24 @@ #ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H #define SOC_INTEL_COMMON_BLOCK_EBDA_H -#include <soc/ebda.h> - #define EBDA_SIGNATURE 0xebdaebda -/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ +/* EBDA structure */ +struct ebda_config { + uint32_t signature; /* EBDA signature */ + uint32_t tolum_end; /* coreboot memory start */ + uint32_t reserved_mem_size; /* chipset reserved memory size */ +}; -/* Fill up EBDA structure inside Mainboard directory */ -void create_mainboard_ebda(struct ebda_config *cfg); +/* Initialize EBDA and store structure into EBDA area */ +void initialize_ebda_area(void); /* - * SoC overrides - * - * All new SoC must implement below functionality for romstage. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg); - -/* - * API to perform below operation - * 1. Initialize EBDA area - * 2. Fill up EBDA structure inside SOC directory - * 3. Fill up EBDA structure inside Mainboard directory - * 4. Store EBDA structure into EBDA area - */ -void fill_ebda_area(void); - -/* Fill the ebda object pointed to by cfg. Object will be zero filled + * Fill the ebda object pointed to by cfg. Object will be zero filled * if signature check fails. */ void retrieve_ebda_object(struct ebda_config *cfg); -/* - * EBDA structure - * - * SOC should implement EBDA structure as per need - * as below. - * - * Note: First 4 bytes should be reserved for signature as - * 0xEBDA - * - * struct ebda_config { - * uint32_t signature; - * <Required variables..> - * }; - */ +/* API for filling ebda with data */ +void fill_memmap_ebda(struct ebda_config *cfg); #endif diff --git a/src/soc/intel/common/block/memmap/Kconfig b/src/soc/intel/common/block/memmap/Kconfig new file mode 100644 index 0000000..677400b --- /dev/null +++ b/src/soc/intel/common/block/memmap/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_MEMMAP + bool + select SOC_INTEL_COMMON_BLOCK_EBDA + help + Intel Processor common MEMMAP library support diff --git a/src/soc/intel/common/block/memmap/Makefile.inc b/src/soc/intel/common/block/memmap/Makefile.inc new file mode 100644 index 0000000..8da9815 --- /dev/null +++ b/src/soc/intel/common/block/memmap/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMMAP) += memmap.c diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/common/block/memmap/memmap.c similarity index 96% rename from src/soc/intel/skylake/memmap.c rename to src/soc/intel/common/block/memmap/memmap.c index e98bf51..03ef3b8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/common/block/memmap/memmap.c @@ -46,7 +46,7 @@ } /* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) +void fill_memmap_ebda(struct ebda_config *cfg) { struct range_entry fsp_mem; struct range_entry tolum; @@ -65,8 +65,8 @@ void cbmem_top_init(void) { - /* Fill up EBDA area */ - fill_ebda_area(); + /* Initialize EBDA area */ + initialize_ebda_area(); } /* diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 7ece9549..c8c4c24 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -20,6 +20,7 @@ select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_MEMMAP select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030..401b446 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c -bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += p2sb.c bootblock-y += uart.c @@ -26,7 +25,6 @@ romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -44,7 +42,6 @@ ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -62,7 +59,6 @@ smm-y += smihandler.c smm-y += uart.c -postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c deleted file mode 100644 index 9c7f067..0000000 --- a/src/soc/intel/icelake/memmap.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <fsp/util.h> -#include <intelblocks/ebda.h> -#include <intelblocks/systemagent.h> -#include <stdlib.h> - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry fsp_mem; - struct range_entry tolum; - - /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - if (fsp_find_bootloader_tolum(&tolum)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); - - /* Locate the FSP reserved memory area */ - if (fsp_find_reserved_memory(&fsp_mem)) - die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - - cfg->tolum_end = range_entry_end(&tolum); - cfg->reserved_mem_size = range_entry_size(&fsp_mem); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_end; -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..dce1d6b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += memmap.c romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c @@ -55,7 +54,6 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -77,7 +75,6 @@ smm-y += uart.c smm-y += xhci.c -postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c postcar-y += i2c.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Gerrit-Change-Number: 36137 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 64

Change in coreboot[master]: soc/intel: skl,cnl,icl: rely on TOLUM and reserved memory returned by...
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36136 ) Change subject: soc/intel: skl,cnl,icl: rely on TOLUM and reserved memory returned by FSP ...................................................................... soc/intel: skl,cnl,icl: rely on TOLUM and reserved memory returned by FSP Instead of doing our own calculations, rely on the TOLUM and reserved memory size returned by FSP. This (hopefully) saves us from making mistakes in calculations of offsets and aligments. Further this makes it easier to implement e.g. SGX PRMRR size selection via Kconfig as we do not have to know anything and do not have to make any assumptions about aligning but simply pass (valid) values to FSP. Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/include/soc/ebda.h M src/soc/intel/skylake/memmap.c 4 files changed, 43 insertions(+), 533 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/36136/1 diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index f3286cc..b2fcad0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -28,8 +28,7 @@ #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <stdlib.h> - -#include "chip.h" +#include <fsp/util.h> void smm_region(uintptr_t *start, size_t *size) { @@ -37,161 +36,6 @@ *size = sa_get_tseg_size(); } -/* Calculate ME Stolen size */ -static size_t get_imr_size(void) -{ - size_t imr_size; - - /* ME stolen memory */ - imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE); - - return imr_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_cannonlake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - prmrr_size = config->PrmrrSize; - - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - else - prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB); - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Me stolen memory and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_cannonlake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_imr_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - -/* - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - const struct device *dev; - - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "ERROR - IGD device not found!"); - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - /* * SoC implementation * @@ -210,10 +54,19 @@ /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry fsp_mem; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + if (fsp_find_bootloader_tolum(&tolum)) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + + /* Locate the FSP reserved memory area */ + if (fsp_find_reserved_memory(&fsp_mem)) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + cfg->tolum_end = range_entry_end(&tolum); + cfg->reserved_mem_size = range_entry_size(&fsp_mem); } void cbmem_top_init(void) @@ -253,15 +106,6 @@ { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); return (void *)(uintptr_t)ebda_cfg.tolum_base; diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 20c4e6f..9df1065 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -28,6 +28,7 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <stdlib.h> +#include <fsp/util.h> void smm_region(uintptr_t *start, size_t *size) { @@ -35,161 +36,6 @@ *size = sa_get_tseg_size(); } -/* Calculate ME Stolen size */ -static size_t get_imr_size(void) -{ - size_t imr_size; - - /* ME stolen memory */ - imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE); - - return imr_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_icelake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - prmrr_size = config->PrmrrSize; - - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - else - prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB); - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Me stolen memory and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_icelake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_imr_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - -/* - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - const struct device *dev; - - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "ERROR - IGD device not found!"); - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - /* * SoC implementation * @@ -208,10 +54,19 @@ /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry fsp_mem; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + if (fsp_find_bootloader_tolum(&tolum)) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + + /* Locate the FSP reserved memory area */ + if (fsp_find_reserved_memory(&fsp_mem)) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + cfg->tolum_end = range_entry_end(&tolum); + cfg->reserved_mem_size = range_entry_size(&fsp_mem); } void cbmem_top_init(void) @@ -251,18 +106,9 @@ { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)(uintptr_t)ebda_cfg.tolum_end; } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h index ad62394..d588c18 100644 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ b/src/soc/intel/skylake/include/soc/ebda.h @@ -20,8 +20,8 @@ struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ - uint32_t tolum_base; /* 0x04 - coreboot memory start */ - uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */ + uint32_t tolum_end; /* 0x04 - coreboot memory start */ + uint32_t reserved_mem_size; /* 0x0C - chipset reserved memory size */ }; #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 29f2517..5c4cc3a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -29,8 +29,7 @@ #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <stdlib.h> - -#include "chip.h" +#include <fsp/util.h> void smm_region(uintptr_t *start, size_t *size) { @@ -38,185 +37,6 @@ *size = sa_get_tseg_size(); } -static bool is_ptt_enable(void) -{ - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) - return true; - - return false; -} - -/* Calculate PTT size */ -static size_t get_ptt_size(void) -{ - /* Allocate 4KB for PTT if enabled */ - return is_ptt_enable() ? 4*KiB : 0; -} - -/* Calculate Trace Hub size */ -static size_t get_tracehub_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) -{ - uintptr_t tracehub_base = dram_base; - size_t tracehub_size = 0; - - if (!config->ProbelessTrace) - return 0; - - /* GDXC MOT */ - tracehub_base -= GDXC_MOT_MEMORY_SIZE; - /* Round down to natural boundary according to PSMI size */ - tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE); - /* GDXC IOT */ - tracehub_base -= GDXC_IOT_MEMORY_SIZE; - /* PSMI buffer area */ - tracehub_base -= PSMI_BUFFER_AREA_SIZE; - - /* Tracehub Area Size */ - tracehub_size = dram_base - tracehub_base; - - return tracehub_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - if (CONFIG(PLATFORM_USES_FSP1_1)) - prmrr_size = 1*MiB; - else - prmrr_size = config->PrmrrSize; - - if (!prmrr_size) - return 0; - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base) -{ - const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (igd_dev && igd_dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Trace Hub config and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base) -{ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_skylake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_tracehub_size(reserve_mem_base, config); - - /* Get PTT size */ - reserve_mem_base -= get_ptt_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - -/* - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | Trace Memory | - * +--------------------------+ Probless Trace - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - /* * SoC implementation * @@ -235,10 +55,19 @@ /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry fsp_mem; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + if (fsp_find_bootloader_tolum(&tolum)) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + + /* Locate the FSP reserved memory area */ + if (fsp_find_reserved_memory(&fsp_mem)) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + cfg->tolum_end = range_entry_end(&tolum); + cfg->reserved_mem_size = range_entry_size(&fsp_mem); } void cbmem_top_init(void) @@ -278,18 +107,9 @@ { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)(uintptr_t)ebda_cfg.tolum_end; } #if CONFIG(PLATFORM_USES_FSP2_0) -- To view, visit https://review.coreboot.org/c/coreboot/+/36136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Gerrit-Change-Number: 36136 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

6 66

Change in coreboot[master]: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value
by HAOUAS Elyes (Code Review) 04 Nov '19

04 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36458 ) Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ...................................................................... sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/acpi/lpc.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/1 diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 87eab07..793545d 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -79,7 +79,7 @@ Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status -- To view, visit https://review.coreboot.org/c/coreboot/+/36458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Gerrit-Change-Number: 36458 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: nb/i945: Use defined DEFAULT_RCBA
by HAOUAS Elyes (Code Review) 04 Nov '19

04 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36464 ) Change subject: nb/i945: Use defined DEFAULT_RCBA ...................................................................... nb/i945: Use defined DEFAULT_RCBA Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/1 diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 7a9715c..73ff17b 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -16,6 +16,7 @@ #include "hostbridge.asl" #include "../i945.h" +#include "src/southbridge/intel/common/rcba.h" /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -51,7 +52,7 @@ //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Gerrit-Change-Number: 36464 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel: Remove unsued code
by Patrick Rudolph (Code Review) 04 Nov '19

04 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35207 ) Change subject: soc/intel: Remove unsued code ...................................................................... soc/intel: Remove unsued code Delete acpi_create_intel_hpet() which has been replaced by acpi_write_hpet() in the corresponding soc folders some time ago. Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h 9 files changed, 0 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35207/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c322cce..db6b271 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -131,37 +131,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 29acda7..2851f92 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc00..c0455b4 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -185,37 +185,6 @@ #endif } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 24fe3ae..d075464 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -25,7 +25,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 5de58ea..5ab77e0 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -21,7 +21,6 @@ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..565c181 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -128,37 +128,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h index 27b7000..917419e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ b/src/soc/intel/fsp_baytrail/include/soc/acpi.h @@ -21,7 +21,6 @@ #include <soc/nvs.h> #include <device/device.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 6b1d3f6..e8aebe2 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -114,36 +114,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index 44e17d0..419f229 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -20,7 +20,6 @@ #include <arch/acpi.h> -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); uint16_t get_pmbase(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/35207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Gerrit-Change-Number: 35207 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: nb/intel/nehalem: Fix 'dead increment'
by HAOUAS Elyes (Code Review) 04 Nov '19

04 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36135 ) Change subject: nb/intel/nehalem: Fix 'dead increment' ...................................................................... nb/intel/nehalem: Fix 'dead increment' Dead increment spotted out using clang-tools. Value stored to 'some_delay_3_halfcycles' is never read. Change-Id: I8133f9e8786006bd278d281a132b6a2bd863a967 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/36135/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 1fca4c4..f24d643 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -825,7 +825,6 @@ int some_delay_1_cycle_ceil; int some_delay_1_cycle_floor; - some_delay_3_halfcycles = 0; some_delay_3_ps_rounded = 0; extended_silicon_revision = info->silicon_revision; if (!info->silicon_revision) -- To view, visit https://review.coreboot.org/c/coreboot/+/36135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8133f9e8786006bd278d281a132b6a2bd863a967 Gerrit-Change-Number: 36135 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: cbfs: store header offset as absolute value BE from fmap_top
by Marty E. Plummer (Code Review) 04 Nov '19

04 Nov '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36346 ) Change subject: cbfs: store header offset as absolute value BE from fmap_top ...................................................................... cbfs: store header offset as absolute value BE from fmap_top Change-Id: Idc99b0c133faa2aa15d06f998e7371d332ffa490 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/lib/cbfs.c M util/cbfstool/cbfstool.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36346/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..8fb747f 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -296,13 +296,14 @@ size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; - /* Find location of header using signed 32-bit offset from + /* Find location of header using unsigned 32-bit offset from * end of CBFS region. */ offset = fmap_top - sizeof(int32_t); if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) return -1; - offset = fmap_top + rel_offset; + /* Subtract after converting to the native byte ordering */ + offset = fmap_top - ntohl(rel_offset); if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) return -1; diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 65c5e08..c829005 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -285,8 +285,8 @@ static void fill_header_offset(void *location, uint32_t offset) { - // TODO: When we have a BE target, we'll need to store this as BE - write_le32(location, offset); + // Store as BE as all other cbfs data structures are + write_be32(location, offset); } static int update_master_header_loc_topswap(struct cbfs_image *image, @@ -380,7 +380,10 @@ uint32_t header_offset = CBFS_SUBHEADER(entry) - buffer_get(&image.buffer); - header_offset = -(buffer_size(&image.buffer) - header_offset); + /* Store as absolute value (positive) and subtract + * it in src/lib/cbfs.c:cbfs_master_header_props + */ + header_offset = buffer_size(&image.buffer) - header_offset; h_loc = (void *)(buffer_get(&image.buffer) + buffer_size(&image.buffer) - 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/36346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc99b0c133faa2aa15d06f998e7371d332ffa490 Gerrit-Change-Number: 36346 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: mb/google/hatch: update DLL values for Kindred
by Jamie Chen (Code Review) 04 Nov '19

04 Nov '19

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36076 ) Change subject: mb/google/hatch: update DLL values for Kindred ...................................................................... mb/google/hatch: update DLL values for Kindred Update emmc DLL values for Kindred BUG=b:131401116 BRANCH=none TEST=Boot to OS 100 times on Kindred EVT Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/hatch/variants/kindred/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36076/1 diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 272cbfb..9d33fa9 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -61,7 +61,7 @@ # Refer to EDS-Vol2-14.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x0F10" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-14.3.9. @@ -69,7 +69,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2F2D2D" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-14.3.10. @@ -77,7 +77,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C121936" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-14.3.12. @@ -88,13 +88,13 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1182D" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-14.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/36076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Gerrit-Change-Number: 36076 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: include: Remove EC_EVENT_* from elog.h
by Yu-Ping Wu (Code Review) 04 Nov '19

04 Nov '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36499 ) Change subject: include: Remove EC_EVENT_* from elog.h ...................................................................... include: Remove EC_EVENT_* from elog.h All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_* macros defined in ec_commands.h, which is synchronized from Chromium OS ec repository. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/include/elog.h M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/ec.c 4 files changed, 14 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/36499/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 32f06bb..48102d3 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -97,7 +97,7 @@ static void google_chromeec_elog_add_recovery_event(void *unused) { uint64_t *events = cbmem_find(CBMEM_ID_EC_HOSTEVENT); - uint8_t event_byte = EC_EVENT_KEYBOARD_RECOVERY; + uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY; if (!events) return; @@ -107,7 +107,7 @@ if (*events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)) - event_byte = EC_EVENT_KEYBOARD_RECOVERY_HWREINIT; + event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT; elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte); } diff --git a/src/include/elog.h b/src/include/elog.h index 0328a86..1692a80 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -61,37 +61,6 @@ /* Embedded controller event */ #define ELOG_TYPE_EC_EVENT 0x91 -#define EC_EVENT_LID_CLOSED 0x01 -#define EC_EVENT_LID_OPEN 0x02 -#define EC_EVENT_POWER_BUTTON 0x03 -#define EC_EVENT_AC_CONNECTED 0x04 -#define EC_EVENT_AC_DISCONNECTED 0x05 -#define EC_EVENT_BATTERY_LOW 0x06 -#define EC_EVENT_BATTERY_CRITICAL 0x07 -#define EC_EVENT_BATTERY 0x08 -#define EC_EVENT_THERMAL_THRESHOLD 0x09 -#define EC_EVENT_DEVICE_EVENT 0x0a -#define EC_EVENT_THERMAL 0x0b -#define EC_EVENT_USB_CHARGER 0x0c -#define EC_EVENT_KEY_PRESSED 0x0d -#define EC_EVENT_INTERFACE_READY 0x0e -#define EC_EVENT_KEYBOARD_RECOVERY 0x0f -#define EC_EVENT_THERMAL_SHUTDOWN 0x10 -#define EC_EVENT_BATTERY_SHUTDOWN 0x11 -#define EC_EVENT_FAN_ERROR 0x12 -#define EC_EVENT_THROTTLE_STOP 0x13 -#define EC_EVENT_HANG_DETECT 0x14 -#define EC_EVENT_HANG_REBOOT 0x15 -#define EC_EVENT_PD_MCU 0x16 -#define EC_EVENT_BATTERY_STATUS 0x17 -#define EC_EVENT_PANIC 0x18 -#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 -#define EC_EVENT_RTC 0x1a -#define EC_EVENT_MKBP 0x1b -#define EC_EVENT_USB_MUX 0x1c -#define EC_EVENT_MODE_CHANGE 0x1d -#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e -#define EC_EVENT_EXTENDED 0x1f /* Power */ #define ELOG_TYPE_POWER_FAIL 0x92 diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 5883cdc..92d361d 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -42,7 +42,7 @@ #if CONFIG(ELOG_GSMI) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_EVENT_BATTERY_CRITICAL); + EC_HOST_EVENT_BATTERY_CRITICAL); battery_critical_logged = 1; #endif break; @@ -50,7 +50,8 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); + elog_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_LID_CLOSED); #endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); @@ -71,7 +72,8 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); + elog_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_LID_CLOSED); #endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index a54b80b..660bb76 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -76,7 +76,8 @@ printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR); + elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + EC_HOST_EVENT_THROTTLE_START); #endif } @@ -86,7 +87,8 @@ printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL); + elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + EC_HOST_EVENT_THERMAL); #endif } @@ -98,14 +100,15 @@ printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); + elog_add_event_word(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_BATTERY_CRITICAL); #endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY); + elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY); #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/36499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Gerrit-Change-Number: 36499 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019