coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/Kconfig: Drop unused DEBUG_ACPI
by HAOUAS Elyes (Code Review) 05 Nov '19

05 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36498 ) Change subject: src/Kconfig: Drop unused DEBUG_ACPI ...................................................................... src/Kconfig: Drop unused DEBUG_ACPI Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36498/1 diff --git a/src/Kconfig b/src/Kconfig index 2b41ff2..defe4e4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -828,17 +828,6 @@ # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. -config DEBUG_ACPI - prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 - bool - default n - help - This option enables additional ACPI related debug messages. - - Note: This option will slightly increase the size of the coreboot image. - - If unsure, say N. - config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Gerrit-Change-Number: 36498 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Disable i8042 support
by Patrick Rudolph (Code Review) 05 Nov '19

05 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36078 ) Change subject: mb/supermicro/x11-lga1151-series: Disable i8042 support ...................................................................... mb/supermicro/x11-lga1151-series: Disable i8042 support Even though the vendor firmware enables the i8042 I/O port, it doesn't feed valid data to those, but instead uses USB HID devices. Disable the KBC port in SuperI/O and report no KCS port using FADT. Fixes: * Fixes error message in Linux that i8042 keyboard couldn't be enabled. Tested on Supermicro X11SSH-TF: The virtual remote managment console still works. Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb 2 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36078/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 541b23d..069e65a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -12,6 +12,7 @@ select SUPERIO_ASPEED_AST2400 select GENERATE_SMBIOS_TABLES select IPMI_KCS + select NO_FADT_8042 if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 09aa8b5..d08cc36 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -78,12 +78,7 @@ io 0x66 = 0xa30 irq 0x70 = 0xb end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 0xc - end + device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO device pnp 2e.b on # SUART3 io 0x60 = 0x3e8 -- To view, visit https://review.coreboot.org/c/coreboot/+/36078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Gerrit-Change-Number: 36078 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: cpu/x86/mp_init: Wait longer with serial enabled
by Patrick Rudolph (Code Review) 05 Nov '19

05 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34570 ) Change subject: cpu/x86/mp_init: Wait longer with serial enabled ...................................................................... cpu/x86/mp_init: Wait longer with serial enabled In case of slow serial wait longer for MP init to pickup jobs. This fixes a crash observed on KBL with 8core CPU as the task is stored on the BSP stack, which is reused for something else if the APs are to slow. Tested on SuperMicro X11SSH-TF. Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34570/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149..8ff214e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -892,6 +892,19 @@ } mfence(); + if (CONFIG(CONSOLE_SERIAL)) { + /* The serial console is slow and has a spinlock. + * It can take a while for all APs to pickup the work, + * especially with modern multicore CPUs. + * + * Wait longer than requested, otherwise we will return early + * and the stack containing the AP work will be reused for + * something else, causing the APs to crash. + * + * 100msec seems to be sufficent on 8core platform. + */ + expire_us = 100 * USECS_PER_MSEC; + } /* Wait for all the APs to signal back that call has been accepted. */ if (expire_us > 0) stopwatch_init_usecs_expire(&sw, expire_us); -- To view, visit https://review.coreboot.org/c/coreboot/+/34570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Gerrit-Change-Number: 34570 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 26

Change in coreboot[master]: soc/intel/common: Don't link CAR teardown in romstage
by Arthur Heymans (Code Review) 05 Nov '19

05 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36166 ) Change subject: soc/intel/common: Don't link CAR teardown in romstage ...................................................................... soc/intel/common: Don't link CAR teardown in romstage This is done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Makefile.inc 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/36166/1 diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index a6c4f37..857bf0f 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -3,7 +3,6 @@ bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S -- To view, visit https://review.coreboot.org/c/coreboot/+/36166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Gerrit-Change-Number: 36166 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: [TEST-ONLY]Set STAPM percentage for Treeya
by Peichao Li (Code Review) 05 Nov '19

05 Nov '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35042 ) Change subject: [TEST-ONLY]Set STAPM percentage for Treeya ...................................................................... [TEST-ONLY]Set STAPM percentage for Treeya Tuning stapm percent from 80 to 68 meet our thermal requirement BUG=None TEST=build and boot treeya Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35042/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index beb99e0..7005644 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -20,7 +20,7 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "16 * MiB" - register "stapm_percent" = "80" + register "stapm_percent" = "68" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" -- To view, visit https://review.coreboot.org/c/coreboot/+/35042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 Gerrit-Change-Number: 35042 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/asrock/h110m/devicetree: update VR config info
by Maxim Polyakov (Code Review) 04 Nov '19

04 Nov '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36378 ) Change subject: mb/asrock/h110m/devicetree: update VR config info ...................................................................... mb/asrock/h110m/devicetree: update VR config info Change-Id: Ia2b90d9ede782852c2127da972333bada378b217 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36378/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 8f64d02..425bc63 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -82,21 +82,21 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax* | 0 | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ - # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c + # VR Settings Configuration + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax* | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + # * - is set automatically in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = VR_CFG_AMP(20), \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2b90d9ede782852c2127da972333bada378b217 Gerrit-Change-Number: 36378 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: src/superio/nuvoton/nct5539d: use SuperIO acpigen
by Maxim Polyakov (Code Review) 04 Nov '19

04 Nov '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36380 ) Change subject: src/superio/nuvoton/nct5539d: use SuperIO acpigen ...................................................................... src/superio/nuvoton/nct5539d: use SuperIO acpigen Adds the code needed to use apcigen[1] for the nct5539d SuperIO chip. [1] https://review.coreboot.org/c/coreboot/+/33033 Not tested on real hardware Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/superio/nuvoton/nct5539d/Makefile.inc M src/superio/nuvoton/nct5539d/superio.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36380/1 diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc index 6e3fdf2..a6f3a02 100644 --- a/src/superio/nuvoton/nct5539d/Makefile.inc +++ b/src/superio/nuvoton/nct5539d/Makefile.inc @@ -14,3 +14,5 @@ ## ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += ../../common/generic.c diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index e38f845..4f2a4a5 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -40,6 +40,26 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *nct5539d_acpi_hid(const struct device *dev) +{ + if ((dev->path.type != DEVICE_PATH_PNP) || + (dev->path.pnp.port == 0) || + ((dev->path.pnp.device & 0xff) > NCT5539D_DS)) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case NCT5539D_SP1: + return ACPI_HID_COM; + case NCT5539D_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -47,6 +67,11 @@ .enable = pnp_alt_enable, .init = nct5539d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct5539d_acpi_hid, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802 Gerrit-Change-Number: 36380 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/asrock/h110m: use SuperIO acpigen
by Maxim Polyakov (Code Review) 04 Nov '19

04 Nov '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36381 ) Change subject: mb/asrock/h110m: use SuperIO acpigen ...................................................................... mb/asrock/h110m: use SuperIO acpigen Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/acpi/superio.asl M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 101 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36381/1 diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl index b671e3c..8b13789 100644 --- a/src/mainboard/asrock/h110m/acpi/superio.asl +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 425bc63..8854e76 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -322,101 +322,108 @@ device pci 1e.6 off end # SDCard device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on - # Global Control Registers - # Device IRQ Polarity - irq 0x13 = 0x00 - irq 0x14 = 0x00 - # Global Option - irq 0x24 = 0xfb - irq 0x27 = 0x10 - # Multi Function - irq 0x1a = 0xb0 - irq 0x1b = 0xe6 - irq 0x2a = 0x04 - irq 0x2c = 0x40 - irq 0x2d = 0x03 - # Parallel Port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on # GPIO6 - irq 0xf6 = 0xff - irq 0xf7 = 0xff - irq 0xf8 = 0xff - end - device pnp 2e.107 on # GPIO7 - irq 0xe0 = 0x7f - irq 0xe1 = 0x0d - end - device pnp 2e.207 on # GPIO8 - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xed = 0xff - end - device pnp 2e.8 off end # WDT - device pnp 2e.108 on end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 on end # GPIO1 - device pnp 2e.9 on end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xe4 = 0x7b - irq 0xe5 = 0x02 - irq 0xea = 0x04 - end - device pnp 2e.209 on # GPIO4 - irq 0xf0 = 0x7f - irq 0xf1 = 0x80 - end - device pnp 2e.309 on # GPIO5 - irq 0xf4 = 0xdf - irq 0xf5 = 0xd5 - end - device pnp 2e.a on - # Power RAM in S3 and let the PCH - # handle power failure actions - irq 0xe4 = 0x70 - # Set HWM reset source to LRESET# - irq 0xe7 = 0x01 - end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 on end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 on end # DS3OPT - device pnp 2e.616 on end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end -- To view, visit https://review.coreboot.org/c/coreboot/+/36381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Gerrit-Change-Number: 36381 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: src/superio/nuvoton/nct6791d: use SuperIO acpigen
by Maxim Polyakov (Code Review) 04 Nov '19

04 Nov '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36379 ) Change subject: src/superio/nuvoton/nct6791d: use SuperIO acpigen ...................................................................... src/superio/nuvoton/nct6791d: use SuperIO acpigen Adds the code needed to use apcigen[1] for the nct6791d SuperIO chip. [1] https://review.coreboot.org/c/coreboot/+/33033 Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/superio/nuvoton/nct6791d/Makefile.inc M src/superio/nuvoton/nct6791d/superio.c 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36379/1 diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc index db5c620..a1299a4 100644 --- a/src/superio/nuvoton/nct6791d/Makefile.inc +++ b/src/superio/nuvoton/nct6791d/Makefile.inc @@ -14,3 +14,5 @@ ## ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += ../../common/generic.c diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 23d5a6f..08f0bfa 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -22,10 +22,10 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> - +#include <superio/common/ssdt.h> +#include <arch/acpi.h> #include "nct6791d.h" - static void nct6791d_init(struct device *dev) { if (!dev->enabled) @@ -38,6 +38,27 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *nct6791d_acpi_hid(const struct device *dev) +{ + if ((dev->path.type != DEVICE_PATH_PNP) || + (dev->path.pnp.port == 0) || + ((dev->path.pnp.device & 0xff) > NCT6791D_DS)) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case NCT6791D_SP1: /* falltrough */ + case NCT6791D_SP2: + return ACPI_HID_COM; + case NCT6791D_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -45,6 +66,11 @@ .enable = pnp_alt_enable, .init = nct6791d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct6791d_acpi_hid, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af Gerrit-Change-Number: 36379 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: google/auron: hook up libgfxinit
by Matt DeVillier (Code Review) 04 Nov '19

04 Nov '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36107 ) Change subject: google/auron: hook up libgfxinit ...................................................................... google/auron: hook up libgfxinit Test: build/boot lulu variant with libgfxinit Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36107/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 13348a3..b4ef3a8 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -9,6 +9,7 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 6b1de05..ca42470 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -35,3 +35,5 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/auron/gma-mainboard.ads b/src/mainboard/google/auron/gma-mainboard.ads new file mode 100644 index 0000000..d110261 --- /dev/null +++ b/src/mainboard/google/auron/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/36107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Gerrit-Change-Number: 36107 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019