coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ec/google/chromeec: de-dup a _UID
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27604 Change subject: ec/google/chromeec: de-dup a _UID ...................................................................... ec/google/chromeec: de-dup a _UID There's two instances od _UID 1 for PNP0C02. This change moves the more system-specific instance of the two to a higher number. I believe these are the 4 I'm seeing. soc/intel/skylake/acpi/systemagent.asl Device (PDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) soc/intel/skylake/acpi/lpc.asl Device (LDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) ec/google/chromeec/acpi/superio.asl Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) ec/google/chromeec/acpi/superio.asl Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 3) Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27604/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 7cd6523..8faabee 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -39,7 +39,7 @@ #ifdef SIO_EC_MEMMAP_ENABLE Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) + Name (_UID, 4) Name (_ADR, 0) Method (_STA, 0, NotSerialized) { -- To view, visit https://review.coreboot.org/27604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4 Gerrit-Change-Number: 27604 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: use unique _uid
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27603 Change subject: soc/intel/skylake: use unique _uid ...................................................................... soc/intel/skylake: use unique _uid There's two cases of 1 being used. This changes the eighth instance to use 8. Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/skylake/acpi/irqlinks.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/27603/1 diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index 6a85a74..1dd50ba 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -389,7 +389,7 @@ Device (LNKH) { Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 1) + Name (_UID, 8) Name (_PRS, ResourceTemplate () { -- To view, visit https://review.coreboot.org/27603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481 Gerrit-Change-Number: 27603 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by build bot (Jenkins) (Code Review) 23 Jul '18

23 Jul '18

1 0

Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by Piotr Król (Code Review) 23 Jul '18

23 Jul '18

Piotr Król has uploaded a new patch set (#2). ( https://review.coreboot.org/27602 ) Change subject: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA ...................................................................... nb/amd/pi/00730F01: use MMIO and performance counters from AGESA This patch contain minimal set of changes to initial IVRS implementation to make it work reliably. Code in this patch was tested with Xen 4.8 and Debian 4.14.y - this software stack survived 100x reboots without any hang. Previously using IVRS provided by AGESA lead to 29/100 hangs. MMIO base shall not be hard coded since this value depends on platform design. Performance counters were selected experimentally, since lack of them cause 4.14.y panic: [ 1.064229] AMD-Vi: IOMMU performance counters supported [ 1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000 [ 1.073554] IP: iommu_go_to_state+0xf8a/0x1260 [ 1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0 [ 1.073554] Oops: 0000 [#1] SMP NOPTI [ 1.073554] Modules linked in: [ 1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13 [ 1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2 [ 1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000 [ 1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260 [ 1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282 [ 1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88 [ 1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246 [ 1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170 [ 1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000 [ 1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000 [ 1.073554] FS: 0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000 [ 1.073554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0 [ 1.073554] Call Trace: [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] amd_iommu_init+0x11/0x89 [ 1.073554] pci_iommu_init+0x16/0x3f [ 1.073554] ? e820__memblock_setup+0x60/0x60 [ 1.073554] do_one_initcall+0x51/0x190 [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] kernel_init_freeable+0x16b/0x1ec [ 1.073554] ? rest_init+0xb0/0xb0 [ 1.073554] kernel_init+0xa/0xf7 [ 1.073554] ret_from_fork+0x22/0x40 [ 1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2 [ 1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28 [ 1.073554] CR2: ffffaffc4065c000 [ 1.073554] ---[ end trace 44588f98aa7c7c0b ]--- [ 1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09 [ 1.255973] [ 1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9 Possible future improvements: - compare device entries with values returned by AGESA - enable EFRSup (this is enabled in AGESA) - try various IVHD flags (there is difference between initial implementation and AGESA) Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 42 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/27602/2 -- To view, visit https://review.coreboot.org/27602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Gerrit-Change-Number: 27602 Gerrit-PatchSet: 2 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by build bot (Jenkins) (Code Review) 23 Jul '18

23 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27602 ) Change subject: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA ...................................................................... Patch Set 1: (7 comments) https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 635: ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 637: ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 638: ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 648: ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 653: ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 655: ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ line over 80 characters https://review.coreboot.org/#/c/27602/1/src/northbridge/amd/pi/00730F01/nor… PS1, Line 656: ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ line over 80 characters -- To view, visit https://review.coreboot.org/27602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Gerrit-Change-Number: 27602 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Jul 2018 13:50:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 23 Jul '18

23 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 16: (102 comments) https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 441: static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 453: if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 460: if (dev->path.pci.devfn == 0x2) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 460: if (dev->path.pci.devfn == 0x2) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 462: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 463: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 464: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 465: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 466: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 467: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 468: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 469: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 470: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 473: } else if (dev->path.pci.devfn < (0x2 << 3)) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 473: } else if (dev->path.pci.devfn < (0x2 << 3)) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 475: } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 475: } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 476: /* FCH PCIe bridge device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 477: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 478: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 479: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 480: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 481: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 482: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 483: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 484: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 485: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 488: } else { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 489: if (dev->path.pci.devfn == (0x14 << 3)) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 489: if (dev->path.pci.devfn == (0x14 << 3)) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 490: /* SMBUS controller */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 491: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 492: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 493: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 494: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 495: p[3] = 0x97; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 496: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 497: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 498: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 499: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 502: } else { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 503: /* Other southbridge device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 504: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 505: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 506: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 507: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 508: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 509: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 510: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 511: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 512: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 518: if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 518: if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 519: /* Device behind bridge */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 520: if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 520: if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 521: /* Device is PCIe */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 522: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 523: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 524: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 525: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 526: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 527: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 528: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 529: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 530: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 533: } else { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 534: /* Device is legacy PCI or PCI-X */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 535: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 536: p[0] = 0x42; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 537: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 538: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 539: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 540: p[4] = 0x0; /* Reserved */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 541: p[5] = parent->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 542: p[6] = parent->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 543: p[7] = 0x0; /* Reserved */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 547: } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 547: } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 548: if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 548: if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 549: /* Bridge is PCIe */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 550: p = (uint8_t *) *current; line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 551: p[0] = 0x2; /* Entry type */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 552: p[1] = dev->path.pci.devfn; /* Device */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 553: p[2] = dev->bus->secondary; /* Bus */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 554: p[3] = 0x0; /* Data */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 555: p[4] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 556: p[5] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 557: p[6] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 558: p[7] = 0x0; /* Padding */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 570: for (sibling = link->children; sibling; sibling = sibling->sibling) line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 571: add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 576: unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 613: static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 619: printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n"); Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 624: ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 625: ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 630: ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 632: ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 633: ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ line over 80 characters https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/no… PS16, Line 655: add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 16 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 23 Jul 2018 13:50:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by Piotr Król (Code Review) 23 Jul '18

23 Jul '18

Piotr Król has uploaded this change for review. ( https://review.coreboot.org/27602 Change subject: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA ...................................................................... nb/amd/pi/00730F01: use MMIO and performance counters from AGESA This patch contain minimal set of changes to initial IVRS implementation to make it work reliably. Code in this patch was tested with Xen 4.8 and Debian 4.14.y - this software stack survived 100x reboots without any hang. Previously using IVRS provided by AGESA lead to 29/100 hangs. MMIO base shall not be hard coded since this value depends on platform design. Performance counters were selected experimentally, since lack of them cause 4.14.y panic: [ 1.064229] AMD-Vi: IOMMU performance counters supported [ 1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000 [ 1.073554] IP: iommu_go_to_state+0xf8a/0x1260 [ 1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0 [ 1.073554] Oops: 0000 [#1] SMP NOPTI [ 1.073554] Modules linked in: [ 1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13 [ 1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2 [ 1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000 [ 1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260 [ 1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282 [ 1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88 [ 1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246 [ 1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170 [ 1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000 [ 1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000 [ 1.073554] FS: 0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000 [ 1.073554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0 [ 1.073554] Call Trace: [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] amd_iommu_init+0x11/0x89 [ 1.073554] pci_iommu_init+0x16/0x3f [ 1.073554] ? e820__memblock_setup+0x60/0x60 [ 1.073554] do_one_initcall+0x51/0x190 [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] kernel_init_freeable+0x16b/0x1ec [ 1.073554] ? rest_init+0xb0/0xb0 [ 1.073554] kernel_init+0xa/0xf7 [ 1.073554] ret_from_fork+0x22/0x40 [ 1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2 [ 1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28 [ 1.073554] CR2: ffffaffc4065c000 [ 1.073554] ---[ end trace 44588f98aa7c7c0b ]--- [ 1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09 [ 1.255973] [ 1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9 Possible future improvements: - compare device entries with values returned by AGESA - enable EFRSup (this is enabled in AGESA) - try various IVHD flags (there is difference between initial implementation and AGESA) Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 36 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/27602/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 50d4a24..d3d7981 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -613,6 +613,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p; + acpi_ivrs_t *ivrs_agesa; device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -625,18 +626,41 @@ ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */ ivrs->iv_info |= (0x2 << 5); /* Guest virtual address width */ - ivrs->ivhd.type = 0x10; - ivrs->ivhd.flags = 0x0e; - ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ - ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); - ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ - ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ - ivrs->ivhd.iommu_base_low = 0xfeb00000; - ivrs->ivhd.iommu_base_high = 0x0; - ivrs->ivhd.pci_segment_group = 0x0; - ivrs->ivhd.iommu_info = 0x0; - ivrs->ivhd.iommu_info |= (0x13 << 8); - ivrs->ivhd.iommu_feature_info = 0x0; + + /* obtain IOMMU base address */ + ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs_agesa != NULL) { + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; + ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x13 << 8); + /* puse only performance counters related bits: + * PNCounters[16:13] and + * PNBanks[22:17], + * otherwise 0 */ + ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; + } else { + /* TODO: what we can do here? */ + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = 0xfeb00000; + ivrs->ivhd.iommu_base_high = 0x0; + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x13 << 8); + ivrs->ivhd.iommu_feature_info = 0x0; + } /* Describe HPET */ p = (uint8_t *)current; -- To view, visit https://review.coreboot.org/27602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Gerrit-Change-Number: 27602 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com>

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Change in coreboot[master]: include/device/pci: Fix union endianess
by Felix Held (Code Review) 23 Jul '18

23 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27600 ) Change subject: include/device/pci: Fix union endianess ...................................................................... Patch Set 1: Code-Review-1 (1 comment) https://review.coreboot.org/#/c/27600/1/src/include/device/pci.h File src/include/device/pci.h: https://review.coreboot.org/#/c/27600/1/src/include/device/pci.h@68 PS1, Line 68: }; : #endif the #endif needs to be before the }; -- To view, visit https://review.coreboot.org/27600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3dad4153008654d69db881e83e96421e9e3bde5a Gerrit-Change-Number: 27600 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Jul 2018 13:46:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: [test]i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc
by Elyes HAOUAS (Code Review) 23 Jul '18

23 Jul '18

1 0

Change in coreboot[master]: [test]i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc
by Elyes HAOUAS (Code Review) 23 Jul '18

23 Jul '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/27590 ) Change subject: [test]i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27590/2/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/27590/2/src/northbridge/intel/i945/raminit.… PS2, Line 965: > you change IDX for this option... in fact for dual channel, we need 2 idx : the 1st one is for channel0 : idx= 5 * dimm0 + dimm1 and the 2nd for channel1, called idx_channel1 = 5 * dimm2 + dimm3 -- To view, visit https://review.coreboot.org/27590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff1705788fdffeacd94fe5e50507733ff7c0f96b Gerrit-Change-Number: 27590 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Jul 2018 11:38:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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