coreboot-gerrit July 2018

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Change in coreboot[master]: lib/nhlt: add missing size field
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27612 to look at the new patch set (#2). Change subject: lib/nhlt: add missing size field ...................................................................... lib/nhlt: add missing size field coreboot doesn't provide a field that's required by some drivers. This doc is apparently offline: https://01.org/blogs/2016/intel-smart-sound-technology-audio-dsp but can currently be found at: https://docplayer.net/36738126-Intel-smart-sound-technology-audio- dsp-non-hd-audio-acpi-high-level-design.html Figure 2-1 (page 9) shows a SPECIFIC_CONFIG struct that should follow the endpoint descriptors. The struct is described in section 2.2 (page 10). It's sufficient to just provide the "CapabilitiesSize" field that's set to zero (meaning no capabilities follow). Change-Id: Ic0480c8123225a49c23b9e6af44ee20072c57a3f Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/lib/nhlt.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27612/2 -- To view, visit https://review.coreboot.org/27612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic0480c8123225a49c23b9e6af44ee20072c57a3f Gerrit-Change-Number: 27612 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: lib/nhlt: add missing size field
by build bot (Jenkins) (Code Review) 23 Jul '18

23 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27612 ) Change subject: lib/nhlt: add missing size field ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27612/1/src/lib/nhlt.c File src/lib/nhlt.c: https://review.coreboot.org/#/c/27612/1/src/lib/nhlt.c@390 PS1, Line 390: ser32(cur, 0); /* size of "Capabilities" buffer that follows (i.e., none) */ line over 80 characters -- To view, visit https://review.coreboot.org/27612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic0480c8123225a49c23b9e6af44ee20072c57a3f Gerrit-Change-Number: 27612 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Jul 2018 22:35:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: lib/nhlt: add missing size field
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27612 Change subject: lib/nhlt: add missing size field ...................................................................... lib/nhlt: add missing size field coreboot doesn't provide a field that's required by some drivers. This doc is apparently offline: https://01.org/blogs/2016/intel-smart-sound-technology-audio-dsp but can currently be found at: https://docplayer.net/36738126-Intel-smart-sound-technology-audio- dsp-non-hd-audio-acpi-high-level-design.html Figure 2-1 (page 9) shows a SPECIFIC_CONFIG struct that should follow the endpoint descriptors. The struct is described in section 2.2 (page 10). It's sufficient to just provide the "CapabilitiesSize" field that's set to zero (meaning no capabilities follow). Change-Id: Ic0480c8123225a49c23b9e6af44ee20072c57a3f Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/lib/nhlt.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27612/1 diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index f6135c7..876d97d 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -276,7 +276,7 @@ size_t nhlt_current_size(struct nhlt *nhlt) { - return calc_size(nhlt) + sizeof(acpi_header_t); + return calc_size(nhlt) + sizeof(acpi_header_t) + sizeof(uint32_t); } static void nhlt_free_resources(struct nhlt *nhlt) @@ -387,6 +387,7 @@ for (i = 0; i < nhlt->num_endpoints; i++) serialize_endpoint(&nhlt->endpoints[i], cur); + ser32(cur, 0); /* size of "Capabilities" buffer that follows (i.e., none) */ } uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) -- To view, visit https://review.coreboot.org/27612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic0480c8123225a49c23b9e6af44ee20072c57a3f Gerrit-Change-Number: 27612 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: permit Kconfig to set subsystem ID
by Arthur Heymans (Code Review) 23 Jul '18

23 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27609 ) Change subject: soc/intel/skylake: permit Kconfig to set subsystem ID ...................................................................... Patch Set 1: Code-Review-1 (1 comment) With this change there are two different methods to have FSP configure subsystemID (Kconfig and devicetree) and another one from devicetree with .set_subsystem pci ops? Why? https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 380: ifdef > The IS_ENABLED only works with boolean parameters, and this setting is the actual value of the vendo […] sorry overlooked that... -- To view, visit https://review.coreboot.org/27609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Gerrit-Change-Number: 27609 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Jul 2018 21:09:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: set turbo mode on all processors
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27611 Change subject: soc/intel: set turbo mode on all processors ...................................................................... soc/intel: set turbo mode on all processors The diagnostic test suite at biosbits.org complains that coreboot only sets up turbo mode on the first (i.e., 0th) processor. This change has the same speed set on all processors. The function that returns the turbo speed ratio is always returning the value for 1 core, which I'm not sure is another oversight or was done intentionally because turbo mode is only being set on the first processor. This change enables turbo mode on all processors (the test suite is now happy), though we're also now setting a slightly lower turbo mode ration (at least for the skylakes I'm using, where there's a higher value for 1-core but 2-4 cores all have the same [but slightly lower] value). I'm not sure what's the lesser evil, though practically speaking it may not matter much either way since the OS that's booted is likely to just set its own parameters (or make these moot, e.g., by writing 1 to MSR 0x770 to enable Speed Shift). Change-Id: Ib9b9989fdcb211f2a6a03cf60a7037cdbd028a7f Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/skylake/cpu.c 3 files changed, 54 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27611/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a049..b7ef990 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -75,24 +75,11 @@ return (platform_info.hi >> 1) & 3; } -/* - * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the - * factory configured values for of 1-core, 2-core, 3-core - * and 4-core turbo ratio limits for all processors. - * - * 7:0 - MAX_TURBO_1_CORE - * 15:8 - MAX_TURBO_2_CORES - * 23:16 - MAX_TURBO_3_CORES - * 31:24 - MAX_TURBO_4_CORES - * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. - */ void cpu_set_p_state_to_turbo_ratio(void) { - msr_t msr, perf_ctl; + msr_t perf_ctl; - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; + perf_ctl.lo = cpu_get_max_turbo_ratio() << 8; perf_ctl.hi = 0; wrmsr(MSR_IA32_PERF_CTL, perf_ctl); @@ -290,11 +277,51 @@ return (msr.lo & 0x7fff) * 1000 / power_unit; } +uint32_t cpu_get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +/* + * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the + * factory configured values for of 1-core, 2-core, 3-core + * and 4-core turbo ratio limits for all processors. + * + * 7:0 - MAX_TURBO_1_CORE + * 15:8 - MAX_TURBO_2_CORES + * 23:16 - MAX_TURBO_3_CORES + * 31:24 - MAX_TURBO_4_CORES + * + */ uint32_t cpu_get_max_turbo_ratio(void) { + uint32_t cores_per_package = cpu_get_cores_per_package(); msr_t msr; + + /* + * Some chip architectures have more than 4 cores and + * thus can have more than 32-bits set in the MSR. + * For now the cores are capped at 4 to avoid adding + * architecture-specific validation/checks. Using the + * 4th element is still better than the prior + * functionality that only used the 1-core setting. + */ + if (cores_per_package > 4) + cores_per_package = 4; + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - return msr.lo & 0xff; + return (msr.lo >> (8 * (cores_per_package - 1))) & 0xff; } void mca_configure(void *unused) diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 88f04b4..b17515c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -151,6 +151,11 @@ uint32_t cpu_get_power_max(void); /* + * cpu_get_cores_per_package returns number of cores per package + */ +uint32_t cpu_get_cores_per_package(void); + +/* * cpu_get_max_turbo_ratio returns the maximum turbo ratio limit for the * processor */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5535ec6..1c9f064 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -462,10 +462,15 @@ smm_relocate(); } +static void per_cpu_set_max_ratio(void *unused) +{ + cpu_set_max_ratio(); +} + static void post_mp_init(void) { /* Set Max Ratio */ - cpu_set_max_ratio(); + mp_run_on_all_cpus(per_cpu_set_max_ratio, NULL, 2 * USECS_PER_MSEC); /* * Now that all APs have been relocated as well as the BSP let SMIs -- To view, visit https://review.coreboot.org/27611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9b9989fdcb211f2a6a03cf60a7037cdbd028a7f Gerrit-Change-Number: 27611 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: permit Kconfig to set subsystem ID
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/27609 ) Change subject: soc/intel/skylake: permit Kconfig to set subsystem ID ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 380: ifdef > use "if (IS_ENABLED(CONFIG_SUBSYSTEM_VENDOR_ID))" The IS_ENABLED only works with boolean parameters, and this setting is the actual value of the vendor ID. -- To view, visit https://review.coreboot.org/27609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Gerrit-Change-Number: 27609 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 23 Jul 2018 20:25:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/skl: Add AML IccMax and show IGD SKU
by Gaggery Tsai (Code Review) 23 Jul '18

23 Jul '18

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/27610 ) Change subject: src/soc/intel/skl: Add AML IccMax and show IGD SKU ...................................................................... Patch Set 1: Code-Review-1 I will need to grab a AML board for a test prior inviting folks to review. -- To view, visit https://review.coreboot.org/27610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Gerrit-Change-Number: 27610 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Comment-Date: Mon, 23 Jul 2018 20:09:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/intel/skl: Add AML IccMax and show IGD SKU
by Gaggery Tsai (Code Review) 23 Jul '18

23 Jul '18

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/27610 Change subject: src/soc/intel/skl: Add AML IccMax and show IGD SKU ...................................................................... src/soc/intel/skl: Add AML IccMax and show IGD SKU This patch adds AML IccMax for VR configuration. From doc #594883, the IccMax for Core was changed to 28A, we need this patch to accommodate the changes. Besides, add up AML-Y GFX sku ID while reporting system information. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage I will need a AML device to test. WIP. Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/vr_config.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27610/1 diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 7d5bc3f..1072236 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -102,6 +102,7 @@ { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"}, { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" }, { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R, "Amberlake ULX GT2" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 57affe5..6a1f3e5 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -23,6 +23,7 @@ #define KBLY_ICCMAX_SA VR_CFG_AMP(4.1) #define KBLY_ICCMAX_CORE VR_CFG_AMP(24) +#define AMLY_ICCMAX_CORE VR_CFG_AMP(28) #define KBLY_ICCMAX_GTS_GTUS VR_CFG_AMP(24) #define KBLR_ICCMAX_SA_U42 VR_CFG_AMP(6) #define KBLU_ICCMAX_SA_U22 VR_CFG_AMP(4.5) @@ -36,11 +37,13 @@ KBL_R_SKU, KBL_U_BASE_SKU, KBL_U_PREMIUM_SKU, + AML_Y_SKU, }; /* * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax is the same among KBL-Y but KBL-U/R. + * Addendum for AML-Y #594883, IccMax for IA core is 28A. * +----------------+-------------+---------------+------+-----+ * | Domain/Setting | SA | IA | GTUS | GTS | * +----------------+-------------+---------------+------+-----+ @@ -50,6 +53,8 @@ * +----------------+-------------+---------------+------+-----+ * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | * +----------------+-------------+---------------+------+-----+ + * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ */ static const struct { @@ -92,6 +97,15 @@ KBLUR_ICCMAX_GTS_GTUS } }, + [AML_Y_SKU] = { + .sku = AML_Y_SKU, + .icc_max = { + KBLY_ICCMAX_SA, + AMLY_ICCMAX_CORE, + KBLY_ICCMAX_GTS_GTUS, + KBLY_ICCMAX_GTS_GTUS + } + }, }; /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ @@ -176,9 +190,13 @@ id = get_dev_id(SA_DEV_ROOT); if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) sku = KBL_R_SKU; - else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) - sku = KBL_Y_SKU; - else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) { + else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { + id = get_dev_id(SA_DEV_IGD); + if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R) + sku = AML_Y_SKU; + else + sku = KBL_Y_SKU; + } else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) { id = get_dev_id(PCH_DEV_LPC); if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) sku = KBL_U_BASE_SKU; -- To view, visit https://review.coreboot.org/27610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Gerrit-Change-Number: 27610 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: permit Kconfig to set subsystem ID
by Arthur Heymans (Code Review) 23 Jul '18

23 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27609 ) Change subject: soc/intel/skylake: permit Kconfig to set subsystem ID ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/27609/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 380: ifdef use "if (IS_ENABLED(CONFIG_SUBSYSTEM_VENDOR_ID))" -- To view, visit https://review.coreboot.org/27609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Gerrit-Change-Number: 27609 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 23 Jul 2018 19:57:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: permit Kconfig to set subsystem ID
by Matt Delco (Code Review) 23 Jul '18

23 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27609 Change subject: soc/intel/skylake: permit Kconfig to set subsystem ID ...................................................................... soc/intel/skylake: permit Kconfig to set subsystem ID This change permits the subsystem ID to be specified via Kconfig for the devices on the SoC. I'm also changing the behavior of how defaults are handled. Some devices are getting zero'ed subsystem IDs because the unset (and thus zero'ed) config options are overwriting the fsp defaults. With this change the fsp defaults will only be overwritten by non-zero config values. Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 31 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/27609/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a6e03ca..06e90fb 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -44,6 +44,11 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Subsystem Vendor ID of the SA devices*/ + uint16_t DefaultSvid; + /* Subsystem ID of the SA devices*/ + uint16_t DefaultSid; + /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f51559f..cccaba5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -374,8 +374,32 @@ */ params->SpiFlashCfgLockDown = 0; } - params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; - params->PchSubSystemId = config->PchConfigSubSystemId; + /* only replacing subsys ID defaults when 'config' non-zero */ + if (config->DefaultSvid) + params->DefaultSvid = config->DefaultSvid; +#ifdef CONFIG_SUBSYSTEM_VENDOR_ID + else + params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; +#endif + if (config->DefaultSid) + params->DefaultSid = config->DefaultSid; +#ifdef CONFIG_SUBSYSTEM_DEVICE_ID + else + params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; +#endif + if (config->PchConfigSubSystemVendorId) + params->PchSubSystemVendorId = + config->PchConfigSubSystemVendorId; +#ifdef CONFIG_SUBSYSTEM_VENDOR_ID + else + params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; +#endif + if (config->PchConfigSubSystemId) + params->PchSubSystemId = config->PchConfigSubSystemId; +#ifdef CONFIG_SUBSYSTEM_VENDOR_ID + else + params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; +#endif params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; -- To view, visit https://review.coreboot.org/27609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Gerrit-Change-Number: 27609 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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coreboot-gerrit July 2018