coreboot-gerrit June 2018

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Change in coreboot[master]: payloads/libpayload/drivers/i8042: Add macros for i8042 commands
by Furquan Shaikh (Code Review) 29 Jun '18

29 Jun '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27289 Change subject: payloads/libpayload/drivers/i8042: Add macros for i8042 commands ...................................................................... payloads/libpayload/drivers/i8042: Add macros for i8042 commands This change adds macros for commands (written to 0x64) and keyboard commands (written to 0x60) for 8042 controller. BUG=b:110024487 Change-Id: I74b2388d048e35b5bdf5bd862d0975e88f1bd6af Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M payloads/libpayload/drivers/i8042/i8042.c A payloads/libpayload/drivers/i8042/i8042.h M payloads/libpayload/drivers/i8042/keyboard.c 3 files changed, 87 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27289/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index b679448..69740d9 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -31,6 +31,8 @@ #include <libpayload.h> #include <stddef.h> +#include "i8042.h" + /* Overflowing FIFO implementation */ struct fifo { @@ -204,13 +206,13 @@ kbc_init = 1; /* Disable first device */ - if (i8042_cmd(0xad) != 0) { + if (i8042_cmd(I8042_CMD_DIS_KB) != 0) { kbc_init = 0; return 0; } /* Disable second device */ - if (i8042_cmd(0xa7) != 0) { + if (i8042_cmd(I8042_CMD_DIS_AUX) != 0) { kbc_init = 0; return 0; } @@ -220,17 +222,18 @@ read_data(); /* Self test. */ - if (i8042_cmd_with_response(0xaa) != 0x55) { + if (i8042_cmd_with_response(I8042_CMD_SELF_TEST) + != I8042_SELF_TEST_RSP) { kbc_init = 0; return 0; } /* Test secondary port */ - if (i8042_cmd_with_response(0xa9) == 0) + if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0) aux_fifo = fifo_init(4 * 32); /* Test first PS/2 port */ - if (i8042_cmd_with_response(0xab) == 0) + if (i8042_cmd_with_response(I8042_CMD_KB_TEST) == 0) ps2_fifo = fifo_init(2 * 16); kbc_init = 0; diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h new file mode 100644 index 0000000..788a134 --- /dev/null +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -0,0 +1,69 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2018 Google LLC. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __DRIVERS_I8042_I8042_H__ +#define __DRIVERS_I8042_I8042_H__ + +/* Port 0x64 commands */ +#define I8042_CMD_RD_CMD_BYTE 0x20 +#define I8042_CMD_WR_CMD_BYTE 0x60 +#define I8042_CMD_DIS_AUX 0xa7 +#define I8042_CMD_EN_AUX 0xa8 +#define I8042_CMD_AUX_TEST 0xa9 +#define I8042_CMD_SELF_TEST 0xaa +#define I8042_SELF_TEST_RSP 0x55 +#define I8042_CMD_KB_TEST 0xab +#define I8042_CMD_DIAG_DUMP 0xac +#define I8042_CMD_DIS_KB 0xad +#define I8042_CMD_EN_KB 0xae +#define I8042_CMD_RD_INPUT_PORT 0xc0 +#define I8042_CMD_RD_OUTPUT_PORT 0xd0 +#define I8042_CMD_WR_OUTPUT_PORT 0xd1 +#define I8042_CMD_RD_TEST_INPUTS 0xe0 + +/* Port 0x60 keyboard commands */ +#define I8042_KBCMD_SET_MODE_IND 0xed +#define I8042_MODE_CAPS_LOCK_ON (1 << 2) +#define I8042_MODE_CAPS_LOCK_OFF (0 << 2) +#define I8042_MODE_NUM_LOCK_ON (1 << 1) +#define I8042_MODE_NUM_LOCK_OFF (0 << 1) +#define I8042_MODE_SCROLL_LOCK_ON (1 << 0) +#define I8042_MODE_SCROLL_LOCK_OFF (0 << 0) +#define I8042_KBCMD_SET_SCANCODE 0xf0 +#define I8042_SCANCODE_SET_1 (1) +#define I8042_SCANCODE_SET_2 (2) +#define I8042_SCANCODE_SET_3 (3) +#define I8042_KBCMD_SET_TYPEMATIC 0xf3 +#define I8042_KBCMD_EN 0xf4 +#define I8042_KBCMD_DEFAULT_DIS 0xf5 +#define I8042_KBCMD_SET_DEFAULT 0xf6 +#define I8042_KBCMD_RESEND 0xfe +#define I8042_KBCMD_RESET 0xff + +#endif /* __DRIVERS_I8042_I8042_H__ */ diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index af44e01..d5606a3 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -32,7 +32,8 @@ #include <libpayload-config.h> #include <libpayload.h> -#define I8042_CMD_DIS_KB 0xad +#include "i8042.h" + #define POWER_BUTTON 0x90 struct layout_maps { @@ -203,12 +204,12 @@ case 0x3a: if (modifier & KB_MOD_CAPSLOCK) { modifier &= ~KB_MOD_CAPSLOCK; - if (keyboard_cmd(0xed)) - keyboard_cmd(0 << 2); + if (keyboard_cmd(I8042_KBCMD_SET_MODE_IND)) + keyboard_cmd(I8042_MODE_CAPS_LOCK_OFF); } else { modifier |= KB_MOD_CAPSLOCK; - if (keyboard_cmd(0xed)) - keyboard_cmd(1 << 2); + if (keyboard_cmd(I8042_KBCMD_SET_MODE_IND)) + keyboard_cmd(I8042_MODE_CAPS_LOCK_ON); } break; } @@ -304,19 +305,19 @@ keyboard_getchar(); /* Enable first PS/2 port */ - i8042_cmd(0xae); + i8042_cmd(I8042_CMD_EN_KB); /* Set scancode set 1 */ - ret = keyboard_cmd(0xf0); + ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); if (!ret) return; - ret = keyboard_cmd(0x01); + ret = keyboard_cmd(I8042_SCANCODE_SET_1); if (!ret) return; /* Enable scanning */ - ret = keyboard_cmd(0xf4); + ret = keyboard_cmd(I8042_KBCMD_EN); if (!ret) return; -- To view, visit https://review.coreboot.org/27289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74b2388d048e35b5bdf5bd862d0975e88f1bd6af Gerrit-Change-Number: 27289 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: cbfstool: Update FIT entry type for MCU
by Furquan Shaikh (Code Review) 29 Jun '18

29 Jun '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27288 ) Change subject: cbfstool: Update FIT entry type for MCU ...................................................................... Patch Set 1: Already fixed here: https://review.coreboot.org/c/coreboot/+/27266 -- To view, visit https://review.coreboot.org/27288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7edd25dd1953cb827ba919554c675759e47491c4 Gerrit-Change-Number: 27288 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Fri, 29 Jun 2018 18:13:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cbfstool: Update FIT entry type for MCU
by Naresh Solanki (Code Review) 29 Jun '18

29 Jun '18

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/27288 Change subject: cbfstool: Update FIT entry type for MCU ...................................................................... cbfstool: Update FIT entry type for MCU FIT entry for MCU should have type set to FIT_TYPE_MICROCODE. Change-Id: I7edd25dd1953cb827ba919554c675759e47491c4 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- M util/cbfstool/fit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27288/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 31ab3de..1ed16ce 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -183,7 +183,7 @@ */ entry->size_reserved = 0x0000; /* Checksum valid should be cleared for MCU */ - entry->type_checksum_valid = 0; + entry->type_checksum_valid = FIT_TYPE_MICROCODE; entry->version = FIT_MICROCODE_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); -- To view, visit https://review.coreboot.org/27288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7edd25dd1953cb827ba919554c675759e47491c4 Gerrit-Change-Number: 27288 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com>

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Change in coreboot[master]: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27275 ) Change subject: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75586/ : SUCCESS -- To view, visit https://review.coreboot.org/27275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Gerrit-Change-Number: 27275 Gerrit-PatchSet: 3 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 17:58:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Generate ACPI RMRR table
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27270 ) Change subject: soc/intel/skylake: Generate ACPI RMRR table ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29643/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75585/ : SUCCESS -- To view, visit https://review.coreboot.org/27270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Gerrit-Change-Number: 27270 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 16:34:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27269 ) Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75584/ : SUCCESS -- To view, visit https://review.coreboot.org/27269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Gerrit-Change-Number: 27269 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Fri, 29 Jun 2018 16:29:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by Martin Roth (Code Review) 29 Jun '18

29 Jun '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27268 ) Change subject: stoneyridge: Enable legacy IO ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 378: static void sb_enable_legacy_io(void) > I did, but wanted to call out the fact that they are different io ranged. […] I think it's fine, I was just curious why you split them. -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 15:54:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by Raul Rangel (Code Review) 29 Jun '18

29 Jun '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/27268 ) Change subject: stoneyridge: Enable legacy IO ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 378: static void sb_enable_legacy_io(void) > I'm fine with this, but did you consider doing both at the same time since it's the same register? […] I did, but wanted to call out the fact that they are different io ranged. I can rename the method to sb_enable_io() and combine them both if you want. -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 15:41:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by Martin Roth (Code Review) 29 Jun '18

29 Jun '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27268 ) Change subject: stoneyridge: Enable legacy IO ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27268/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 378: static void sb_enable_legacy_io(void) I'm fine with this, but did you consider doing both at the same time since it's the same register? sb_pm_decode_setup(); -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 15:36:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by Martin Roth (Code Review) 29 Jun '18

29 Jun '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27267 ) Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 15:33:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018