build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27169 )
Change subject: drivers/fsp1_1: fix VBT Loading by using GMA common function
......................................................................
Patch Set 4: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/29215/ : SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/75138/ : SUCCESS
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/27168 )
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
Patch Set 8: Code-Review+2
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Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
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Gerrit-Comment-Date: Wed, 20 Jun 2018 13:13:09 +0000
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Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27168
to look at the new patch set (#8).
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan(a)gmail.com>
---
M util/inteltool/gpio.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/powermgt.c
M util/inteltool/rootcmplx.c
M util/inteltool/spi.c
6 files changed, 112 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27168/8
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/27168 )
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/#/c/27168/7/util/inteltool/gpio.c
File util/inteltool/gpio.c:
https://review.coreboot.org/#/c/27168/7/util/inteltool/gpio.c@873
PS7, Line 873: /* Shares Lynx Point register locations but has less of them */
Nit, all 8 series is Lynx Point. The integrated one is referred to as
Lynx Point-LP.
https://review.coreboot.org/#/c/27168/7/util/inteltool/inteltool.h
File util/inteltool/inteltool.h:
https://review.coreboot.org/#/c/27168/7/util/inteltool/inteltool.h@187
PS7, Line 187: #define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41
: #define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42
These two use spaces now?
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Gerrit-Comment-Date: Wed, 20 Jun 2018 12:52:15 +0000
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Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27168
to look at the new patch set (#7).
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan(a)gmail.com>
---
M util/inteltool/gpio.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/powermgt.c
M util/inteltool/rootcmplx.c
M util/inteltool/spi.c
6 files changed, 112 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27168/7
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Gerrit-Change-Number: 27168
Gerrit-PatchSet: 7
Gerrit-Owner: Quan Tran <qeed.quan(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27168
to look at the new patch set (#6).
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan(a)gmail.com>
---
M util/inteltool/gpio.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/powermgt.c
M util/inteltool/rootcmplx.c
M util/inteltool/spi.c
6 files changed, 112 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27168/6
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Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Gerrit-Change-Number: 27168
Gerrit-PatchSet: 6
Gerrit-Owner: Quan Tran <qeed.quan(a)gmail.com>
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Nico Huber has posted comments on this change. ( https://review.coreboot.org/27168 )
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/#/c/27168/5/util/inteltool/gpio.c
File util/inteltool/gpio.c:
https://review.coreboot.org/#/c/27168/5/util/inteltool/gpio.c@873
PS5, Line 873: size = 29;
Please leave a comment that this is intentionally reusing the 29
first registers of the LP variant. Otherwise ppl might get confused
and try to "fix" it...
https://review.coreboot.org/#/c/27168/5/util/inteltool/inteltool.h
File util/inteltool/inteltool.h:
https://review.coreboot.org/#/c/27168/5/util/inteltool/inteltool.h@201
PS5, Line 201: #define PCI_DEVICE_ID_INTEL_H81 0x8c5c
again, please align
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Gerrit-Comment-Date: Wed, 20 Jun 2018 12:31:38 +0000
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