coreboot-gerrit June 2018

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Change in coreboot[master]: soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27250 ) Change subject: soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29458/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75407/ : SUCCESS -- To view, visit https://review.coreboot.org/27250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be Gerrit-Change-Number: 27250 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 03:56:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Remove dead files
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27252 ) Change subject: soc/intel/apollolake: Remove dead files ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29460/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75409/ : SUCCESS -- To view, visit https://review.coreboot.org/27252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Gerrit-Change-Number: 27252 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 03:52:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common: Disable GPEs just before enabling SMIs
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27251 ) Change subject: soc/intel/common: Disable GPEs just before enabling SMIs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29459/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75408/ : SUCCESS -- To view, visit https://review.coreboot.org/27251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed Gerrit-Change-Number: 27251 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 03:48:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Remove call to pmc_fixup_power_state
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27249 ) Change subject: soc/intel/apollolake: Remove call to pmc_fixup_power_state ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29457/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75406/ : SUCCESS -- To view, visit https://review.coreboot.org/27249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Gerrit-Change-Number: 27249 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 03:43:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Remove dead files
by Furquan Shaikh (Code Review) 27 Jun '18

27 Jun '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27252 Change subject: soc/intel/apollolake: Remove dead files ...................................................................... soc/intel/apollolake: Remove dead files Change a86d1b8 (soc/intel/common: Add SMM common code for Intel Platforms) moved APL to use common SMM code. However, smi.c and smm.h files under soc/intel/apollolake/ were not removed. This change removes the dead files since they are not used anymore. BUG=b:110836465 Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/soc/intel/apollolake/include/soc/smm.h D src/soc/intel/apollolake/smi.c 2 files changed, 0 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/27252/1 diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h deleted file mode 100644 index eda0bc44..0000000 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include <stdint.h> -#include <soc/gpio.h> -#include <fsp/memmap.h> - -/* - * The initialization of the southbridge is split into 2 compoments. One is - * for clearing the state in the SMM registers. The other is for enabling - * SMIs. - */ -void southbridge_smm_clear_state(void); -void southbridge_smm_enable_smi(void); - -#endif diff --git a/src/soc/intel/apollolake/smi.c b/src/soc/intel/apollolake/smi.c deleted file mode 100644 index eacc2cb..0000000 --- a/src/soc/intel/apollolake/smi.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <intelblocks/pmclib.h> -#include <string.h> -#include <soc/pm.h> -#include <soc/smm.h> - -void southbridge_smm_clear_state(void) -{ - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - - if (pmc_get_smi_en() & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "Done\n"); - - /* Dump and clear status registers */ - pmc_clear_smi_status(); - pmc_clear_pm1_status(); - pmc_clear_tco_status(); - pmc_clear_all_gpe_status(); -} - -void southbridge_smm_enable_smi(void) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - pmc_enable_pm1(PWRBTN_EN | GBL_EN); - pmc_disable_std_gpe(PME_B0_EN); - - /* Enable SMI generation */ - pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} -- To view, visit https://review.coreboot.org/27252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Gerrit-Change-Number: 27252 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common: Disable GPEs just before enabling SMIs
by Furquan Shaikh (Code Review) 27 Jun '18

27 Jun '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27251 Change subject: soc/intel/common: Disable GPEs just before enabling SMIs ...................................................................... soc/intel/common: Disable GPEs just before enabling SMIs Call to pmc_disable_all_gpe is required before enabling SMIs to ensure that we do not end up in a recursive SMI handler loop as mentioned in change 74145f7 (intel/common/pmc: Disable all GPEs during pmc_init). Thus, this call was added at the end of pmc_fill_power_state as we want to ensure that all the GPE registers are backed up before being cleared for identifying the wake source in ramstage. This resulted in a side-effect on APL where pmc_fixup_power_state was called much later in the boot process. Even though we have got rid of pmc_fixup_power_state, this change moves the call to pmc_disable_all_gpe to happen just before enabling SMIs. This helps to keep the disabling of GPEs logically before the enabling of SMIs and any clean ups that happen in pmc or soc-specific code should not affect the state of GPEs. BUG=b:110836465 TEST=Verified that wake sources are correctly identified on KBL and APL. Also, no SMI handler issues observed when resuming. Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smm/smm.c 2 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27251/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0795990..339e674 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -416,18 +416,6 @@ ps->prev_sleep_state = pmc_prev_sleep_state(ps); printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - /* - * GPEs need to be disabled before enabling SMI. Otherwise, it could - * lead to SMIs being triggered in coreboot preventing the progress of - * normal boot-up. However, GPEs should not be disabled as part of - * pmc_gpe_init which happens in bootblock. Otherwise, - * pmc_fill_power_state would read GPE0_EN registers as all 0s thus - * losing information about the wake source. Hence, - * pmc_disable_all_gpe() is placed here after GPE0_EN registers are - * saved in chipset_power_state. - */ - pmc_disable_all_gpe(); - return ps->prev_sleep_state; } diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index e8c5245..6059995 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -46,6 +46,15 @@ pmc_disable_std_gpe(PME_B0_EN); /* + * GPEs need to be disabled before enabling SMI. Otherwise, it could + * lead to SMIs being triggered in coreboot preventing the progress of + * normal boot-up. This is done as late as possible so that + * pmc_fill_power_state can read the correct state of GPE0_EN* registers + * and not lose information about the wake source. + */ + pmc_disable_all_gpe(); + + /* * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) -- To view, visit https://review.coreboot.org/27251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed Gerrit-Change-Number: 27251 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state
by Furquan Shaikh (Code Review) 27 Jun '18

27 Jun '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27250 Change subject: soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state ...................................................................... soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state Now that APL does not need pmc_fixup_power_state, this function can be removed from the PMC common code as well. BUG=b:110836465 Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27250/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index d631f01..ddf384b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -150,9 +150,6 @@ */ void pmc_global_reset_lock(void); -/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */ -void pmc_fixup_power_state(void); - /* Returns the power state structure */ struct chipset_power_state *pmc_get_power_state(void); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 38d4196..0795990 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -385,30 +385,6 @@ return soc_prev_sleep_state(ps, prev_sleep_state); } -/* - * This function re-writes the gpe0 register values in power state - * cbmem variable. After system wakes from sleep state internal PMC logic - * writes default values in GPE_CFG register which gives a wrong offset to - * calculate the wake reason. So we need to set it again to the routing - * table as per the devicetree. - */ -void pmc_fixup_power_state(void) -{ - int i; - struct chipset_power_state *ps; - - ps = pmc_get_power_state(); - if (ps == NULL) - return; - - for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); - printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", - i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); - } -} - void pmc_fill_pm_reg_info(struct chipset_power_state *ps) { int i; -- To view, visit https://review.coreboot.org/27250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be Gerrit-Change-Number: 27250 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake: Remove call to pmc_fixup_power_state
by Furquan Shaikh (Code Review) 27 Jun '18

27 Jun '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27249 Change subject: soc/intel/apollolake: Remove call to pmc_fixup_power_state ...................................................................... soc/intel/apollolake: Remove call to pmc_fixup_power_state On APL, call to pmc_fixup_power_state was added because GPE0_EN registers did not have the right bits set on resume from S3 -- this was a result of GPE_CFG registers getting reset to their default state on resume. GPE_CFG registers are programmed as part of pmc_gpe_init which was previously done only in ramstage. However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in bootblock), call to pmc_gpe_init was added to bootblock which means that GPE_CFG registers will have the right state by the time control reaches romstage where pmc_fill_power_state is called. Thus, call to pmc_fixup_power_state is totally redundant and in fact leads to side-effects because of the call to pmc_disable_all_gpe at the end of pmc_fill_power_state. BUG=b:110836465 TEST=Verified on yorp that wake source is correctly identified on resume from S3. Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/pmc.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27249/1 diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 58cb71a..15ef243 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -97,7 +97,6 @@ /* Set up GPE configuration */ pmc_gpe_init(); - pmc_fixup_power_state(); pmc_set_acpi_mode(); if (cfg != NULL) -- To view, visit https://review.coreboot.org/27249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Gerrit-Change-Number: 27249 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: nocturne: Fix uid and desc for sx9310
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27248 ) Change subject: nocturne: Fix uid and desc for sx9310 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29456/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75405/ : SUCCESS -- To view, visit https://review.coreboot.org/27248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Gerrit-Change-Number: 27248 Gerrit-PatchSet: 1 Gerrit-Owner: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 23:55:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Fix uid and desc for sx9310
by Enrico Granata (Code Review) 26 Jun '18

26 Jun '18

Enrico Granata has uploaded this change for review. ( https://review.coreboot.org/27248 Change subject: nocturne: Fix uid and desc for sx9310 ...................................................................... nocturne: Fix uid and desc for sx9310 This commit changes the uid and desc fields for the sx9310 entries in the devicetree to be unique, and correctly identify the position of the respective sensors. Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Signed-off-by: Enrico Granata <egranata(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27248/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0797f62..91c0b44 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -301,10 +301,10 @@ end # I2C #0 - Touchscreen device pci 15.1 on chip drivers/i2c/sx9310 - register "desc" = ""Left SAR Proximity Sensor"" + register "desc" = ""Right SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" - register "uid" = "1" + register "uid" = "0" register "reg_prox_ctrl0" = "0x1A" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" -- To view, visit https://review.coreboot.org/27248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Gerrit-Change-Number: 27248 Gerrit-PatchSet: 1 Gerrit-Owner: Enrico Granata <egranata(a)chromium.org>

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coreboot-gerrit June 2018