coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: clear MCA before booting to OS
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26392 ) Change subject: soc/intel/skylake: clear MCA before booting to OS ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29440/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75390/ : SUCCESS -- To view, visit https://review.coreboot.org/26392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305 Gerrit-Change-Number: 26392 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 26 Jun 2018 19:43:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27244 ) Change subject: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29439/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75389/ : SUCCESS -- To view, visit https://review.coreboot.org/27244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Gerrit-Change-Number: 27244 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 19:38:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: add a space in printing ME FPF status
by Pratikkumar V Prajapati (Code Review) 26 Jun '18

26 Jun '18

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/27246 Change subject: soc/intel/skylake: add a space in printing ME FPF status ...................................................................... soc/intel/skylake: add a space in printing ME FPF status This is cosmetic change Before: ME: Power Management Event : Clean global reset ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused After: ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/skylake/me.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27246/1 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index a23172e..36f8339 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -424,7 +424,7 @@ } } - printk(BIOS_DEBUG, "ME: FPF status : "); + printk(BIOS_DEBUG, "ME: FPF status : "); switch (hfs6.fields.fpf_nvars) { case ME_HFS6_FPF_NOT_COMMITTED: printk(BIOS_DEBUG, "unfused\n"); -- To view, visit https://review.coreboot.org/27246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Gerrit-Change-Number: 27246 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: nb/intel/pineview: Don't use PCI operations on the pci_domain device
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27243 ) Change subject: nb/intel/pineview: Don't use PCI operations on the pci_domain device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29438/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75388/ : SUCCESS -- To view, visit https://review.coreboot.org/27243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Gerrit-Change-Number: 27243 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 19:33:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Don't use PCI operations on the pci_domain device
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27245 ) Change subject: nb/intel/x4x: Don't use PCI operations on the pci_domain device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29437/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75387/ : SUCCESS -- To view, visit https://review.coreboot.org/27245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb Gerrit-Change-Number: 27245 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 19:29:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/gm45: Don't use PCI operations on the pci_domain device
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27242 ) Change subject: nb/intel/gm45: Don't use PCI operations on the pci_domain device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29436/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75386/ : SUCCESS -- To view, visit https://review.coreboot.org/27242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a Gerrit-Change-Number: 27242 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 19:24:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Don't use PCI operations on the pci_domain device
by Arthur Heymans (Code Review) 26 Jun '18

26 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27245 Change subject: nb/intel/x4x: Don't use PCI operations on the pci_domain device ...................................................................... nb/intel/x4x: Don't use PCI operations on the pci_domain device The pci_domain just happens to have bus, device and function set to 0, which is why to code works. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/northbridge.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27245/1 diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 3e50229..08e5e1c 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -44,16 +44,18 @@ pci_domain_read_resources(dev); + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(dev, D0F0_TOUUD); + touud = pci_read_config16(mch, D0F0_TOUUD); touud <<= 20; /* Top of Lower Usable DRAM */ - tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; + tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff; + tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; tom <<= 26; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", @@ -63,7 +65,7 @@ /* Graphics memory comes next */ - const u16 ggc = pci_read_config16(dev, D0F0_GGC); + const u16 ggc = pci_read_config16(mch, D0F0_GGC); printk(BIOS_DEBUG, "IGD decoded, subtracting "); /* Graphics memory */ @@ -79,7 +81,7 @@ uma_sizek += gsm_sizek; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); - reg8 = pci_read_config8(dev, D0F0_ESMRAMC); + reg8 = pci_read_config8(mch, D0F0_ESMRAMC); reg8 >>= 1; reg8 &= 3; switch (reg8) { -- To view, visit https://review.coreboot.org/27245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb Gerrit-Change-Number: 27245 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device
by Arthur Heymans (Code Review) 26 Jun '18

26 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27244 Change subject: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device ...................................................................... nb/intel/sandybridge: Don't use PCI operations on the pci_domain device The pci_domain just happens to have bus, device and function set to 0, which is why to code works. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27244/1 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 8c2aaf3..56d3c49 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -152,26 +152,28 @@ * 14fe00000 5368MB TOUUD */ + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(dev, TOUUD+4); + touud = pci_read_config32(mch, TOUUD+4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= pci_read_config32(mch, TOUUD); /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD); + tolud = pci_read_config32(mch, TOLUD); /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(dev, 0xa4); + tom = pci_read_config32(mch, 0xa4); tom <<= 32; - tom |= pci_read_config32(dev, 0xa0); + tom |= pci_read_config32(mch, 0xa0); printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); /* ME UMA needs excluding if total memory <4GB */ - me_base = pci_read_config32(dev, 0x74); + me_base = pci_read_config32(mch, 0x74); me_base <<= 32; - me_base |= pci_read_config32(dev, 0x70); + me_base |= pci_read_config32(mch, 0x70); printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); @@ -190,7 +192,7 @@ } /* Graphics memory comes next */ - ggc = pci_read_config16(dev, GGC); + ggc = pci_read_config16(mch, GGC); if (!(ggc & 2)) { printk(BIOS_DEBUG, "IGD decoded, subtracting "); @@ -210,7 +212,7 @@ } /* Calculate TSEG size from its base which must be below GTT */ - tseg_base = pci_read_config32(dev, 0xb8); + tseg_base = pci_read_config32(mch, 0xb8); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; -- To view, visit https://review.coreboot.org/27244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Gerrit-Change-Number: 27244 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/pineview: Don't use PCI operations on the pci_domain device
by Arthur Heymans (Code Review) 26 Jun '18

26 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27243 Change subject: nb/intel/pineview: Don't use PCI operations on the pci_domain device ...................................................................... nb/intel/pineview: Don't use PCI operations on the pci_domain device The pci_domain just happens to have bus, device and function set to 0, which is why to code works. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/northbridge.c 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27243/1 diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 93c7558..6b8075e 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -59,20 +59,22 @@ u16 index; const u32 top32memk = 4 * (GiB / KiB); + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + index = 3; pci_domain_read_resources(dev); /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(dev, TOUUD); + touud = pci_read_config16(mch, TOUUD); touud <<= 20; /* Top of Lower Usable DRAM */ - tolud = pci_read_config16(dev, TOLUD) & 0xfff0; + tolud = pci_read_config16(mch, TOLUD) & 0xfff0; tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(dev, TOM) & 0x1ff; + tom = pci_read_config16(mch, TOM) & 0x1ff; tom <<= 27; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", @@ -81,7 +83,7 @@ tomk = tolud >> 10; /* Graphics memory */ - const u16 ggc = pci_read_config16(dev, GGC); + const u16 ggc = pci_read_config16(mch, GGC); const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); tomk -= gms_sizek; @@ -91,9 +93,9 @@ printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); tomk -= gsm_sizek; - const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10; - const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10; - const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10; + const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10; + const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10; + const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10; /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; -- To view, visit https://review.coreboot.org/27243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Gerrit-Change-Number: 27243 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/gm45: Don't use PCI operations on the pci_domain device
by Arthur Heymans (Code Review) 26 Jun '18

26 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27242 Change subject: nb/intel/gm45: Don't use PCI operations on the pci_domain device ...................................................................... nb/intel/gm45: Don't use PCI operations on the pci_domain device The pci_domain just happens to have bus, device and function set to 0, which is why to code works. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c 1 file changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27242/1 diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 4c42513..a3f517b 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -95,16 +95,18 @@ pci_domain_read_resources(dev); + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(dev, D0F0_TOUUD); + touud = pci_read_config16(mch, D0F0_TOUUD); touud <<= 20; /* Top of Lower Usable DRAM */ - tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; + tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(dev, D0F0_TOM) & 0x1ff; + tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; tom <<= 27; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", @@ -113,7 +115,7 @@ tomk = tolud >> 10; /* Graphics memory comes next */ - const u16 ggc = pci_read_config16(dev, D0F0_GGC); + const u16 ggc = pci_read_config16(mch, D0F0_GGC); if (!(ggc & 2)) { printk(BIOS_DEBUG, "IGD decoded, subtracting "); @@ -129,7 +131,7 @@ uma_sizek = gms_sizek + gsm_sizek; } - const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); + const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC); const u32 tseg_sizek = decode_tseg_size(esmramc); printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); tomk -= tseg_sizek; @@ -185,10 +187,12 @@ { u32 reg32; + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 = pci_read_config32(mch, PCI_COMMAND); reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config32(mch, PCI_COMMAND, reg32); } static struct device_operations pci_domain_ops = { -- To view, visit https://review.coreboot.org/27242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a Gerrit-Change-Number: 27242 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit June 2018