coreboot-gerrit June 2018

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Change in coreboot[master]: util/crossgcc: Allow building a new gcc against new binutils with -D
by Patrick Georgi (Code Review) 26 Jun '18

26 Jun '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/27241 Change subject: util/crossgcc: Allow building a new gcc against new binutils with -D ...................................................................... util/crossgcc: Allow building a new gcc against new binutils with -D With -D, the newly built toolchain isn't installed into $prefix/... but into $DESTDIR/$prefix/... while being built for $prefix alone. This is useful for distributions, but it breaks down when the build host already has the toolchain installed in $prefix without proper build isolation (cf. gentoo): In such cases libgcc etc are built using the new compiler (as gcc's build system is smart enough to state the path explicitly), but that compiler then uses its regular algorithm to determine the path to as, ld, ... That makes it use the tools from $prefix, which might differ in formats (assembly, certain object file flags, ...): nds32le-elf in particular has rather unstable formats still, and so new compilers can't work with old binutils. The approach to deal with this is to take an unused path that's specified by gcc's build system ($out/gcc/$arch/$version) and symlink it to the new toolchain - these explicitly given directories take precedence over the default search path, and so the new binutils are used. Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27241/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index cd8a091..ef0c4d5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -752,6 +752,8 @@ --with-mpc=$DESTDIR$TARGETDIR \ --with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \ && \ + mkdir -p gcc/$TARGETARCH && \ + ln -s $DESTDIR$TARGETDIR/$TARGETARCH/bin gcc/$TARGETARCH/$GCC_VERSION && \ $MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" all-gcc && \ $MAKE install-gcc DESTDIR=$DESTDIR || touch .failed -- To view, visit https://review.coreboot.org/27241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed Gerrit-Change-Number: 27241 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

1 0

Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

1 0

Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26132 ) Change subject: soc/intel/common/block: Move p2sb common functions into block/p2sb ...................................................................... Patch Set 47: (8 comments) https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c File src/soc/intel/skylake/p2sb.c: https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@23 PS47, Line 23: if (count != P2SB_EP_MASK_MAX_REG) { code indent should use tabs where possible https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@23 PS47, Line 23: if (count != P2SB_EP_MASK_MAX_REG) { please, no spaces at the start of a line https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@24 PS47, Line 24: printk(BIOS_ERR, "Unable to program EPMASK registers\n"); code indent should use tabs where possible https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@24 PS47, Line 24: printk(BIOS_ERR, "Unable to program EPMASK registers\n"); please, no spaces at the start of a line https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@25 PS47, Line 25: return; code indent should use tabs where possible https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@25 PS47, Line 25: return; please, no spaces at the start of a line https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@26 PS47, Line 26: } code indent should use tabs where possible https://review.coreboot.org/#/c/26132/47/src/soc/intel/skylake/p2sb.c@26 PS47, Line 26: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/26132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Gerrit-Change-Number: 26132 Gerrit-PatchSet: 47 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Jun 2018 16:58:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

1 0

Change in coreboot[master]: google/grunt: revert "stoneyridge: Move agesa out of bootblock"
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27240 ) Change subject: google/grunt: revert "stoneyridge: Move agesa out of bootblock" ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75365/ : SUCCESS -- To view, visit https://review.coreboot.org/27240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e30e3a5625f83778c9a217d79b8fef36736c5a1 Gerrit-Change-Number: 27240 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 15:29:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: google/grunt: revert "stoneyridge: Move agesa out of bootblock"
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27240 ) Change subject: google/grunt: revert "stoneyridge: Move agesa out of bootblock" ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29415/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75364/ : SUCCESS -- To view, visit https://review.coreboot.org/27240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e30e3a5625f83778c9a217d79b8fef36736c5a1 Gerrit-Change-Number: 27240 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Jun 2018 14:57:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: revert "stoneyridge: Move agesa out of bootblock"
by Kevin Chiu (Code Review) 26 Jun '18

26 Jun '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27240 Change subject: google/grunt: revert "stoneyridge: Move agesa out of bootblock" ...................................................................... google/grunt: revert "stoneyridge: Move agesa out of bootblock" with CL:26478, test FAFT firmware_CorruptFwSigB on Grunt/Careena will cause BIOS FW crash and it can only recover by re-flash BIOS. so reverts CL:26478 to fix FAFT firmware_CorruptFwSigB test fail. BUG=none BRANCH=master TEST=emerge-grunt coreboot run FAFT firmware_CorruptFwSigB and pass Change-Id: I6e30e3a5625f83778c9a217d79b8fef36736c5a1 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/romstage.c 2 files changed, 57 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27240/1 diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 7b2c420..d431c43 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -73,6 +73,27 @@ CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); } +/* + * To move AGESA calls to romstage, just move agesa_call() and bsp_agesa_call() + * to romstage.c. Also move the call to bsp_agesa_call() to the marked location + * in romstage.c. + */ +static void agesa_call(void) +{ + post_code(0x37); + do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + + post_code(0x38); + /* APs will not exit amdinitearly */ + do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); +} + +static void bsp_agesa_call(void) +{ + set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ + agesa_call(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { amd_initmmio(); @@ -97,6 +118,37 @@ post_code(0x90); } +/* + * This step is in bootblock because the SMU FW1 must be loaded prior to + * issuing any reset to the system. Set up just enough to get the command + * to the PSP. A side effect of placing this step here is we will always + * load a RO version of FW1 and never a RW version. + * + * todo: If AMD develops a more robust methodology, move this function to + * romstage. + */ +static void load_smu_fw1(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into "BAR3" and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); +} + void bootblock_soc_init(void) { if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) @@ -106,6 +158,11 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + load_smu_fw1(); + + bsp_agesa_call(); + /* Initialize any early i2c buses. */ i2c_soc_early_init(); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 78472d3..a742cd0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -41,44 +41,6 @@ /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); -} - -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -99,12 +61,6 @@ console_init(); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); - - - bsp_agesa_call(); - mainboard_romstage_entry(s3_resume); if (!s3_resume) { -- To view, visit https://review.coreboot.org/27240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e30e3a5625f83778c9a217d79b8fef36736c5a1 Gerrit-Change-Number: 27240 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: intel/common/pch/i2c: Move i2c file to common PCH
by Maulik V Vaghela (Code Review) 26 Jun '18

26 Jun '18

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/26729 ) Change subject: intel/common/pch/i2c: Move i2c file to common PCH ...................................................................... Abandoned Abandoning since changes are already part of another patch. -- To view, visit https://review.coreboot.org/26729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I333ca3f3e96505993c81fd3113c68d1f92b8f1b8 Gerrit-Change-Number: 26729 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review) 26 Jun '18

26 Jun '18

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coreboot-gerrit June 2018