coreboot-gerrit June 2018

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Change in coreboot[master]: mb/asus/x555la: Add new mainboard (NOT WORKING)
by Angel Pons (Code Review) 27 Jun '18

27 Jun '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/27256 Change subject: mb/asus/x555la: Add new mainboard (NOT WORKING) ...................................................................... mb/asus/x555la: Add new mainboard (NOT WORKING) This is a Haswell laptop which happens to not have Intel Boot Guard. This has been based off google/slippy. This change also affects some Haswell files to ease debugging. It adds several printk() calls and works around bugs in SPI flashconsole and monotonic timer. This laptop shares the SPI flash with the EC, whose firmware is at the beginning of the BIOS region defined by the flash descriptor and is 128K in size. Currently the laptop tries to initialize the onboard RAM with one of the provided SPD files (from the Google chromebook files) and mrc.bin does not return an error, but testing the memory results in a hang. Due to lack of proper flashing hardware I have to put this aside. Working: Embedded Controller firmware, flashconsole. Not working: Everything else. Change-Id: I361c1f06ed8d5c61ee7fa0f25e3ec93f292a3296 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/romstage.c M src/lib/ramtest.c A src/mainboard/asus/x555la/Kconfig A src/mainboard/asus/x555la/Kconfig.name A src/mainboard/asus/x555la/Makefile.inc A src/mainboard/asus/x555la/acpi/ec.asl A src/mainboard/asus/x555la/acpi/haswell_pci_irqs.asl A src/mainboard/asus/x555la/acpi/mainboard.asl A src/mainboard/asus/x555la/acpi/platform.asl A src/mainboard/asus/x555la/acpi/superio.asl A src/mainboard/asus/x555la/acpi/thermal.asl.OFF A src/mainboard/asus/x555la/acpi_tables.c A src/mainboard/asus/x555la/board_info.txt A src/mainboard/asus/x555la/cmos.layout A src/mainboard/asus/x555la/devicetree.cb A src/mainboard/asus/x555la/dsdt.asl A src/mainboard/asus/x555la/fadt.c A src/mainboard/asus/x555la/gma-mainboard.ads A src/mainboard/asus/x555la/gpio.h A src/mainboard/asus/x555la/hda_verb.c A src/mainboard/asus/x555la/mainboard.c A src/mainboard/asus/x555la/romstage.c A src/mainboard/asus/x555la/spd/.hSamsung_M471B5674QH0.spdex A src/mainboard/asus/x555la/spd/Elpida_EDJ4216EFBG.spd.hex A src/mainboard/asus/x555la/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/asus/x555la/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/asus/x555la/spd/Samsung_K4B4G1646B.spd.hex A src/mainboard/asus/x555la/spd/Samsung_K4B4G1646Q.spd.hex A src/mainboard/asus/x555la/spd/Samsung_M471B5674QH0.spd.hex A src/mainboard/asus/x555la/thermal.h 32 files changed, 1,635 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27256/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 423966c..368fee9 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,7 +10,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select HAVE_MONOTONIC_TIMER + #select HAVE_MONOTONIC_TIMER select SMP select MMX select SSE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bbd98da..eae9a80 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,14 +7,14 @@ ramstage-y += acpi.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-y += monotonic_timer.c +#ramstage-y += monotonic_timer.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c -smm-y += monotonic_timer.c +#smm-y += monotonic_timer.c cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 0e91dae..3fd389f 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -83,6 +83,7 @@ void romstage_common(const struct romstage_params *params) { + printk(BIOS_EMERG, "Romstage begins...\n"); int boot_mode; int wake_from_s3; @@ -94,6 +95,7 @@ wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + printk(BIOS_EMERG, "Report BIST failure...\n"); /* Halt if there was a built in self test failure */ report_bist_failure(params->bist); @@ -125,20 +127,24 @@ timestamp_add_now(TS_BEFORE_INITRAM); + printk(BIOS_EMERG, "RAM INIT will start now...\n"); report_platform_info(); if (params->copy_spd != NULL) params->copy_spd(params->pei_data); sdram_initialize(params->pei_data); + printk(BIOS_EMERG, "RAM INIT worked properly...\n"); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3b); intel_early_me_status(); + printk(BIOS_EMERG, "ME status worked properly\n"); quick_ram_check(); + printk(BIOS_EMERG, "RAM check worked properly...\n"); post_code(0x3e); if (!wake_from_s3) { diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 461a028..d1e13b1 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -186,30 +186,41 @@ { int fail = 0; u32 backup; + printk(BIOS_EMERG, "RAM CHECK START!\n"); backup = read_phys(dst); write_phys(dst, 0x55555555); phys_memory_barrier(); + printk(BIOS_EMERG, "RAM CYCLE 1!\n"); if (read_phys(dst) != 0x55555555) fail = 1; + printk(BIOS_EMERG, "RAM TEST 1!\n"); write_phys(dst, 0xaaaaaaaa); phys_memory_barrier(); + printk(BIOS_EMERG, "RAM CYCLE 2!\n"); if (read_phys(dst) != 0xaaaaaaaa) fail = 1; + printk(BIOS_EMERG, "RAM TEST 2!\n"); write_phys(dst, 0x00000000); phys_memory_barrier(); + printk(BIOS_EMERG, "RAM CYCLE 3!\n"); if (read_phys(dst) != 0x00000000) fail = 1; + printk(BIOS_EMERG, "RAM TEST 3!\n"); write_phys(dst, 0xffffffff); phys_memory_barrier(); + printk(BIOS_EMERG, "RAM CYCLE 4!\n"); if (read_phys(dst) != 0xffffffff) fail = 1; + printk(BIOS_EMERG, "RAM TEST 4!\n"); write_phys(dst, backup); if (fail) { post_code(0xea); die("RAM INIT FAILURE!\n"); } + printk(BIOS_EMERG, "RAM INIT SUCCESS!\n"); phys_memory_barrier(); + printk(BIOS_EMERG, "RAM INIT END!\n"); } void quick_ram_check(void) diff --git a/src/mainboard/asus/x555la/Kconfig b/src/mainboard/asus/x555la/Kconfig new file mode 100644 index 0000000..d7f4c9a --- /dev/null +++ b/src/mainboard/asus/x555la/Kconfig @@ -0,0 +1,82 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_X555LA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_HASWELL + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select INTEL_INT15 + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_LIBGFXINIT + select TSC_MONOTONIC_TIMER + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default asus/x555la + +config MAINBOARD_PART_NUMBER + string + default "X555LA" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +##config VGA_BIOS_ID + ##string + ##default "8086,0a16" + +##config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + ##hex + ##default 0x21dd + +##config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + ##hex + ##default 0x17aa + +##config DRAM_RESET_GATE_GPIO + ##int + ##default 60 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_ASUS_X555LA diff --git a/src/mainboard/asus/x555la/Kconfig.name b/src/mainboard/asus/x555la/Kconfig.name new file mode 100644 index 0000000..d9ed9ad --- /dev/null +++ b/src/mainboard/asus/x555la/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_X555LA + bool "X555LA" diff --git a/src/mainboard/asus/x555la/Makefile.inc b/src/mainboard/asus/x555la/Makefile.inc new file mode 100644 index 0000000..7d0bc4e --- /dev/null +++ b/src/mainboard/asus/x555la/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +## DIMM SPD for on-board memory +#SPD_BIN = $(obj)/spd.bin + +## Order of names in SPD_SOURCES is important! +#SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 +#SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 +#SPD_SOURCES += Samsung_K4B4G1646B # 2: 4GB / CH0 + CH1 +#SPD_SOURCES += Samsung_K4B4G1646Q # 1: 4GB / CH0 + CH1 +#SPD_SOURCES += Samsung_M471B5674QH0 # 0: 4GB / CH0 + CH1 +#SPD_SOURCES += Micron_4KTF25664HZ # 3: 2GB / CH0 +#SPD_SOURCES += Hynix_HMT425S6AFR6A # 4: 2GB / CH0 +#SPD_SOURCES += Samsung_K4B4G1646B # 4: 2GB / CH0 +#SPD_SOURCES += Samsung_K4B4G1646Q # 4: 2GB / CH0 + CH1 +#SPD_SOURCES += Samsung_M471B5674QH0 # 3: 2GB / CH0 + CH1 + +#SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +#$(SPD_BIN): $(SPD_DEPS) + #for f in $+; \ + #do for c in $$(cat $$f | grep -v ^#); \ + #do printf $$(printf '\%o' 0x$$c); \ + #done; \ + #done > $@ + +#cbfs-files-y += spd.bin +#spd.bin-file := $(SPD_BIN) +#spd.bin-type := spd diff --git a/src/mainboard/asus/x555la/acpi/ec.asl b/src/mainboard/asus/x555la/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/x555la/acpi/haswell_pci_irqs.asl b/src/mainboard/asus/x555la/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..0900a3d --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/haswell_pci_irqs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for Haswell */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} diff --git a/src/mainboard/asus/x555la/acpi/mainboard.asl b/src/mainboard/asus/x555la/acpi/mainboard.asl new file mode 100644 index 0000000..fa2b153 --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/mainboard.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (CTPA) + { + Name (_HID, "CYAP0000") + Name (_DDN, "Cypress Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x67, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/asus/x555la/acpi/platform.asl b/src/mainboard/asus/x555la/acpi/platform.asl new file mode 100644 index 0000000..270464e --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/platform.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/x555la/acpi/superio.asl b/src/mainboard/asus/x555la/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/x555la/acpi/thermal.asl.OFF b/src/mainboard/asus/x555la/acpi/thermal.asl.OFF new file mode 100644 index 0000000..0c694c0 --- /dev/null +++ b/src/mainboard/asus/x555la/acpi/thermal.asl.OFF @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +#define HAVE_THERMALZONE +Scope (\_TZ) +{ + // Handler for throttle requests on this platform + // 0 = Stop throttling + // 1 = Start throttling + Method (THRT, 1, Serialized) + { + If (LEqual (Arg0, 0)) { + /* Disable Power Limit */ + \_SB.PCI0.MCHC.CTLD () + } Else { + /* Enable Power Limit */ + \_SB.PCI0.MCHC.CTLE (\F0PW) + } + } + + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (TCHK, 0, Serialized) + { + // Get Temperature from TIN# set in NVS + Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + + // Check for sensor not calibrated + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (CTOK(0)) + } + + // Check for sensor not present + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (CTOK(0)) + } + + // Check for sensor not powered + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (CTOK(0)) + } + + // Check for sensor bad reading + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (CTOK(0)) + } + + // Adjust by offset to get Kelvin + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + // Convert to 1/10 Kelvin + Multiply (Local0, 10, Local0) + Return (Local0) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from EC in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TCRT), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for EC to re-poll + Sleep (1000) + + // Re-read temperature from EC + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + } +} diff --git a/src/mainboard/asus/x555la/acpi_tables.c b/src/mainboard/asus/x555la/acpi_tables.c new file mode 100644 index 0000000..ec97c1d --- /dev/null +++ b/src/mainboard/asus/x555la/acpi_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC *//* + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0);*/ + + /* INT_SRC_OVR *//* + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); +*/ + + return current; +} diff --git a/src/mainboard/asus/x555la/board_info.txt b/src/mainboard/asus/x555la/board_info.txt new file mode 100644 index 0000000..fc1d86e --- /dev/null +++ b/src/mainboard/asus/x555la/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: ASUS +Board name: X555LA +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/asus/x555la/cmos.layout b/src/mainboard/asus/x555la/cmos.layout new file mode 100644 index 0000000..c2cbdbc --- /dev/null +++ b/src/mainboard/asus/x555la/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/x555la/devicetree.cb b/src/mainboard/asus/x555la/devicetree.cb new file mode 100644 index 0000000..7466ed4 --- /dev/null +++ b/src/mainboard/asus/x555la/devicetree.cb @@ -0,0 +1,122 @@ +chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 04.0 on end # Thermal + + chip southbridge/intel/lynxpoint + #register "pirqa_routing" = "0x8b" + #register "pirqb_routing" = "0x8a" + #register "pirqc_routing" = "0x8b" + #register "pirqd_routing" = "0x8b" + #register "pirqe_routing" = "0x80" + #register "pirqf_routing" = "0x80" + #register "pirqg_routing" = "0x80" + #register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + #register "gen1_dec" = "0x00fc0801" + #register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + #register "alt_gp_smi_en" = "0x0004" + #register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + #register "gpe0_en_2" = "0x00000010" + #register "gpe0_en_3" = "0x00000000" + #register "gpe0_en_4" = "0x00000000" + + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x33" + #register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + #register "sata_port0_gen3_dtle" = "0x5" + #register "sata_port1_gen3_dtle" = "0x5" + + #register "sio_acpi_mode" = "1" + #register "sio_i2c0_voltage" = "0" # 3.3V + #register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 1 + #register "pcie_port_force_aspm" = "0x01" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + #register "icc_clock_disable" = "0x013c0000" + + #device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/asus/x555la/dsdt.asl b/src/mainboard/asus/x555la/dsdt.asl new file mode 100644 index 0000000..4e64020 --- /dev/null +++ b/src/mainboard/asus/x555la/dsdt.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // Thermal handler + //#include "acpi/thermal.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <cpu/intel/haswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + +/* + Scope (\_SB.PCI0.RP01) + { + Device (WLAN) + { + Name (_ADR, Zero) + } + } +*/ + + // Mainboard specific + //#include "acpi/mainboard.asl" + + // Chipset specific sleep states + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/x555la/fadt.c b/src/mainboard/asus/x555la/fadt.c new file mode 100644 index 0000000..fe50215 --- /dev/null +++ b/src/mainboard/asus/x555la/fadt.c @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + //u16 pmbase = get_pmbase(); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; +/* + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +*/ + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/asus/x555la/gma-mainboard.ads b/src/mainboard/asus/x555la/gma-mainboard.ads new file mode 100644 index 0000000..338f1fc --- /dev/null +++ b/src/mainboard/asus/x555la/gma-mainboard.ads @@ -0,0 +1,38 @@ +-- +-- Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely + -- have a high-resolution display attached first, `Internal` last. + + -- #FIXME: Check what is actually used + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/x555la/gpio.h b/src/mainboard/asus/x555la/gpio.h new file mode 100644 index 0000000..8e24b3a --- /dev/null +++ b/src/mainboard/asus/x555la/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X555LA_GPIO_H +#define X555LA_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_PIRQ, + LP_GPIO_UNUSED, + LP_GPIO_ACPI_SCI, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_ACPI_SCI, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_OUT_LOW, + LP_GPIO_UNUSED, + LP_GPIO_ACPI_SCI, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_ACPI_SMI, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_OUT_HIGH, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_OUT_LOW, + LP_GPIO_UNUSED, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_LOW, + LP_GPIO_INPUT, + LP_GPIO_UNUSED, + LP_GPIO_OUT_HIGH, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_INPUT, + LP_GPIO_INPUT, + LP_GPIO_INPUT, + LP_GPIO_INPUT, + LP_GPIO_OUT_HIGH, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_UNUSED, + LP_GPIO_INPUT_INVERT, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_NATIVE, + LP_GPIO_NATIVE, + LP_GPIO_OUT_LOW, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_LOW, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_HIGH, + LP_GPIO_OUT_LOW, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_UNUSED, + LP_GPIO_END +}; + +#endif diff --git a/src/mainboard/asus/x555la/hda_verb.c b/src/mainboard/asus/x555la/hda_verb.c new file mode 100644 index 0000000..56fe320 --- /dev/null +++ b/src/mainboard/asus/x555la/hda_verb.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000e, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60110), + + /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ + // group 1, cap 0 + // no connector, no jack detect + // speaker out, analog + // fixed function, internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ + // group2, cap 0 + // black, jack detect + // Mic in, 3.5mm Jack + // connector, External left panel + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020), + + /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* Pin Complex (NID 0x1B) LINE2 - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, Internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ + // group2, cap 1 + // black, jack detect + // HPOut, 3.5mm Jack + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x03211021), + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/x555la/mainboard.c b/src/mainboard/asus/x555la/mainboard.c new file mode 100644 index 0000000..22b8c97 --- /dev/null +++ b/src/mainboard/asus/x555la/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <types.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/x555la/romstage.c b/src/mainboard/asus/x555la/romstage.c new file mode 100644 index 0000000..ece10b2 --- /dev/null +++ b/src/mainboard/asus/x555la/romstage.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include "gpio.h" +#include <timer.h> + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory *//* +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + char *spd_file; + size_t spd_file_len; + size_t spd_len = sizeof(peid->spd_data[0]); + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + //die("SPD data not found."); + printk(BIOS_EMERG, "EMERGENCY: SPD data not found.\n"); + + if (spd_file_len < ((spd_index + 1) * spd_len)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < spd_len) + //die("Missing SPD data."); + printk(BIOS_EMERG, "EMERGENCY: Missing SPD data.\n"); + + memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + + + switch (spd_index) { + case 0: case 1: case 2: + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); + break; + case 3: case 4: case 5: + peid->dimm_channel1_disabled = 3; + } +}*/ + /* Index 0-2, are 4GB config with both CH0 and CH1 + * Index 3-5, are 2GB config with CH0 only + */ + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + //.spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + //.ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + .copy_spd = NULL, + //.copy_spd = copy_spd, + }; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/asus/x555la/spd/.hSamsung_M471B5674QH0.spdex b/src/mainboard/asus/x555la/spd/.hSamsung_M471B5674QH0.spdex new file mode 100644 index 0000000..c2a23cd --- /dev/null +++ b/src/mainboard/asus/x555la/spd/.hSamsung_M471B5674QH0.spdex @@ -0,0 +1,17 @@ +# Samsung M471B5674QH0-YK0 (K4B4G1646Q) +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asus/x555la/spd/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/asus/x555la/spd/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asus/x555la/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/asus/x555la/spd/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asus/x555la/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/asus/x555la/spd/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646B.spd.hex b/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646B.spd.hex new file mode 100644 index 0000000..fb529d0 --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646B.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646B-HYXX +92 11 0B 03 04 19 02 02 03 11 01 08 0C 00 3E 00 +69 78 69 3C 69 11 20 89 20 08 3C 3C 01 68 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 2A E3 +4D 34 37 31 42 35 36 37 34 42 48 30 2D 43 48 39 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646Q.spd.hex b/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646Q.spd.hex new file mode 100644 index 0000000..d6b0770 --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Samsung_K4B4G1646Q.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646Q-HYK0 +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/asus/x555la/spd/Samsung_M471B5674QH0.spd.hex b/src/mainboard/asus/x555la/spd/Samsung_M471B5674QH0.spd.hex new file mode 100644 index 0000000..c2a23cd --- /dev/null +++ b/src/mainboard/asus/x555la/spd/Samsung_M471B5674QH0.spd.hex @@ -0,0 +1,17 @@ +# Samsung M471B5674QH0-YK0 (K4B4G1646Q) +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asus/x555la/thermal.h b/src/mainboard/asus/x555la/thermal.h new file mode 100644 index 0000000..921bbfc --- /dev/null +++ b/src/mainboard/asus/x555la/thermal.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 99 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif -- To view, visit https://review.coreboot.org/27256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I361c1f06ed8d5c61ee7fa0f25e3ec93f292a3296 Gerrit-Change-Number: 27256 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

1 0

Change in coreboot[master]: amd/common/pi: Remove obsolete heapmanager workaround
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27254 ) Change subject: amd/common/pi: Remove obsolete heapmanager workaround ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29471/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75420/ : SUCCESS -- To view, visit https://review.coreboot.org/27254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Gerrit-Change-Number: 27254 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 17:11:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/common/pi: Remove AGESA support files from bootblock
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27255 ) Change subject: amd/common/pi: Remove AGESA support files from bootblock ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29472/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75421/ : SUCCESS -- To view, visit https://review.coreboot.org/27255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Gerrit-Change-Number: 27255 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 17:08:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/common/pi: Remove AGESA support files from bootblock
by Marshall Dawson (Code Review) 27 Jun '18

27 Jun '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27255 Change subject: amd/common/pi: Remove AGESA support files from bootblock ...................................................................... amd/common/pi: Remove AGESA support files from bootblock The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/Makefile.inc 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27255/1 diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index f5f1f99..65386f2 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -1,9 +1,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y) -bootblock-y += agesawrapper.c -bootblock-y += def_callouts.c -bootblock-y += heapmanager.c - romstage-y += agesawrapper.c romstage-y += def_callouts.c romstage-y += heapmanager.c -- To view, visit https://review.coreboot.org/27255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Gerrit-Change-Number: 27255 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/common/pi: Remove obsolete heapmanager workaround
by Marshall Dawson (Code Review) 27 Jun '18

27 Jun '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27254 Change subject: amd/common/pi: Remove obsolete heapmanager workaround ...................................................................... amd/common/pi: Remove obsolete heapmanager workaround Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/heapmanager.c 1 file changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27254/1 diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 63db1ce..cbffb77 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -73,17 +73,9 @@ AGESA_REBASE_PARAMS *Rebase; Rebase = (AGESA_REBASE_PARAMS *)ConfigPtr; - if (ENV_BOOTBLOCK) { + Rebase->HeapAddress = (UINTN)agesa_heap_base(); + if (!Rebase->HeapAddress) Rebase->HeapAddress = CONFIG_PI_AGESA_CAR_HEAP_BASE; - } else { - /* - * todo: remove the if() above and keep the assignment here - * once all AGESA functions are removed from bootblock. - */ - Rebase->HeapAddress = (UINTN)agesa_heap_base(); - if (!Rebase->HeapAddress) - Rebase->HeapAddress = CONFIG_PI_AGESA_CAR_HEAP_BASE; - } return AGESA_SUCCESS; } -- To view, visit https://review.coreboot.org/27254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Gerrit-Change-Number: 27254 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivity
by Nick Vaccaro (Code Review) 27 Jun '18

27 Jun '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/27221 ) Change subject: mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivity ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27221/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/27221/1/src/mainboard/google/poppy/variants… PS1, Line 138: NONE > As mentioned in b/78613978#comment10 given this is an active-low interrupt, the pull-down is doing t […] If signal is active low, why did you change this definition from "_INVERT" ? IF it's a double-mapping issue with kernel, the kernel is where it should be changed, IMO; this file should map to how the hardware actually behaves. -- To view, visit https://review.coreboot.org/27221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335 Gerrit-Change-Number: 27221 Gerrit-PatchSet: 1 Gerrit-Owner: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 27 Jun 2018 16:46:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/*: Add a few VBT files
by Matt DeVillier (Code Review) 27 Jun '18

27 Jun '18

Matt DeVillier has submitted this change and it was merged. ( https://review.coreboot.org/27222 ) Change subject: mb/google/*: Add a few VBT files ...................................................................... mb/google/*: Add a few VBT files These files are directly extracted from the vendor firmware Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/27222 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/chell/Kconfig A src/mainboard/google/chell/data.vbt M src/mainboard/google/cyan/Kconfig A src/mainboard/google/cyan/variants/banon/data.vbt A src/mainboard/google/cyan/variants/celes/data.vbt A src/mainboard/google/cyan/variants/cyan/data.vbt A src/mainboard/google/cyan/variants/edgar/data.vbt A src/mainboard/google/cyan/variants/kefka/data.vbt A src/mainboard/google/cyan/variants/reks/data.vbt A src/mainboard/google/cyan/variants/relm/data.vbt A src/mainboard/google/cyan/variants/setzer/data.vbt A src/mainboard/google/cyan/variants/terra/data.vbt A src/mainboard/google/cyan/variants/ultima/data.vbt A src/mainboard/google/cyan/variants/wizpig/data.vbt M src/mainboard/google/eve/Kconfig A src/mainboard/google/eve/data.vbt M src/mainboard/google/fizz/Kconfig A src/mainboard/google/fizz/data.vbt M src/mainboard/google/lars/Kconfig A src/mainboard/google/lars/data.vbt 20 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index 9257b5a..2a8c237 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -15,6 +15,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/chell/data.vbt b/src/mainboard/google/chell/data.vbt new file mode 100644 index 0000000..a654a5e --- /dev/null +++ b/src/mainboard/google/chell/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index fdd6316..7520410 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -8,6 +8,7 @@ select ENABLE_BUILTIN_COM1 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/cyan/variants/banon/data.vbt b/src/mainboard/google/cyan/variants/banon/data.vbt new file mode 100644 index 0000000..0fa2d5e --- /dev/null +++ b/src/mainboard/google/cyan/variants/banon/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/celes/data.vbt b/src/mainboard/google/cyan/variants/celes/data.vbt new file mode 100644 index 0000000..0fa2d5e --- /dev/null +++ b/src/mainboard/google/cyan/variants/celes/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/cyan/data.vbt b/src/mainboard/google/cyan/variants/cyan/data.vbt new file mode 100644 index 0000000..0fa2d5e --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/edgar/data.vbt b/src/mainboard/google/cyan/variants/edgar/data.vbt new file mode 100644 index 0000000..90e6d25 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/kefka/data.vbt b/src/mainboard/google/cyan/variants/kefka/data.vbt new file mode 100644 index 0000000..23606e3 --- /dev/null +++ b/src/mainboard/google/cyan/variants/kefka/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/reks/data.vbt b/src/mainboard/google/cyan/variants/reks/data.vbt new file mode 100644 index 0000000..4d12712 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/relm/data.vbt b/src/mainboard/google/cyan/variants/relm/data.vbt new file mode 100644 index 0000000..296f2f7 --- /dev/null +++ b/src/mainboard/google/cyan/variants/relm/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/setzer/data.vbt b/src/mainboard/google/cyan/variants/setzer/data.vbt new file mode 100644 index 0000000..fa7087f --- /dev/null +++ b/src/mainboard/google/cyan/variants/setzer/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/terra/data.vbt b/src/mainboard/google/cyan/variants/terra/data.vbt new file mode 100644 index 0000000..3ad0cb3 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/ultima/data.vbt b/src/mainboard/google/cyan/variants/ultima/data.vbt new file mode 100644 index 0000000..4d12712 --- /dev/null +++ b/src/mainboard/google/cyan/variants/ultima/data.vbt Binary files differ diff --git a/src/mainboard/google/cyan/variants/wizpig/data.vbt b/src/mainboard/google/cyan/variants/wizpig/data.vbt new file mode 100644 index 0000000..0fa2d5e --- /dev/null +++ b/src/mainboard/google/cyan/variants/wizpig/data.vbt Binary files differ diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 9205651..a841f22 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -15,6 +15,7 @@ select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/eve/data.vbt b/src/mainboard/google/eve/data.vbt new file mode 100644 index 0000000..2f950c8 --- /dev/null +++ b/src/mainboard/google/eve/data.vbt Binary files differ diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 7b3ba45..c6e43d8 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -12,6 +12,7 @@ select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 diff --git a/src/mainboard/google/fizz/data.vbt b/src/mainboard/google/fizz/data.vbt new file mode 100644 index 0000000..dbbf475 --- /dev/null +++ b/src/mainboard/google/fizz/data.vbt Binary files differ diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index e9c27be..9f74fec 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -17,6 +17,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/lars/data.vbt b/src/mainboard/google/lars/data.vbt new file mode 100644 index 0000000..0aac82c --- /dev/null +++ b/src/mainboard/google/lars/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/27222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e Gerrit-Change-Number: 27222 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: drivers/intel/fsp1_1: Fix vbt_len type
by Matt DeVillier (Code Review) 27 Jun '18

27 Jun '18

Matt DeVillier has submitted this change and it was merged. ( https://review.coreboot.org/27224 ) Change subject: drivers/intel/fsp1_1: Fix vbt_len type ...................................................................... drivers/intel/fsp1_1: Fix vbt_len type Type of vbt_len should be size_t, change to fix compiler error Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/27224 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp1_1/vbt.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index b73d3a2..b6bb308 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -26,7 +26,7 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) { const optionrom_vbt_t *vbt_data = NULL; - uint32_t vbt_len; + size_t vbt_len; /* Check boot mode - for S3 resume path VBT loading is not needed */ if (s3_resume) { -- To view, visit https://review.coreboot.org/27224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9 Gerrit-Change-Number: 27224 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivity
by Vincent Palatin (Code Review) 27 Jun '18

27 Jun '18

Vincent Palatin has posted comments on this change. ( https://review.coreboot.org/27221 ) Change subject: mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivity ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27221/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/27221/1/src/mainboard/google/poppy/variants… PS1, Line 138: NONE > a 20k pulldown here would help for preEVT2 devices (preEVT2 is missing a pd in hw on this line; EVT2 […] As mentioned in b/78613978#comment10 given this is an active-low interrupt, the pull-down is doing the opposite of what we want, we would like a pull-up. -- To view, visit https://review.coreboot.org/27221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335 Gerrit-Change-Number: 27221 Gerrit-PatchSet: 1 Gerrit-Owner: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 27 Jun 2018 13:30:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek/mt8183: add PLL and clock init support
by build bot (Jenkins) (Code Review) 27 Jun '18

27 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27031 ) Change subject: mediatek/mt8183: add PLL and clock init support ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29469/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75419/ : SUCCESS -- To view, visit https://review.coreboot.org/27031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Gerrit-Change-Number: 27031 Gerrit-PatchSet: 9 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Jun 2018 12:52:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018