Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26883
Change subject: nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap region
......................................................................
nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap region
This binary needs to be at a specific offset and will therefore always
be located in the COREBOOT fmap region.
This will be useful with C_ENVIRONMENT_BOOTBLOCK where romstages in
FW_MAIN_x will still need the same binary.
Change-Id: Ia73d468ab23932f92331ef40b8e8066cef55af2c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/raminit.c
2 files changed, 16 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/26883/1
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 3a47195..692744b 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -84,4 +84,9 @@
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
+config RO_REGION_ONLY
+ string
+ depends on CHROMEOS
+ default "mrc.bin"
+
endif
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index e5e2b93..cdbb1a9 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -120,6 +120,9 @@
void sdram_initialize(struct pei_data *pei_data)
{
unsigned long entry;
+ uint32_t type = CBFS_TYPE_MRC;
+ struct cbfsf f;
+ size_t fsize;
printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
@@ -142,9 +145,14 @@
/* Pass console handler in pei_data */
pei_data->tx_byte = do_putchar;
- /* Locate and call UEFI System Agent binary. */
- entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin",
- CBFS_TYPE_MRC, NULL);
+ /*
+ * Locate and call UEFI System Agent binary. The binary needs to be at
+ * a fixed offset in the flash and can therefore only reside in the
+ * COREBOOT fmap region
+ */
+ cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type);
+ fsize = region_device_sz(&f.data);
+ entry = (unsigned long)rdev_mmap(&f.data, 0, fsize);
if (entry) {
int rv;
asm volatile (
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia73d468ab23932f92331ef40b8e8066cef55af2c
Gerrit-Change-Number: 26883
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Subrata Banik has abandoned this change. ( https://review.coreboot.org/26882 )
Change subject: soc/intel/{apollolake, geminilake}: Rectify GSPI device name
......................................................................
Abandoned
i believe first documentation need to be fixed before this CL goes.
APL and GLK EDS are not in sync in terms of explaining the nomenclature between SPI and GSPI
According to the EDS, SPI 0(19.0), SPI 1(19.1) and SPI 2(19.2).
--
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Gerrit-Change-Id: Iff540eefa5e93b8ad86916745705b48e99cc6767
Gerrit-Change-Number: 26882
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26862 )
Change subject: cbfstool: Show current FMAP region in print
......................................................................
Patch Set 2:
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/74385/ : SUCCESS
--
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Gerrit-Change-Number: 26862
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Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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Gerrit-Comment-Date: Wed, 06 Jun 2018 07:49:44 +0000
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