coreboot-gerrit April 2018

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Change in coreboot[master]: drivers/i2c/adm1026: Remove unneeded headers
by Felix Held (Code Review) 26 Apr '18

26 Apr '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/25867 ) Change subject: drivers/i2c/adm1026: Remove unneeded headers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaed9c0882847511642d8eaab25e10d1ecf24bf90 Gerrit-Change-Number: 25867 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:29:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/i2c/lm63: Remove unneeded headers
by Felix Held (Code Review) 26 Apr '18

26 Apr '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/25868 ) Change subject: drivers/i2c/lm63: Remove unneeded headers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id13eef7f0fca0b929372490859aa4734ea7a9f23 Gerrit-Change-Number: 25868 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:29:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: southbridge/intel: Remove space before/after parenthesis
by Elyes HAOUAS (Code Review) 26 Apr '18

26 Apr '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25880 Change subject: southbridge/intel: Remove space before/after parenthesis ...................................................................... southbridge/intel: Remove space before/after parenthesis Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/acpi/serialio.asl M src/southbridge/intel/lynxpoint/lpc.c 13 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/25880/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8d125eb..ea7a808 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -239,7 +239,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 73366f7..f17a44f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -249,7 +249,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 8a815c5..3a17701 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -249,7 +249,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index cbb2297..b9af406 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -270,7 +270,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 305da2a..cef36e9 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -29,11 +29,11 @@ /* 8259-compatible Programmable Interrupt Controller */ Device (PIC) { - Name (_HID, EisaId ("PNP0000") ) + Name (_HID, EisaId ("PNP0000")) Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, ) - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, ) + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02,) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02,) IRQNoFlags () {2} }) } @@ -41,10 +41,10 @@ /* PC-class DMA Controller */ Device (DMA1) { - Name (_HID, EisaId ("PNP0200") ) + Name (_HID, EisaId ("PNP0200")) Name (_CRS, ResourceTemplate () { - DMA (Compatibility, BusMaster, Transfer8, ) {4} + DMA (Compatibility, BusMaster, Transfer8,) {4} IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,) IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,) IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,) @@ -66,7 +66,7 @@ /* AT Real-Time Clock */ Device (RTC) { - Name (_HID, EisaId ("PNP0B00") ) + Name (_HID, EisaId ("PNP0B00")) Name (_CRS, ResourceTemplate () { IO (Decode16,0x0070,0x0070,0x01,0x04,) @@ -86,7 +86,7 @@ /* x87-compatible Floating Point Processing Unit */ Device (COPR) { - Name (_HID, EisaId ("PNP0C04") ) + Name (_HID, EisaId ("PNP0C04")) Name (_CRS, ResourceTemplate () { IO (Decode16,0x00F0,0x00F0,0x01,0x10,) diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 3477c52..5b95c57 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -68,7 +68,7 @@ * power-on default is 0x7fffbfffh */ if (gpo) { /* only 8bit access allowed */ - outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb(gpo & 0xff, DEFAULT_PMBASE + GPO0); outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index 3ed83b7..f9a7904 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -220,7 +220,7 @@ mbar = pci_read_config16(dev, MBAR) & 0xfffe; reg16 = inw(mmbar + EXT_MODEM_ID1); - if ((reg16 & 0xc000) != 0xc000 ) { + if ((reg16 & 0xc000) != 0xc000) { if (reg16 & (1 << 0)) { reg32 = inw(mmbar + VENDOR_ID2); reg32 <<= 16; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 3502c8b..0f0bbcf 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -155,7 +155,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Disable NMI. */ + reg8 |= (1 << 7); /* Disable NMI. */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bc45b9d..abc8667 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -227,7 +227,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 18025ff..c631da9 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -229,7 +229,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 559ad06..857a53e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -231,7 +231,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index e8e81c3..9323b91 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -131,7 +131,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} }) Method (_CRS, 0, NotSerialized) @@ -172,7 +172,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -254,7 +254,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -333,7 +333,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} }) Method (_CRS, 0, NotSerialized) @@ -371,7 +371,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -422,7 +422,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -473,7 +473,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} }) Method (_CRS, 0, NotSerialized) @@ -511,7 +511,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5} }) Method (_CRS, 0, NotSerialized) @@ -560,7 +560,7 @@ , // ResourceSource BAR0) Interrupt (ResourceConsumer, - Level, ActiveHigh, Shared, , , ) {14} + Level, ActiveHigh, Shared, , ,) {14} }) Method (_CRS, 0, NotSerialized) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2e37950..d1d00c6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -247,7 +247,7 @@ reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); -- To view, visit https://review.coreboot.org/25880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e Gerrit-Change-Number: 25880 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: southbridge/nvidia: Remove spaces before/after parenthesis
by build bot (Jenkins) (Code Review) 26 Apr '18

26 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25879 ) Change subject: southbridge/nvidia: Remove spaces before/after parenthesis ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25040/ : SUCCESS -- To view, visit https://review.coreboot.org/25879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94a87d631c9336b861523592ff217fe823436b36 Gerrit-Change-Number: 25879 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:23:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: southbridge/nvidia: Remove spaces before/after parenthesis
by Elyes HAOUAS (Code Review) 26 Apr '18

26 Apr '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25879 Change subject: southbridge/nvidia: Remove spaces before/after parenthesis ...................................................................... southbridge/nvidia: Remove spaces before/after parenthesis Change-Id: I94a87d631c9336b861523592ff217fe823436b36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/ck804/acpi/ck804.asl M src/southbridge/nvidia/mcp55/early_setup_car.c M src/southbridge/nvidia/mcp55/lpc.c M src/southbridge/nvidia/mcp55/smbus.h 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/25879/1 diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl index aac7ea8..4a83b84 100644 --- a/src/southbridge/nvidia/ck804/acpi/ck804.asl +++ b/src/southbridge/nvidia/ck804/acpi/ck804.asl @@ -54,7 +54,7 @@ /* set "B", external (PCI) APIC interrupts */ Name (PRSB, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 16, 17, 18, 19, } }) @@ -93,7 +93,7 @@ /* set "C", southbridge APIC interrupts */ Name (PRSC, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 20, 21, 22, 23, } }) diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 8019a8e..6ddd59e 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -83,7 +83,7 @@ }; int j; - for (j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++) { setup_resource_map_offset(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); @@ -100,7 +100,7 @@ }; int j; - for (j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++) { setup_resource_map_offset(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index eeb6c1b..180b9a8 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -131,7 +131,7 @@ if (nmi_option) byte &= ~(1 << 7); /* Set NMI. */ else - byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ + byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ if (byte != byte_old) outb(byte, 0x70); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index a588a09..274ccfe 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -45,7 +45,7 @@ smbus_delay(); val = inb(smbus_io_base + SMBHSTSTAT); - if ( (val & 0xff) != 0) { + if ((val & 0xff) != 0) { return 0; } } while (--loops); -- To view, visit https://review.coreboot.org/25879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I94a87d631c9336b861523592ff217fe823436b36 Gerrit-Change-Number: 25879 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/southbridge/sis/sis966/nic.c: Improve code formatting
by build bot (Jenkins) (Code Review) 26 Apr '18

26 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25872 ) Change subject: src/southbridge/sis/sis966/nic.c: Improve code formatting ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70838/ : SUCCESS -- To view, visit https://review.coreboot.org/25872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08 Gerrit-Change-Number: 25872 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:18:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode
by Daisuke Nojiri (Code Review) 26 Apr '18

26 Apr '18

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/25878 Change subject: cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode ...................................................................... cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port is connected to a device with alternate mode(s) and the call is made for the mode with the index higher than 0 (e.g. Zinger). This patch adds delay between calls to the EC to query alternate mode information. This allows the EC to process each call properly. It also resets all the fields of chromeec_command in each iteration in case google_chromeec_command changes them. BUG=b:78630899 BRANCH=none TEST=Verify Fizz boots without monitors on Zinger. Verify the svid enumeration happens as expected. Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/25878/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index fb3ffab..9676f2d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -963,23 +963,28 @@ for (i = 0; i < r.num_ports; i++) { struct ec_params_usb_pd_get_mode_request p; struct ec_params_usb_pd_get_mode_response res; - - p.port = i; - p.svid_idx = 0; - cmd.cmd_code = EC_CMD_USB_PD_GET_AMODE; - cmd.cmd_version = 0; - cmd.cmd_data_in = &p; - cmd.cmd_size_in = sizeof(p); - cmd.cmd_data_out = &res; - cmd.cmd_size_out = sizeof(res); - cmd.cmd_dev_index = 0; + int svid_idx = 0; do { + /* Reset cmd in each iteration in case + * google_chromeec_command changes it. */ + p.port = i; + p.svid_idx = svid_idx; + cmd.cmd_code = EC_CMD_USB_PD_GET_AMODE; + cmd.cmd_version = 0; + cmd.cmd_data_in = &p; + cmd.cmd_size_in = sizeof(p); + cmd.cmd_data_out = &res; + cmd.cmd_size_out = sizeof(res); + cmd.cmd_dev_index = 0; + if (google_chromeec_command(&cmd) < 0) return -1; if (res.svid == svid) return 1; - p.svid_idx++; + svid_idx++; + /* Avoid storming EC */ + mdelay(100); } while (res.svid); } -- To view, visit https://review.coreboot.org/25878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Gerrit-Change-Number: 25878 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: src/southbridge/sis/sis966/nic.c: Improve code formatting
by build bot (Jenkins) (Code Review) 26 Apr '18

26 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25872 ) Change subject: src/southbridge/sis/sis966/nic.c: Improve code formatting ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25026/ : SUCCESS -- To view, visit https://review.coreboot.org/25872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08 Gerrit-Change-Number: 25872 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:02:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/southbridge/sis/sis966/nic.c: Improve code formatting
by build bot (Jenkins) (Code Review) 26 Apr '18

26 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25872 ) Change subject: src/southbridge/sis/sis966/nic.c: Improve code formatting ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70837/ : ABORTED -- To view, visit https://review.coreboot.org/25872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08 Gerrit-Change-Number: 25872 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 20:02:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/southbridge/sis/sis966/nic.c: Improve code formatting
by build bot (Jenkins) (Code Review) 26 Apr '18

26 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25872 ) Change subject: src/southbridge/sis/sis966/nic.c: Improve code formatting ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/25025/ : SUCCESS -- To view, visit https://review.coreboot.org/25872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08 Gerrit-Change-Number: 25872 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Apr 2018 19:57:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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