coreboot-gerrit April 2018

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Change in coreboot[master]: commonlib/storage: Make pci sdhci code compile in romstage
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25067 ) Change subject: commonlib/storage: Make pci sdhci code compile in romstage ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23722/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69401/ : SUCCESS -- To view, visit https://review.coreboot.org/25067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Gerrit-Change-Number: 25067 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 03 Apr 2018 21:46:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: commonlib/storage: Make sd_mmc_go_idle an api
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25066 ) Change subject: commonlib/storage: Make sd_mmc_go_idle an api ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23720/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69399/ : SUCCESS -- To view, visit https://review.coreboot.org/25066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I064a9bded347be5d500047df92d1c448c3392016 Gerrit-Change-Number: 25066 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 03 Apr 2018 21:42:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
by Bora Guvendik (Code Review) 03 Apr '18

03 Apr '18

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25514 Change subject: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK ...................................................................... soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK In order to improve boot time via emmc, enable Intel common code that sends CMD0 and CMD1 early in firmware. Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/early_mmc.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/romstage.c 5 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25514/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index fcb1ef7..4ff3369 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -10,6 +10,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_EARLY_MMC_WAKE help Intel GLK support diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 65df559..f1b056d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -90,6 +90,7 @@ romstage-y += gpio_glk.c smm-y += gpio_glk.c ramstage-y += gpio_glk.c +romstage-y += early_mmc.c else bootblock-y += gpio_apl.c romstage-y += gpio_apl.c diff --git a/src/soc/intel/apollolake/early_mmc.c b/src/soc/intel/apollolake/early_mmc.c new file mode 100644 index 0000000..9761da0 --- /dev/null +++ b/src/soc/intel/apollolake/early_mmc.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "chip.h" +#include <intelblocks/early_mmc.h> +#include <intelblocks/gpio.h> +#include <soc/pci_devs.h> + + +static const struct pad_config mmc_early_gpios[] = { + PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ + PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/ + PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/ + PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/ + PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/ + PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/ + PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/ + PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/ + PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/ + PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/ + PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/ + PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/ + PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0)/*EMMC0_STROBE*/ +}; + +int soc_set_mmc_gpios(void) +{ + gpio_configure_pads(&mmc_early_gpios[0], ARRAY_SIZE(mmc_early_gpios)); + + return 0; +} + +void soc_get_mmc_frequencies(uint32_t* f_min, uint32_t* f_max) +{ + *f_min = 400000; + *f_max = 25000000; +} + +int soc_set_mmc_dll(struct mmc_dll_params* params) +{ + const struct device *dev = SA_DEV_ROOT; + const struct soc_intel_apollolake_config *config = dev->chip_info; + + params->emmc_tx_data_cntl1 = config->emmc_tx_data_cntl1; + params->emmc_tx_data_cntl2 = config->emmc_tx_data_cntl2; + params->emmc_rx_cmd_data_cntl1 = config->emmc_rx_cmd_data_cntl1; + params->emmc_rx_cmd_data_cntl2 = config->emmc_rx_cmd_data_cntl2; + params->emmc_rx_strobe_cntl = config->emmc_rx_strobe_cntl; + params->emmc_tx_cmd_cntl = config->emmc_tx_cmd_cntl; + + return 0; +} diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 7e6a795..a912c3b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -49,6 +49,7 @@ /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 +#define PRERAM_MMC_BASE_ADDRESS 0xfe030000 /* Temporary BAR for early I2C bus access */ #define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index a8a0dd1..77f4af4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -52,6 +52,7 @@ #include <delay.h> #include <compiler.h> #include "chip.h" +#include <intelblocks/early_mmc.h> static const uint8_t hob_variable_guid[16] = { 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, @@ -198,6 +199,11 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE)) { + if (early_mmc_wake_hw() < 0) + printk(BIOS_DEBUG, "Early mmc initilization failed \n"); + } + if (punit_init()) set_max_freq(); else -- To view, visit https://review.coreboot.org/25514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d Gerrit-Change-Number: 25514 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25513 ) Change subject: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69398/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23719/ : SUCCESS -- To view, visit https://review.coreboot.org/25513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2664fc66a55b3b5cb8997114a8622a47181dd911 Gerrit-Change-Number: 25513 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Apr 2018 21:28:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message
by Nico Huber (Code Review) 03 Apr '18

03 Apr '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25513 Change subject: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message ...................................................................... WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message Change-Id: I2664fc66a55b3b5cb8997114a8622a47181dd911 --- M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/devicetree.cb M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 5 files changed, 170 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/25513/1 diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index 5a9e570..da1afb4 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -74,6 +74,8 @@ # coreboot config options: cpu #424 8 r 0 unused +424 1 e 1 request_hmrfpo + # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index bed406a..fe05a50 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -76,7 +76,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index a5c5e52..1b88a3d 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -27,6 +27,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include <string.h> #include <delay.h> #include <elog.h> @@ -458,39 +459,6 @@ } #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - printk(BIOS_NOTICE, "ME: Requesting global reset\n"); - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - #ifdef __SMM__ static void intel_me7_finalize_smm(void) { @@ -543,6 +511,75 @@ } #else /* !__SMM__ */ +static int mkhi_hmrfpo_enable(void) +{ + u64 send = 0; + struct { + u64 unknown; + u32 status; + } receive; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_HMRFPO, + .command = MKHI_HMRFPO_ENABLE, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(send), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + if (mei_sendrecv(&mei, &mkhi, &send, &receive, sizeof(receive)) < 0) { + printk(BIOS_ERR, "ME: HMRFPO ENABLE message failed\n"); + return -1; + } + + if (receive.status != 0) { + printk(BIOS_ERR, "ME: HMRFPO ENABLE returned with error\n"); + return -1; + } + + return 0; +} + +static int mkhi_hmrfpo_disable(void) +{ + return -1; +} + +/* Tell ME to issue a global reset */ +static int mkhi_global_reset(void) +{ + struct me_global_reset reset = { + .request_origin = GLOBAL_RESET_BIOS_POST, + .reset_type = CBM_RR_GLOBAL_RESET, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(reset), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printk(BIOS_NOTICE, "ME: Requesting global reset\n"); + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { + /* No response means reset will happen shortly... */ + halt(); + } + + /* If the ME responded it rejected the reset request */ + printk(BIOS_ERR, "ME: Global Reset failed\n"); + return -1; +} + /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(device_t dev) { @@ -697,6 +734,9 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(device_t dev) { + u8 request_hmrfpo = 0; + struct me_hfs hfs; + me_bios_path path = intel_me_path(dev); /* Do initial setup and determine the BIOS path */ @@ -716,6 +756,17 @@ if (intel_mei_setup(dev) < 0) break; + /* Unlock ME if requested. */ + get_option(&request_hmrfpo, "request_hmrfpo"); + if (request_hmrfpo) { + /* Unlock ME flash region */ + if (mkhi_hmrfpo_enable() == 0) { + /* Issue global reset */ + mkhi_global_reset(); + return; + } + } + #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Print ME firmware version */ mkhi_get_fw_version(); @@ -729,9 +780,22 @@ */ break; + case ME_DISABLE_BIOS_PATH: + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_OVER_MEI) { + mkhi_hmrfpo_disable(); + get_option(&request_hmrfpo, "request_hmrfpo"); + if (request_hmrfpo) { + request_hmrfpo = 0; + set_option("request_hmrfpo", &request_hmrfpo); + } else { + mkhi_global_reset(); + } + } + break; + case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index f95a0b4..0f68d6a 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -181,6 +181,7 @@ #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_HMRFPO 0x05 #define MKHI_GROUP_ID_MDES 0x08 #define MKHI_GROUP_ID_GEN 0xff @@ -188,6 +189,10 @@ #define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_HMRFPO_ENABLE 0x01 +#define MKHI_HMRFPO_LOCK 0x02 +#define MKHI_HMRFPO_DISABLE 0x04 + #define MKHI_MDES_ENABLE 0x09 #define MKHI_GET_FW_VERSION 0x02 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 6463f96..1e040d2 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -27,6 +27,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include <string.h> #include <delay.h> #include <elog.h> @@ -425,7 +426,45 @@ } #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#ifndef __SMM__ +static int mkhi_hmrfpo_enable(void) +{ + u64 send = 0; + struct { + u64 unknown; + u32 status; + } receive; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_HMRFPO, + .command = MKHI_HMRFPO_ENABLE, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(send), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + if (mei_sendrecv(&mei, &mkhi, &send, &receive, sizeof(receive)) < 0) { + printk(BIOS_ERR, "ME: HMRFPO ENABLE message failed\n"); + return -1; + } + + if (receive.status != 0) { + printk(BIOS_ERR, "ME: HMRFPO ENABLE returned with error\n"); + return -1; + } + + return 0; +} + +static int mkhi_hmrfpo_disable(void) +{ + return -1; +} + /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -686,6 +725,8 @@ { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; + u8 request_hmrfpo = 0; + struct me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); @@ -707,19 +748,16 @@ if (intel_me_read_mbp(&mbp_data)) break; -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ - /* - * Unlock ME in recovery mode. - */ - if (vboot_recovery_mode_enabled()) { + /* Unlock ME if requested. */ + get_option(&request_hmrfpo, "request_hmrfpo"); + if (request_hmrfpo) { /* Unlock ME flash region */ - mkhi_hmrfpo_enable(); - - /* Issue global reset */ - mkhi_global_reset(); - return; + if (mkhi_hmrfpo_enable() == 0) { + /* Issue global reset */ + mkhi_global_reset(); + return; + } } -#endif #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(&mbp_data.fw_version_name); @@ -732,9 +770,22 @@ */ break; + case ME_DISABLE_BIOS_PATH: + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_OVER_MEI) { + mkhi_hmrfpo_disable(); + get_option(&request_hmrfpo, "request_hmrfpo"); + if (request_hmrfpo) { + request_hmrfpo = 0; + set_option("request_hmrfpo", &request_hmrfpo); + } else { + mkhi_global_reset(); + } + } + break; + case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } -- To view, visit https://review.coreboot.org/25513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2664fc66a55b3b5cb8997114a8622a47181dd911 Gerrit-Change-Number: 25513 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/amd/gardenia/gpio.c: Convert GPIO to new format
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25512 ) Change subject: mb/amd/gardenia/gpio.c: Convert GPIO to new format ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23718/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69397/ : SUCCESS -- To view, visit https://review.coreboot.org/25512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Gerrit-Change-Number: 25512 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Apr 2018 20:22:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: configure RAPL PL1/PL2
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25511 ) Change subject: mb/google/octopus: configure RAPL PL1/PL2 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23717/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69396/ : SUCCESS -- To view, visit https://review.coreboot.org/25511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If75d94587af63f604dd95e184252e13d1b05d4af Gerrit-Change-Number: 25511 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Apr 2018 20:17:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/amd/gardenia/gpio.c: Convert GPIO to new format
by Richard Spiegel (Code Review) 03 Apr '18

03 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25512 Change subject: mb/amd/gardenia/gpio.c: Convert GPIO to new format ...................................................................... mb/amd/gardenia/gpio.c: Convert GPIO to new format New macros were developed that replace previous way of defining GPIO, with pin and intention very clear while keeping the table mostly identical to previous method (there's no pull up or pull down when a GPIO is set as an output). Change current gardenia table to use the new macros. BUG=b:72875858 TEST=Build Gardenia. Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/25512/1 diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index c274a76..cb10e74 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -28,34 +28,34 @@ */ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { /* NFC PU */ - {GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_64, HIGH), /* PCIe presence detect */ - {GPIO_69, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_69, PULL_UP), /* MUX for Power Express Eval */ - {GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + PAD_GPI(GPIO_116, PULL_DOWN), /* SD power */ - {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_119, HIGH), /* GPIO_136 - UART0_FCH_RX_DEBUG_RX */ - {GPIO_136, Function0, INPUT }, + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* GPIO_137 - UART0_FCH_DEBUG_RTS */ - {GPIO_137, Function0, INPUT }, + PAD_NF(GPIO_137, UART0_RTS_L, PULL_NONE), /* GPIO_138 - UART0_FCH_TX_DEBUG_RX */ - {GPIO_138, Function0, INPUT }, + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* GPIO_142 - UART1_FCH_RTS */ - {GPIO_142, Function0, INPUT }, + PAD_NF(GPIO_142, UART1_RTS_L, PULL_NONE), /* GPIO_143 - UART1_FCH_TX */ - {GPIO_143, Function0, INPUT }, + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), }; const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { /* BT radio disable */ - {GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_14, HIGH), /* NFC wake */ - {GPIO_65, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_65, HIGH), /* Webcam */ - {GPIO_66, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_66, HIGH), /* GPS sleep */ - {GPIO_70, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + PAD_GPO(GPIO_70, HIGH), }; const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 0f7ec1b..2c3555b 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -223,8 +223,13 @@ #define GPIO_40_IOMUX_GPIOxx 0 #define GPIO_42_IOMUX_S5_MUX_CTRL 0 #define GPIO_42_IOMUX_GPIOxx 1 +#define GPIO_64_IOMUX_GPIOxx 0 +#define GPIO_65_IOMUX_GPIOxx 0 +#define GPIO_66_IOMUX_GPIOxx 0 #define GPIO_67_IOMUX_GPIOxx 0 #define GPIO_67_IOMUX_DEVSLP0 1 +#define GPIO_69_IOMUX_GPIOxx 0 +#define GPIO_69_IOMUX_SGPIO_LOAD 1 #define GPIO_70_IOMUX_GPIOxx 0 #define GPIO_70_IOMUX_DEVSLP1 1 #define GPIO_74_IOMUX_LPCCLK0 0 -- To view, visit https://review.coreboot.org/25512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Gerrit-Change-Number: 25512 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/octopus: configure RAPL PL1/PL2
by Hannah Williams (Code Review) 03 Apr '18

03 Apr '18

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/25511 Change subject: mb/google/octopus: configure RAPL PL1/PL2 ...................................................................... mb/google/octopus: configure RAPL PL1/PL2 Change-Id: If75d94587af63f604dd95e184252e13d1b05d4af Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/25511/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 1174d2c..77e5f2b 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -57,6 +57,12 @@ register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_NW_31_0" + # Set RAPL PL1 to 8W. + register "tdp_pl1_override_mw" = "8000" + + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" -- To view, visit https://review.coreboot.org/25511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If75d94587af63f604dd95e184252e13d1b05d4af Gerrit-Change-Number: 25511 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com>

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Change in coreboot[master]: [do not merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 03 Apr '18

03 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [do not merge] add i945G based mainboard ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69395/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23716/ : SUCCESS -- To view, visit https://review.coreboot.org/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Apr 2018 15:58:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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