coreboot-gerrit April 2018

coreboot-gerrit@coreboot.org

1 participants
2168 discussions

Change in coreboot[master]: mainboard: Add ASUS Maximus IV GENE-Z
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24971 ) Change subject: mainboard: Add ASUS Maximus IV GENE-Z ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69496/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23812/ : SUCCESS -- To view, visit https://review.coreboot.org/24971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Gerrit-Change-Number: 24971 Gerrit-PatchSet: 4 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 07:14:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: fsp_broadwell_de: Provide valid address and size for DCACHE range
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25535 ) Change subject: fsp_broadwell_de: Provide valid address and size for DCACHE range ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69494/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23811/ : SUCCESS -- To view, visit https://review.coreboot.org/25535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Gerrit-Change-Number: 25535 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 07:10:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: fsp_broadwell_de: Provide valid ACPI path names for domain and LPC
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25534 ) Change subject: fsp_broadwell_de: Provide valid ACPI path names for domain and LPC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69495/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23810/ : SUCCESS -- To view, visit https://review.coreboot.org/25534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Gerrit-Change-Number: 25534 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 07:07:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: fsp_broadwell_de: Provide valid address and size for DCACHE range
by Werner Zeh (Code Review) 05 Apr '18

05 Apr '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/25535 Change subject: fsp_broadwell_de: Provide valid address and size for DCACHE range ...................................................................... fsp_broadwell_de: Provide valid address and size for DCACHE range On Broadwell-DE the FSP sets up DCACHE in the early call. The address does not match the default FSP 1.0 address defined in src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range is used in pre-ramstage stages. This patch provides the matching DCACHE_RAM_BASE value among with a suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation. The include order of Kconfig files makes sure that the Kconfig file in the soc directory is sourced first and the defined values will override the ones in src/drivers/intel/fsp1_0/Kconfig. Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/fsp/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/25535/1 diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig index 2e1ebeb..4301be5 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig @@ -21,6 +21,22 @@ The Broadwell-DE FSP is built with a preferred base address of 0xffeb0000. +config DCACHE_RAM_BASE + hex + default 0xfe100000 + help + This address needs to match the setup performed inside FSP. + On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000. + +config DCACHE_RAM_SIZE + hex + default 0x8000 + help + The DCACHE is shared between FSP itself and the rest of the coreboot + stages. A size of 0x8000 works fine while provides enough space for + features like VBOOT in verstage. Further increase to a power of two align + value leads to errors in FSP. + config FSP_MEMORY_DOWN bool "Enable Memory Down" default n -- To view, visit https://review.coreboot.org/25535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Gerrit-Change-Number: 25535 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

1 0

Change in coreboot[master]: fsp_broadwell_de: Provide valid ACPI path names for domain and LPC
by Werner Zeh (Code Review) 05 Apr '18

05 Apr '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/25534 Change subject: fsp_broadwell_de: Provide valid ACPI path names for domain and LPC ...................................................................... fsp_broadwell_de: Provide valid ACPI path names for domain and LPC Provide ACPI path names for PCI domain and LPC device so that generated ACPI tables have valid device paths. Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/chip.c M src/soc/intel/fsp_broadwell_de/southcluster.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25534/1 diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index b8db395..118fb99 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -30,6 +30,15 @@ assign_resources(dev->link_list); } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static const char *domain_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + return NULL; +} +#endif + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, @@ -37,6 +46,9 @@ .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = domain_acpi_name +#endif }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 3bf5429..8ad27af 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -263,6 +263,16 @@ } } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static const char *lpc_acpi_name(const struct device *dev) +{ + if (dev->path.pci.devfn == LPC_DEV_FUNC) + return "LPC0"; + else + return NULL; +} +#endif + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, @@ -271,6 +281,9 @@ .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = lpc_acpi_name, +#endif }; static const struct pci_driver southcluster __pci_driver = { -- To view, visit https://review.coreboot.org/25534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Gerrit-Change-Number: 25534 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

1 0

Change in coreboot[master]: soc/intel/common: Add funtion to modify PAT & NXE bit
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25480 ) Change subject: soc/intel/common: Add funtion to modify PAT & NXE bit ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69493/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23809/ : SUCCESS -- To view, visit https://review.coreboot.org/25480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Gerrit-Change-Number: 25480 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 05:42:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/amd/stoneyridege: Create util.c
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25533 ) Change subject: soc/amd/stoneyridege: Create util.c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69485/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23802/ : SUCCESS -- To view, visit https://review.coreboot.org/25533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6 Gerrit-Change-Number: 25533 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 22:27:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/amd/stoneyridege: Create util.c
by Richard Spiegel (Code Review) 05 Apr '18

05 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25533 Change subject: soc/amd/stoneyridege: Create util.c ...................................................................... soc/amd/stoneyridege: Create util.c As part of moving AGESA calls from bootblock to romstage, code was created to read and write to NB IOAPIC. This code should be generalized and made available to anyone. Create file util.c to store the generalized code. Make code available at bootblock, romstage, postcar, verstage, ramstage and smm. BUG=b:74236170 TEST=Build and boot grunt. Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/romstage.c A src/soc/amd/stoneyridge/util.c 5 files changed, 63 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25533/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 61704ea..afdf679 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -48,7 +48,7 @@ bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += sb_util.c +bootblock-y += util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -66,6 +66,7 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c +romstage-y += util.c verstage-y += gpio.c verstage-y += i2c.c @@ -75,11 +76,13 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c +verstage-y += util.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c postcar-y += sb_util.c +postcar-y += util.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c @@ -108,6 +111,7 @@ ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c +ramstage-y += util.c smm-y += monotonic_timer.c smm-y += smihandler.c @@ -116,6 +120,7 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c +smm-y += util.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 8f1ac5d..404e24b 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -30,13 +30,6 @@ #include <amdblocks/psp.h> #include <timestamp.h> -static uintptr_t get_ap_ptr(void) -{ - /* Use the first IOAPIC scratch register */ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - /* Set the MMIO Configuration Base Address and Bus Range. */ static void amd_initmmio(void) { diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 6e42b39..547383d 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -30,10 +30,23 @@ /* NB IOAPIC registers */ #define NB_IOAPIC_INDEX 0xf8 #define NB_IOAPIC_DATA 0xfc -#define NB_IOAPIC_ADDRESS 0x01 +#define NB_IOAPIC_FEATURE_CTRL 0x00 +#define NB_IOAPIC_ADDRESS_LOW 0x01 +#define NB_IOAPIC_ADDRESS_HIGH 0x02 +#define NB_IOAPIC_GBIF_IRR 0x0f +#define NB_IOAPIC_BR0_IRR 0x10 +#define NB_IOAPIC_BR1_IRR 0x11 +#define NB_IOAPIC_BR2_IRR 0x12 +#define NB_IOAPIC_BR3_IRR 0x13 +#define NB_IOAPIC_BR4_IRR 0x14 +#define NB_IOAPIC_APG_IRR 0x2f +#define NB_IOAPIC_SPG_IRR 0x30 +#define NB_IOAPIC_SER_IRQ_IRR 0x31 #define NB_IOAPIC_SCRATCH0 0x3e #define NB_IOAPIC_SCRATCH1 0x3f +#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 + /* D18F1 - Address Map Registers */ /* MMIO base and limit */ @@ -95,5 +108,9 @@ void domain_set_resources(device_t dev); void fam15_finalize(void *chip_info); void setup_uma_memory(void); +uint32_t nb_ioapic_read(uint32_t index); +void nb_ioapic_write(uint32_t index, uint32_t value); +uintptr_t get_ap_ptr(void); +void set_ap_ptr(void *entry); #endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 7911079..2b3452d 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -34,13 +34,6 @@ #include <amdblocks/psp.h> #include <smp/node.h> -static void set_ap_ptr(void *entry) -{ - /* Use the first IOAPIC scratch register */ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, (u32)entry); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; diff --git a/src/soc/amd/stoneyridge/util.c b/src/soc/amd/stoneyridge/util.c new file mode 100644 index 0000000..302bc3f --- /dev/null +++ b/src/soc/amd/stoneyridge/util.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/northbridge.h> +#include <soc/pci_devs.h> + +uint32_t nb_ioapic_read(uint32_t index) +{ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); + return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); +} + +void nb_ioapic_write(uint32_t index, uint32_t value) +{ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); +} + +uintptr_t get_ap_ptr(void) +{ + return nb_ioapic_read(AP_SCRATCH_REG); +} + +void set_ap_ptr(void *entry) +{ + nb_ioapic_write(AP_SCRATCH_REG, (u32)entry); +} -- To view, visit https://review.coreboot.org/25533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6 Gerrit-Change-Number: 25533 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25513 ) Change subject: WIP: sb/intel/bd82x6x/me: Try implementing HMRFPO message ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69484/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23801/ : SUCCESS -- To view, visit https://review.coreboot.org/25513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2664fc66a55b3b5cb8997114a8622a47181dd911 Gerrit-Change-Number: 25513 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 22:06:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/apollolake: Configuring WiFi PCI device ID 0:13.0 for GLK
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25532 ) Change subject: soc/intel/apollolake: Configuring WiFi PCI device ID 0:13.0 for GLK ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69483/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23800/ : SUCCESS -- To view, visit https://review.coreboot.org/25532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5 Gerrit-Change-Number: 25532 Gerrit-PatchSet: 1 Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 21:54:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2018