coreboot-gerrit April 2018

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Change in coreboot[master]: soc/amd: Add "halt this AP" callback to romstage
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25527 ) Change subject: soc/amd: Add "halt this AP" callback to romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69478/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23795/ : SUCCESS -- To view, visit https://review.coreboot.org/25527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0992b2de5856881c19191ec4f637168727686524 Gerrit-Change-Number: 25527 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 20:43:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Make OemCustomize.c available at romstage
by Richard Spiegel (Code Review) 04 Apr '18

04 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25528 Change subject: mainboard: Make OemCustomize.c available at romstage ...................................................................... mainboard: Make OemCustomize.c available at romstage As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/Makefile.inc M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc M src/mainboard/google/kahlee/variants/kahlee/Makefile.inc 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/25528/1 diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index fe3a8c8..f09bf18 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += bootblock/OemCustomize.c bootblock-y += gpio.c +romstage-y += OemCustomize.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index c4c2f9d..1f6d8ce 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -18,6 +18,7 @@ verstage-y += tpm_tis.c +romstage-y += OemCustomize.c romstage-y += gpio.c romstage-y += memory.c romstage-y += tpm_tis.c diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc index fcaf365..ab91501 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += gpio.c bootblock-y += OemCustomize.c +romstage-y += OemCustomize.c romstage-y += gpio.c romstage-y += memory.c -- To view, visit https://review.coreboot.org/25528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Gerrit-Change-Number: 25528 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd: Add "halt this AP" callback to romstage
by Richard Spiegel (Code Review) 04 Apr '18

04 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25527 Change subject: soc/amd: Add "halt this AP" callback to romstage ...................................................................... soc/amd: Add "halt this AP" callback to romstage As part of moving AGESA calls from bootblock to romstage, callback function AGESA_HALT_THIS_AP must be available at romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: I0992b2de5856881c19191ec4f637168727686524 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/cpu/Makefile.inc M src/soc/amd/common/block/pi/def_callouts.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25527/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index fed208a..395ab08 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -4,4 +4,5 @@ postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index beb2d18..fec1776 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -35,6 +35,9 @@ #else const BIOS_CALLOUT_STRUCT BiosCallouts[] = { /* Required callouts */ +#if ENV_ROMSTAGE + { AGESA_HALT_THIS_AP, agesa_HaltThisAp }, +#endif { AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, { AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, { AGESA_DO_RESET, agesa_Reset }, -- To view, visit https://review.coreboot.org/25527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0992b2de5856881c19191ec4f637168727686524 Gerrit-Change-Number: 25527 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridege: Create AP jump structure
by Richard Spiegel (Code Review) 04 Apr '18

04 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25526 Change subject: soc/amd/stoneyridege: Create AP jump structure ...................................................................... soc/amd/stoneyridege: Create AP jump structure As part of moving AGESA calls from bootblock to romstage, create infrastructure to pass a pointer to the AP cores, so they can jump directly to romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/romstage.c 3 files changed, 62 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25526/1 diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index fafaf07..8f1ac5d 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -30,19 +30,11 @@ #include <amdblocks/psp.h> #include <timestamp.h> -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +static uintptr_t get_ap_ptr(void) { - /* - * Call lib/bootblock.c main with BSP, shortcut for APs - * todo: rearchitect AGESA entry points to remove need - * to run amdinitreset, amdinitearly from bootblock. - * Remove AP shortcut. - */ - if (!boot_cpu()) - bootblock_soc_early_init(); /* APs will not return */ - - /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_timestamp(timestamp_get()); + /* Use the first IOAPIC scratch register */ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0); + return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); } /* Set the MMIO Configuration Base Address and Bus Range. */ @@ -65,10 +57,43 @@ set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } -void bootblock_soc_early_init(void) +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { amd_initmmio(); + /* + * Call lib/bootblock.c main with BSP, shortcut for APs + */ + if (!boot_cpu()) { + /* + * Before AGESA is moved to romstage, AP cores will + * reach this code before BSP can set the jump address, + * so ap_romstage_entry will be NULL. + */ + void (*ap_romstage_entry)(void) = (void (*)(void))get_ap_ptr(); + /* + * TODO: Once AGESA calls are moved to romstage, remove + * this section of code. + */ + if (ap_romstage_entry == NULL) + bootblock_soc_early_init(); /* APs will not return */ + + printk(BIOS_DEBUG, "AP calling directly to romstage @%p\n", + ap_romstage_entry); + ap_romstage_entry(); /* execution does not return */ + } + + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_timestamp(timestamp_get()); +} + +void bootblock_soc_early_init(void) +{ + /* + * TODO: Once AGESA calls are moved to romstage, remove the + * if and bootblock_soc_init() as APs will never execute + * bootblock_soc_early_init(). + */ if (!boot_cpu()) bootblock_soc_init(); /* APs will not return */ @@ -117,6 +142,10 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + /* + * TODO: Once AGESA calls are moved to romstage, remove boot_cpu() + * from the if as APs will never execute bootblock_soc_init(). + */ if (boot_cpu() && IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d649ada..6e42b39 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -27,6 +27,13 @@ #define HT_INIT_CONTROL 0x6c # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) +/* NB IOAPIC registers */ +#define NB_IOAPIC_INDEX 0xf8 +#define NB_IOAPIC_DATA 0xfc +#define NB_IOAPIC_ADDRESS 0x01 +#define NB_IOAPIC_SCRATCH0 0x3e +#define NB_IOAPIC_SCRATCH1 0x3f + /* D18F1 - Address Map Registers */ /* MMIO base and limit */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 490fd9e..7911079 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <arch/cpu.h> #include <arch/acpi.h> #include <cpu/x86/msr.h> @@ -31,6 +32,14 @@ #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> +#include <smp/node.h> + +static void set_ap_ptr(void *entry) +{ + /* Use the first IOAPIC scratch register */ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, (u32)entry); +} asmlinkage void car_stage_entry(void) { @@ -45,7 +54,10 @@ int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); int i; - console_init(); + if (boot_cpu()) { + console_init(); + set_ap_ptr(car_stage_entry); + } if (!s3_resume) { post_code(0x40); -- To view, visit https://review.coreboot.org/25526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 Gerrit-Change-Number: 25526 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel EC
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25479 ) Change subject: mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel EC ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69476/ : SUCCESS -- To view, visit https://review.coreboot.org/25479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567 Gerrit-Change-Number: 25479 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 18:21:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: docker/coreboot-sdk: Add device-tree-compiler
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25525 ) Change subject: docker/coreboot-sdk: Add device-tree-compiler ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69475/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23793/ : SUCCESS -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 14:04:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: docker/coreboot-sdk: Add device-tree-compiler
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25525 ) Change subject: docker/coreboot-sdk: Add device-tree-compiler ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69474/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/23792/ : ABORTED -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 13:59:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: docker/coreboot-sdk: Add device-tree-compiler
by Patrick Rudolph (Code Review) 04 Apr '18

04 Apr '18

Patrick Rudolph has uploaded a new patch set (#2). ( https://review.coreboot.org/25525 ) Change subject: docker/coreboot-sdk: Add device-tree-compiler ...................................................................... docker/coreboot-sdk: Add device-tree-compiler Add dtc to Dockerimage for Jenkins. Untested. Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25525/2 -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: docker/coreboot-jenkins-node: Add device-tree-compiler
by Patrick Rudolph (Code Review) 04 Apr '18

04 Apr '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25525 Change subject: docker/coreboot-jenkins-node: Add device-tree-compiler ...................................................................... docker/coreboot-jenkins-node: Add device-tree-compiler Add dtc to dockerimage for Jenkins. Untested. Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25525/1 diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 230842c..875a1ec 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -22,7 +22,7 @@ RUN apt-get -y update && \ apt-get -y install \ - lua5.3 liblua5.3-dev openjdk-8-jre-headless openssh-server && \ + device-tree-compiler lua5.3 liblua5.3-dev openjdk-8-jre-headless openssh-server && \ apt-get clean # Because of the way that the variables are being replaced, docker's 'COPY' -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Be verbose
by build bot (Jenkins) (Code Review) 04 Apr '18

04 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25449 ) Change subject: mb/cavium/cn8100_sff_evb: Be verbose ...................................................................... Patch Set 7: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69471/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23789/ : SUCCESS -- To view, visit https://review.coreboot.org/25449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1 Gerrit-Change-Number: 25449 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Apr 2018 13:28:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit April 2018